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radeonsi: put up to 5 VBO descriptors into user SGPRs
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_compute.h"
28 #include "util/format/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
34 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
35
36 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
37 SI_SAVE_FRAGMENT_STATE,
38
39 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
40 SI_DISABLE_RENDER_COND,
41
42 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
43 };
44
45 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op)
46 {
47 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
48 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
49 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
50 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
51 util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets,
52 (struct pipe_stream_output_target**)sctx->streamout.targets);
53 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
54
55 if (op & SI_SAVE_FRAGMENT_STATE) {
56 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
57 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
58 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
59 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
60 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask);
61 util_blitter_save_scissor(sctx->blitter, &sctx->scissors[0]);
62 util_blitter_save_window_rectangles(sctx->blitter,
63 sctx->window_rectangles_include,
64 sctx->num_window_rectangles,
65 sctx->window_rectangles);
66 }
67
68 if (op & SI_SAVE_FRAMEBUFFER)
69 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
70
71 if (op & SI_SAVE_TEXTURES) {
72 util_blitter_save_fragment_sampler_states(
73 sctx->blitter, 2,
74 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
75
76 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
77 sctx->samplers[PIPE_SHADER_FRAGMENT].views);
78 }
79
80 if (op & SI_DISABLE_RENDER_COND)
81 sctx->render_cond_force_off = true;
82
83 if (sctx->screen->dpbb_allowed) {
84 sctx->dpbb_force_off = true;
85 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
86 }
87 }
88
89 void si_blitter_end(struct si_context *sctx)
90 {
91 if (sctx->screen->dpbb_allowed) {
92 sctx->dpbb_force_off = false;
93 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
94 }
95
96 sctx->render_cond_force_off = false;
97
98 /* Restore shader pointers because the VS blit shader changed all
99 * non-global VS user SGPRs. */
100 sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX);
101 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
102 sctx->vertex_buffer_user_sgprs_dirty = sctx->num_vertex_elements > 0;
103 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
104 }
105
106 static unsigned u_max_sample(struct pipe_resource *r)
107 {
108 return r->nr_samples ? r->nr_samples - 1 : 0;
109 }
110
111 static unsigned
112 si_blit_dbcb_copy(struct si_context *sctx,
113 struct si_texture *src,
114 struct si_texture *dst,
115 unsigned planes, unsigned level_mask,
116 unsigned first_layer, unsigned last_layer,
117 unsigned first_sample, unsigned last_sample)
118 {
119 struct pipe_surface surf_tmpl = {{0}};
120 unsigned layer, sample, checked_last_layer, max_layer;
121 unsigned fully_copied_levels = 0;
122
123 if (planes & PIPE_MASK_Z)
124 sctx->dbcb_depth_copy_enabled = true;
125 if (planes & PIPE_MASK_S)
126 sctx->dbcb_stencil_copy_enabled = true;
127 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
128
129 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
130
131 sctx->decompression_enabled = true;
132
133 while (level_mask) {
134 unsigned level = u_bit_scan(&level_mask);
135
136 /* The smaller the mipmap level, the less layers there are
137 * as far as 3D textures are concerned. */
138 max_layer = util_max_layer(&src->buffer.b.b, level);
139 checked_last_layer = MIN2(last_layer, max_layer);
140
141 surf_tmpl.u.tex.level = level;
142
143 for (layer = first_layer; layer <= checked_last_layer; layer++) {
144 struct pipe_surface *zsurf, *cbsurf;
145
146 surf_tmpl.format = src->buffer.b.b.format;
147 surf_tmpl.u.tex.first_layer = layer;
148 surf_tmpl.u.tex.last_layer = layer;
149
150 zsurf = sctx->b.create_surface(&sctx->b, &src->buffer.b.b, &surf_tmpl);
151
152 surf_tmpl.format = dst->buffer.b.b.format;
153 cbsurf = sctx->b.create_surface(&sctx->b, &dst->buffer.b.b, &surf_tmpl);
154
155 for (sample = first_sample; sample <= last_sample; sample++) {
156 if (sample != sctx->dbcb_copy_sample) {
157 sctx->dbcb_copy_sample = sample;
158 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
159 }
160
161 si_blitter_begin(sctx, SI_DECOMPRESS);
162 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
163 sctx->custom_dsa_flush, 1.0f);
164 si_blitter_end(sctx);
165 }
166
167 pipe_surface_reference(&zsurf, NULL);
168 pipe_surface_reference(&cbsurf, NULL);
169 }
170
171 if (first_layer == 0 && last_layer >= max_layer &&
172 first_sample == 0 && last_sample >= u_max_sample(&src->buffer.b.b))
173 fully_copied_levels |= 1u << level;
174 }
175
176 sctx->decompression_enabled = false;
177 sctx->dbcb_depth_copy_enabled = false;
178 sctx->dbcb_stencil_copy_enabled = false;
179 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
180
181 return fully_copied_levels;
182 }
183
184 /* Helper function for si_blit_decompress_zs_in_place.
185 */
186 static void
187 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
188 struct si_texture *texture,
189 unsigned planes, unsigned level_mask,
190 unsigned first_layer, unsigned last_layer)
191 {
192 struct pipe_surface *zsurf, surf_tmpl = {{0}};
193 unsigned layer, max_layer, checked_last_layer;
194 unsigned fully_decompressed_mask = 0;
195
196 if (!level_mask)
197 return;
198
199 if (planes & PIPE_MASK_S)
200 sctx->db_flush_stencil_inplace = true;
201 if (planes & PIPE_MASK_Z)
202 sctx->db_flush_depth_inplace = true;
203 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
204
205 surf_tmpl.format = texture->buffer.b.b.format;
206
207 sctx->decompression_enabled = true;
208
209 while (level_mask) {
210 unsigned level = u_bit_scan(&level_mask);
211
212 surf_tmpl.u.tex.level = level;
213
214 /* The smaller the mipmap level, the less layers there are
215 * as far as 3D textures are concerned. */
216 max_layer = util_max_layer(&texture->buffer.b.b, level);
217 checked_last_layer = MIN2(last_layer, max_layer);
218
219 for (layer = first_layer; layer <= checked_last_layer; layer++) {
220 surf_tmpl.u.tex.first_layer = layer;
221 surf_tmpl.u.tex.last_layer = layer;
222
223 zsurf = sctx->b.create_surface(&sctx->b, &texture->buffer.b.b, &surf_tmpl);
224
225 si_blitter_begin(sctx, SI_DECOMPRESS);
226 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
227 sctx->custom_dsa_flush,
228 1.0f);
229 si_blitter_end(sctx);
230
231 pipe_surface_reference(&zsurf, NULL);
232 }
233
234 /* The texture will always be dirty if some layers aren't flushed.
235 * I don't think this case occurs often though. */
236 if (first_layer == 0 && last_layer >= max_layer) {
237 fully_decompressed_mask |= 1u << level;
238 }
239 }
240
241 if (planes & PIPE_MASK_Z)
242 texture->dirty_level_mask &= ~fully_decompressed_mask;
243 if (planes & PIPE_MASK_S)
244 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
245
246 sctx->decompression_enabled = false;
247 sctx->db_flush_depth_inplace = false;
248 sctx->db_flush_stencil_inplace = false;
249 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
250 }
251
252 /* Helper function of si_flush_depth_texture: decompress the given levels
253 * of Z and/or S planes in place.
254 */
255 static void
256 si_blit_decompress_zs_in_place(struct si_context *sctx,
257 struct si_texture *texture,
258 unsigned levels_z, unsigned levels_s,
259 unsigned first_layer, unsigned last_layer)
260 {
261 unsigned both = levels_z & levels_s;
262
263 /* First, do combined Z & S decompresses for levels that need it. */
264 if (both) {
265 si_blit_decompress_zs_planes_in_place(
266 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
267 both,
268 first_layer, last_layer);
269 levels_z &= ~both;
270 levels_s &= ~both;
271 }
272
273 /* Now do separate Z and S decompresses. */
274 if (levels_z) {
275 si_blit_decompress_zs_planes_in_place(
276 sctx, texture, PIPE_MASK_Z,
277 levels_z,
278 first_layer, last_layer);
279 }
280
281 if (levels_s) {
282 si_blit_decompress_zs_planes_in_place(
283 sctx, texture, PIPE_MASK_S,
284 levels_s,
285 first_layer, last_layer);
286 }
287 }
288
289 static void
290 si_decompress_depth(struct si_context *sctx,
291 struct si_texture *tex,
292 unsigned required_planes,
293 unsigned first_level, unsigned last_level,
294 unsigned first_layer, unsigned last_layer)
295 {
296 unsigned inplace_planes = 0;
297 unsigned copy_planes = 0;
298 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
299 unsigned levels_z = 0;
300 unsigned levels_s = 0;
301
302 if (required_planes & PIPE_MASK_Z) {
303 levels_z = level_mask & tex->dirty_level_mask;
304
305 if (levels_z) {
306 if (si_can_sample_zs(tex, false))
307 inplace_planes |= PIPE_MASK_Z;
308 else
309 copy_planes |= PIPE_MASK_Z;
310 }
311 }
312 if (required_planes & PIPE_MASK_S) {
313 levels_s = level_mask & tex->stencil_dirty_level_mask;
314
315 if (levels_s) {
316 if (si_can_sample_zs(tex, true))
317 inplace_planes |= PIPE_MASK_S;
318 else
319 copy_planes |= PIPE_MASK_S;
320 }
321 }
322
323 if (unlikely(sctx->log))
324 u_log_printf(sctx->log,
325 "\n------------------------------------------------\n"
326 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
327 first_level, last_level, levels_z, levels_s);
328
329 /* We may have to allocate the flushed texture here when called from
330 * si_decompress_subresource.
331 */
332 if (copy_planes &&
333 (tex->flushed_depth_texture ||
334 si_init_flushed_depth_texture(&sctx->b, &tex->buffer.b.b))) {
335 struct si_texture *dst = tex->flushed_depth_texture;
336 unsigned fully_copied_levels;
337 unsigned levels = 0;
338
339 assert(tex->flushed_depth_texture);
340
341 if (util_format_is_depth_and_stencil(dst->buffer.b.b.format))
342 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
343
344 if (copy_planes & PIPE_MASK_Z) {
345 levels |= levels_z;
346 levels_z = 0;
347 }
348 if (copy_planes & PIPE_MASK_S) {
349 levels |= levels_s;
350 levels_s = 0;
351 }
352
353 fully_copied_levels = si_blit_dbcb_copy(
354 sctx, tex, dst, copy_planes, levels,
355 first_layer, last_layer,
356 0, u_max_sample(&tex->buffer.b.b));
357
358 if (copy_planes & PIPE_MASK_Z)
359 tex->dirty_level_mask &= ~fully_copied_levels;
360 if (copy_planes & PIPE_MASK_S)
361 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
362 }
363
364 if (inplace_planes) {
365 bool has_htile = si_htile_enabled(tex, first_level, inplace_planes);
366 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level,
367 inplace_planes);
368
369 /* Don't decompress if there is no HTILE or when HTILE is
370 * TC-compatible. */
371 if (has_htile && !tc_compat_htile) {
372 si_blit_decompress_zs_in_place(
373 sctx, tex,
374 levels_z, levels_s,
375 first_layer, last_layer);
376 } else {
377 /* This is only a cache flush.
378 *
379 * Only clear the mask that we are flushing, because
380 * si_make_DB_shader_coherent() treats different levels
381 * and depth and stencil differently.
382 */
383 if (inplace_planes & PIPE_MASK_Z)
384 tex->dirty_level_mask &= ~levels_z;
385 if (inplace_planes & PIPE_MASK_S)
386 tex->stencil_dirty_level_mask &= ~levels_s;
387 }
388
389 /* Only in-place decompression needs to flush DB caches, or
390 * when we don't decompress but TC-compatible planes are dirty.
391 */
392 si_make_DB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
393 inplace_planes & PIPE_MASK_S,
394 tc_compat_htile);
395 }
396 /* set_framebuffer_state takes care of coherency for single-sample.
397 * The DB->CB copy uses CB for the final writes.
398 */
399 if (copy_planes && tex->buffer.b.b.nr_samples > 1)
400 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
401 false, true /* no DCC */);
402 }
403
404 static void
405 si_decompress_sampler_depth_textures(struct si_context *sctx,
406 struct si_samplers *textures)
407 {
408 unsigned i;
409 unsigned mask = textures->needs_depth_decompress_mask;
410
411 while (mask) {
412 struct pipe_sampler_view *view;
413 struct si_sampler_view *sview;
414 struct si_texture *tex;
415
416 i = u_bit_scan(&mask);
417
418 view = textures->views[i];
419 assert(view);
420 sview = (struct si_sampler_view*)view;
421
422 tex = (struct si_texture *)view->texture;
423 assert(tex->db_compatible);
424
425 si_decompress_depth(sctx, tex,
426 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
427 view->u.tex.first_level, view->u.tex.last_level,
428 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
429 }
430 }
431
432 static void si_blit_decompress_color(struct si_context *sctx,
433 struct si_texture *tex,
434 unsigned first_level, unsigned last_level,
435 unsigned first_layer, unsigned last_layer,
436 bool need_dcc_decompress,
437 bool need_fmask_expand)
438 {
439 void* custom_blend;
440 unsigned layer, checked_last_layer, max_layer;
441 unsigned level_mask =
442 u_bit_consecutive(first_level, last_level - first_level + 1);
443
444 if (!need_dcc_decompress)
445 level_mask &= tex->dirty_level_mask;
446 if (!level_mask)
447 return;
448
449 if (unlikely(sctx->log))
450 u_log_printf(sctx->log,
451 "\n------------------------------------------------\n"
452 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
453 first_level, last_level, level_mask);
454
455 if (need_dcc_decompress) {
456 custom_blend = sctx->custom_blend_dcc_decompress;
457
458 assert(tex->surface.dcc_offset);
459
460 /* disable levels without DCC */
461 for (int i = first_level; i <= last_level; i++) {
462 if (!vi_dcc_enabled(tex, i))
463 level_mask &= ~(1 << i);
464 }
465 } else if (tex->surface.fmask_size) {
466 custom_blend = sctx->custom_blend_fmask_decompress;
467 } else {
468 custom_blend = sctx->custom_blend_eliminate_fastclear;
469 }
470
471 sctx->decompression_enabled = true;
472
473 while (level_mask) {
474 unsigned level = u_bit_scan(&level_mask);
475
476 /* The smaller the mipmap level, the less layers there are
477 * as far as 3D textures are concerned. */
478 max_layer = util_max_layer(&tex->buffer.b.b, level);
479 checked_last_layer = MIN2(last_layer, max_layer);
480
481 for (layer = first_layer; layer <= checked_last_layer; layer++) {
482 struct pipe_surface *cbsurf, surf_tmpl;
483
484 surf_tmpl.format = tex->buffer.b.b.format;
485 surf_tmpl.u.tex.level = level;
486 surf_tmpl.u.tex.first_layer = layer;
487 surf_tmpl.u.tex.last_layer = layer;
488 cbsurf = sctx->b.create_surface(&sctx->b, &tex->buffer.b.b, &surf_tmpl);
489
490 /* Required before and after FMASK and DCC_DECOMPRESS. */
491 if (custom_blend == sctx->custom_blend_fmask_decompress ||
492 custom_blend == sctx->custom_blend_dcc_decompress)
493 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
494
495 si_blitter_begin(sctx, SI_DECOMPRESS);
496 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
497 si_blitter_end(sctx);
498
499 if (custom_blend == sctx->custom_blend_fmask_decompress ||
500 custom_blend == sctx->custom_blend_dcc_decompress)
501 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
502
503 pipe_surface_reference(&cbsurf, NULL);
504 }
505
506 /* The texture will always be dirty if some layers aren't flushed.
507 * I don't think this case occurs often though. */
508 if (first_layer == 0 && last_layer >= max_layer) {
509 tex->dirty_level_mask &= ~(1 << level);
510 }
511 }
512
513 sctx->decompression_enabled = false;
514 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
515 vi_dcc_enabled(tex, first_level),
516 tex->surface.u.gfx9.dcc.pipe_aligned);
517
518 if (need_fmask_expand && tex->surface.fmask_offset && tex->fmask_is_not_identity) {
519 si_compute_expand_fmask(&sctx->b, &tex->buffer.b.b);
520 tex->fmask_is_not_identity = false;
521 }
522 }
523
524 static void
525 si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex,
526 unsigned first_level, unsigned last_level,
527 bool need_fmask_expand)
528 {
529 /* CMASK or DCC can be discarded and we can still end up here. */
530 if (!tex->cmask_buffer && !tex->surface.fmask_size && !tex->surface.dcc_offset)
531 return;
532
533 si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
534 util_max_layer(&tex->buffer.b.b, first_level),
535 false, need_fmask_expand);
536 }
537
538 static void
539 si_decompress_sampler_color_textures(struct si_context *sctx,
540 struct si_samplers *textures)
541 {
542 unsigned i;
543 unsigned mask = textures->needs_color_decompress_mask;
544
545 while (mask) {
546 struct pipe_sampler_view *view;
547 struct si_texture *tex;
548
549 i = u_bit_scan(&mask);
550
551 view = textures->views[i];
552 assert(view);
553
554 tex = (struct si_texture *)view->texture;
555
556 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
557 view->u.tex.last_level, false);
558 }
559 }
560
561 static void
562 si_decompress_image_color_textures(struct si_context *sctx,
563 struct si_images *images)
564 {
565 unsigned i;
566 unsigned mask = images->needs_color_decompress_mask;
567
568 while (mask) {
569 const struct pipe_image_view *view;
570 struct si_texture *tex;
571
572 i = u_bit_scan(&mask);
573
574 view = &images->views[i];
575 assert(view->resource->target != PIPE_BUFFER);
576
577 tex = (struct si_texture *)view->resource;
578
579 si_decompress_color_texture(sctx, tex, view->u.tex.level,
580 view->u.tex.level,
581 view->access & PIPE_IMAGE_ACCESS_WRITE);
582 }
583 }
584
585 static void si_check_render_feedback_texture(struct si_context *sctx,
586 struct si_texture *tex,
587 unsigned first_level,
588 unsigned last_level,
589 unsigned first_layer,
590 unsigned last_layer)
591 {
592 bool render_feedback = false;
593
594 if (!tex->surface.dcc_offset)
595 return;
596
597 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
598 struct si_surface * surf;
599
600 if (!sctx->framebuffer.state.cbufs[j])
601 continue;
602
603 surf = (struct si_surface*)sctx->framebuffer.state.cbufs[j];
604
605 if (tex == (struct si_texture *)surf->base.texture &&
606 surf->base.u.tex.level >= first_level &&
607 surf->base.u.tex.level <= last_level &&
608 surf->base.u.tex.first_layer <= last_layer &&
609 surf->base.u.tex.last_layer >= first_layer) {
610 render_feedback = true;
611 break;
612 }
613 }
614
615 if (render_feedback)
616 si_texture_disable_dcc(sctx, tex);
617 }
618
619 static void si_check_render_feedback_textures(struct si_context *sctx,
620 struct si_samplers *textures)
621 {
622 uint32_t mask = textures->enabled_mask;
623
624 while (mask) {
625 const struct pipe_sampler_view *view;
626 struct si_texture *tex;
627
628 unsigned i = u_bit_scan(&mask);
629
630 view = textures->views[i];
631 if(view->texture->target == PIPE_BUFFER)
632 continue;
633
634 tex = (struct si_texture *)view->texture;
635
636 si_check_render_feedback_texture(sctx, tex,
637 view->u.tex.first_level,
638 view->u.tex.last_level,
639 view->u.tex.first_layer,
640 view->u.tex.last_layer);
641 }
642 }
643
644 static void si_check_render_feedback_images(struct si_context *sctx,
645 struct si_images *images)
646 {
647 uint32_t mask = images->enabled_mask;
648
649 while (mask) {
650 const struct pipe_image_view *view;
651 struct si_texture *tex;
652
653 unsigned i = u_bit_scan(&mask);
654
655 view = &images->views[i];
656 if (view->resource->target == PIPE_BUFFER)
657 continue;
658
659 tex = (struct si_texture *)view->resource;
660
661 si_check_render_feedback_texture(sctx, tex,
662 view->u.tex.level,
663 view->u.tex.level,
664 view->u.tex.first_layer,
665 view->u.tex.last_layer);
666 }
667 }
668
669 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
670 {
671 util_dynarray_foreach(&sctx->resident_tex_handles,
672 struct si_texture_handle *, tex_handle) {
673 struct pipe_sampler_view *view;
674 struct si_texture *tex;
675
676 view = (*tex_handle)->view;
677 if (view->texture->target == PIPE_BUFFER)
678 continue;
679
680 tex = (struct si_texture *)view->texture;
681
682 si_check_render_feedback_texture(sctx, tex,
683 view->u.tex.first_level,
684 view->u.tex.last_level,
685 view->u.tex.first_layer,
686 view->u.tex.last_layer);
687 }
688 }
689
690 static void si_check_render_feedback_resident_images(struct si_context *sctx)
691 {
692 util_dynarray_foreach(&sctx->resident_img_handles,
693 struct si_image_handle *, img_handle) {
694 struct pipe_image_view *view;
695 struct si_texture *tex;
696
697 view = &(*img_handle)->view;
698 if (view->resource->target == PIPE_BUFFER)
699 continue;
700
701 tex = (struct si_texture *)view->resource;
702
703 si_check_render_feedback_texture(sctx, tex,
704 view->u.tex.level,
705 view->u.tex.level,
706 view->u.tex.first_layer,
707 view->u.tex.last_layer);
708 }
709 }
710
711 static void si_check_render_feedback(struct si_context *sctx)
712 {
713 if (!sctx->need_check_render_feedback)
714 return;
715
716 /* There is no render feedback if color writes are disabled.
717 * (e.g. a pixel shader with image stores)
718 */
719 if (!si_get_total_colormask(sctx))
720 return;
721
722 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
723 si_check_render_feedback_images(sctx, &sctx->images[i]);
724 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
725 }
726
727 si_check_render_feedback_resident_images(sctx);
728 si_check_render_feedback_resident_textures(sctx);
729
730 sctx->need_check_render_feedback = false;
731 }
732
733 static void si_decompress_resident_textures(struct si_context *sctx)
734 {
735 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
736 struct si_texture_handle *, tex_handle) {
737 struct pipe_sampler_view *view = (*tex_handle)->view;
738 struct si_texture *tex = (struct si_texture *)view->texture;
739
740 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
741 view->u.tex.last_level, false);
742 }
743
744 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
745 struct si_texture_handle *, tex_handle) {
746 struct pipe_sampler_view *view = (*tex_handle)->view;
747 struct si_sampler_view *sview = (struct si_sampler_view *)view;
748 struct si_texture *tex = (struct si_texture *)view->texture;
749
750 si_decompress_depth(sctx, tex,
751 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
752 view->u.tex.first_level, view->u.tex.last_level,
753 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
754 }
755 }
756
757 static void si_decompress_resident_images(struct si_context *sctx)
758 {
759 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
760 struct si_image_handle *, img_handle) {
761 struct pipe_image_view *view = &(*img_handle)->view;
762 struct si_texture *tex = (struct si_texture *)view->resource;
763
764 si_decompress_color_texture(sctx, tex, view->u.tex.level,
765 view->u.tex.level,
766 view->access & PIPE_IMAGE_ACCESS_WRITE);
767 }
768 }
769
770 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
771 {
772 unsigned compressed_colortex_counter, mask;
773
774 if (sctx->blitter->running)
775 return;
776
777 /* Update the compressed_colortex_mask if necessary. */
778 compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter);
779 if (compressed_colortex_counter != sctx->last_compressed_colortex_counter) {
780 sctx->last_compressed_colortex_counter = compressed_colortex_counter;
781 si_update_needs_color_decompress_masks(sctx);
782 }
783
784 /* Decompress color & depth textures if needed. */
785 mask = sctx->shader_needs_decompress_mask & shader_mask;
786 while (mask) {
787 unsigned i = u_bit_scan(&mask);
788
789 if (sctx->samplers[i].needs_depth_decompress_mask) {
790 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
791 }
792 if (sctx->samplers[i].needs_color_decompress_mask) {
793 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
794 }
795 if (sctx->images[i].needs_color_decompress_mask) {
796 si_decompress_image_color_textures(sctx, &sctx->images[i]);
797 }
798 }
799
800 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
801 if (sctx->uses_bindless_samplers)
802 si_decompress_resident_textures(sctx);
803 if (sctx->uses_bindless_images)
804 si_decompress_resident_images(sctx);
805
806 if (sctx->ps_uses_fbfetch) {
807 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
808 si_decompress_color_texture(sctx,
809 (struct si_texture*)cb0->texture,
810 cb0->u.tex.first_layer,
811 cb0->u.tex.last_layer, false);
812 }
813
814 si_check_render_feedback(sctx);
815 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
816 if (sctx->cs_shader_state.program->sel.info.uses_bindless_samplers)
817 si_decompress_resident_textures(sctx);
818 if (sctx->cs_shader_state.program->sel.info.uses_bindless_images)
819 si_decompress_resident_images(sctx);
820 }
821 }
822
823 /* Helper for decompressing a portion of a color or depth resource before
824 * blitting if any decompression is needed.
825 * The driver doesn't decompress resources automatically while u_blitter is
826 * rendering. */
827 static void si_decompress_subresource(struct pipe_context *ctx,
828 struct pipe_resource *tex,
829 unsigned planes, unsigned level,
830 unsigned first_layer, unsigned last_layer)
831 {
832 struct si_context *sctx = (struct si_context *)ctx;
833 struct si_texture *stex = (struct si_texture*)tex;
834
835 if (stex->db_compatible) {
836 planes &= PIPE_MASK_Z | PIPE_MASK_S;
837
838 if (!stex->surface.has_stencil)
839 planes &= ~PIPE_MASK_S;
840
841 /* If we've rendered into the framebuffer and it's a blitting
842 * source, make sure the decompression pass is invoked
843 * by dirtying the framebuffer.
844 */
845 if (sctx->framebuffer.state.zsbuf &&
846 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
847 sctx->framebuffer.state.zsbuf->texture == tex)
848 si_update_fb_dirtiness_after_rendering(sctx);
849
850 si_decompress_depth(sctx, stex, planes,
851 level, level,
852 first_layer, last_layer);
853 } else if (stex->surface.fmask_size || stex->cmask_buffer || stex->surface.dcc_offset) {
854 /* If we've rendered into the framebuffer and it's a blitting
855 * source, make sure the decompression pass is invoked
856 * by dirtying the framebuffer.
857 */
858 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
859 if (sctx->framebuffer.state.cbufs[i] &&
860 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
861 sctx->framebuffer.state.cbufs[i]->texture == tex) {
862 si_update_fb_dirtiness_after_rendering(sctx);
863 break;
864 }
865 }
866
867 si_blit_decompress_color(sctx, stex, level, level,
868 first_layer, last_layer, false, false);
869 }
870 }
871
872 struct texture_orig_info {
873 unsigned format;
874 unsigned width0;
875 unsigned height0;
876 unsigned npix_x;
877 unsigned npix_y;
878 unsigned npix0_x;
879 unsigned npix0_y;
880 };
881
882 void si_resource_copy_region(struct pipe_context *ctx,
883 struct pipe_resource *dst,
884 unsigned dst_level,
885 unsigned dstx, unsigned dsty, unsigned dstz,
886 struct pipe_resource *src,
887 unsigned src_level,
888 const struct pipe_box *src_box)
889 {
890 struct si_context *sctx = (struct si_context *)ctx;
891 struct si_texture *ssrc = (struct si_texture*)src;
892 struct si_texture *sdst = (struct si_texture*)dst;
893 struct pipe_surface *dst_view, dst_templ;
894 struct pipe_sampler_view src_templ, *src_view;
895 unsigned dst_width, dst_height, src_width0, src_height0;
896 unsigned dst_width0, dst_height0, src_force_level = 0;
897 struct pipe_box sbox, dstbox;
898
899 /* Handle buffers first. */
900 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
901 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
902 return;
903 }
904
905 if (!util_format_is_compressed(src->format) &&
906 !util_format_is_compressed(dst->format) &&
907 !util_format_is_depth_or_stencil(src->format) &&
908 src->nr_samples <= 1 &&
909 !sdst->surface.dcc_offset &&
910 !(dst->target != src->target &&
911 (src->target == PIPE_TEXTURE_1D_ARRAY || dst->target == PIPE_TEXTURE_1D_ARRAY))) {
912 si_compute_copy_image(sctx, dst, dst_level, src, src_level, dstx, dsty, dstz, src_box);
913 return;
914 }
915
916 assert(u_max_sample(dst) == u_max_sample(src));
917
918 /* The driver doesn't decompress resources automatically while
919 * u_blitter is rendering. */
920 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
921 src_box->z, src_box->z + src_box->depth - 1);
922
923 dst_width = u_minify(dst->width0, dst_level);
924 dst_height = u_minify(dst->height0, dst_level);
925 dst_width0 = dst->width0;
926 dst_height0 = dst->height0;
927 src_width0 = src->width0;
928 src_height0 = src->height0;
929
930 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
931 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
932
933 if (util_format_is_compressed(src->format) ||
934 util_format_is_compressed(dst->format)) {
935 unsigned blocksize = ssrc->surface.bpe;
936
937 if (blocksize == 8)
938 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
939 else
940 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
941 dst_templ.format = src_templ.format;
942
943 dst_width = util_format_get_nblocksx(dst->format, dst_width);
944 dst_height = util_format_get_nblocksy(dst->format, dst_height);
945 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
946 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
947 src_width0 = util_format_get_nblocksx(src->format, src_width0);
948 src_height0 = util_format_get_nblocksy(src->format, src_height0);
949
950 dstx = util_format_get_nblocksx(dst->format, dstx);
951 dsty = util_format_get_nblocksy(dst->format, dsty);
952
953 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
954 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
955 sbox.z = src_box->z;
956 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
957 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
958 sbox.depth = src_box->depth;
959 src_box = &sbox;
960
961 src_force_level = src_level;
962 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
963 if (util_format_is_subsampled_422(src->format)) {
964 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
965 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
966
967 dst_width = util_format_get_nblocksx(dst->format, dst_width);
968 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
969 src_width0 = util_format_get_nblocksx(src->format, src_width0);
970
971 dstx = util_format_get_nblocksx(dst->format, dstx);
972
973 sbox = *src_box;
974 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
975 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
976 src_box = &sbox;
977 } else {
978 unsigned blocksize = ssrc->surface.bpe;
979
980 switch (blocksize) {
981 case 1:
982 dst_templ.format = PIPE_FORMAT_R8_UNORM;
983 src_templ.format = PIPE_FORMAT_R8_UNORM;
984 break;
985 case 2:
986 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
987 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
988 break;
989 case 4:
990 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
991 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
992 break;
993 case 8:
994 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
995 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
996 break;
997 case 16:
998 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
999 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1000 break;
1001 default:
1002 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1003 util_format_short_name(src->format), blocksize);
1004 assert(0);
1005 }
1006 }
1007 }
1008
1009 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1010 * equivalent instead, which doesn't force DCC decompression.
1011 * Note that some chips avoid this issue by using SDMA.
1012 */
1013 if (util_format_is_snorm8(dst_templ.format)) {
1014 dst_templ.format = src_templ.format =
1015 util_format_snorm8_to_sint8(dst_templ.format);
1016 }
1017
1018 vi_disable_dcc_if_incompatible_format(sctx, dst, dst_level,
1019 dst_templ.format);
1020 vi_disable_dcc_if_incompatible_format(sctx, src, src_level,
1021 src_templ.format);
1022
1023 /* Initialize the surface. */
1024 dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
1025 dst_width0, dst_height0,
1026 dst_width, dst_height);
1027
1028 /* Initialize the sampler view. */
1029 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1030 src_width0, src_height0,
1031 src_force_level);
1032
1033 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1034 abs(src_box->depth), &dstbox);
1035
1036 /* Copy. */
1037 si_blitter_begin(sctx, SI_COPY);
1038 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1039 src_view, src_box, src_width0, src_height0,
1040 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1041 false);
1042 si_blitter_end(sctx);
1043
1044 pipe_surface_reference(&dst_view, NULL);
1045 pipe_sampler_view_reference(&src_view, NULL);
1046 }
1047
1048 static void si_do_CB_resolve(struct si_context *sctx,
1049 const struct pipe_blit_info *info,
1050 struct pipe_resource *dst,
1051 unsigned dst_level, unsigned dst_z,
1052 enum pipe_format format)
1053 {
1054 /* Required before and after CB_RESOLVE. */
1055 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1056
1057 si_blitter_begin(sctx, SI_COLOR_RESOLVE |
1058 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1059 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1060 info->src.resource, info->src.box.z,
1061 ~0, sctx->custom_blend_resolve,
1062 format);
1063 si_blitter_end(sctx);
1064
1065 /* Flush caches for possible texturing. */
1066 si_make_CB_shader_coherent(sctx, 1, false, true /* no DCC */);
1067 }
1068
1069 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1070 const struct pipe_blit_info *info)
1071 {
1072 struct si_context *sctx = (struct si_context*)ctx;
1073 struct si_texture *src = (struct si_texture*)info->src.resource;
1074 struct si_texture *dst = (struct si_texture*)info->dst.resource;
1075 ASSERTED struct si_texture *stmp;
1076 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1077 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1078 enum pipe_format format = info->src.format;
1079 struct pipe_resource *tmp, templ;
1080 struct pipe_blit_info blit;
1081
1082 /* Check basic requirements for hw resolve. */
1083 if (!(info->src.resource->nr_samples > 1 &&
1084 info->dst.resource->nr_samples <= 1 &&
1085 !util_format_is_pure_integer(format) &&
1086 !util_format_is_depth_or_stencil(format) &&
1087 util_max_layer(info->src.resource, 0) == 0))
1088 return false;
1089
1090 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1091 * the format is R16G16. Use R16A16, which does work.
1092 */
1093 if (format == PIPE_FORMAT_R16G16_UNORM)
1094 format = PIPE_FORMAT_R16A16_UNORM;
1095 if (format == PIPE_FORMAT_R16G16_SNORM)
1096 format = PIPE_FORMAT_R16A16_SNORM;
1097
1098 /* Check the remaining requirements for hw resolve. */
1099 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1100 !info->scissor_enable &&
1101 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1102 util_is_format_compatible(util_format_description(info->src.format),
1103 util_format_description(info->dst.format)) &&
1104 dst_width == info->src.resource->width0 &&
1105 dst_height == info->src.resource->height0 &&
1106 info->dst.box.x == 0 &&
1107 info->dst.box.y == 0 &&
1108 info->dst.box.width == dst_width &&
1109 info->dst.box.height == dst_height &&
1110 info->dst.box.depth == 1 &&
1111 info->src.box.x == 0 &&
1112 info->src.box.y == 0 &&
1113 info->src.box.width == dst_width &&
1114 info->src.box.height == dst_height &&
1115 info->src.box.depth == 1 &&
1116 !dst->surface.is_linear &&
1117 (!dst->cmask_buffer || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1118 /* Check the last constraint. */
1119 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1120 /* The next fast clear will switch to this mode to
1121 * get direct hw resolve next time if the mode is
1122 * different now.
1123 *
1124 * TODO-GFX10: This does not work in GFX10 because MSAA
1125 * is restricted to 64KB_R_X and 64KB_Z_X swizzle modes.
1126 * In some cases we could change the swizzle of the
1127 * destination texture instead, but the more general
1128 * solution is to implement compute shader resolve.
1129 */
1130 src->last_msaa_resolve_target_micro_mode =
1131 dst->surface.micro_tile_mode;
1132 goto resolve_to_temp;
1133 }
1134
1135 /* Resolving into a surface with DCC is unsupported. Since
1136 * it's being overwritten anyway, clear it to uncompressed.
1137 * This is still the fastest codepath even with this clear.
1138 */
1139 if (vi_dcc_enabled(dst, info->dst.level)) {
1140 if (!vi_dcc_clear_level(sctx, dst, info->dst.level,
1141 DCC_UNCOMPRESSED))
1142 goto resolve_to_temp;
1143
1144 dst->dirty_level_mask &= ~(1 << info->dst.level);
1145 }
1146
1147 /* Resolve directly from src to dst. */
1148 si_do_CB_resolve(sctx, info, info->dst.resource,
1149 info->dst.level, info->dst.box.z, format);
1150 return true;
1151 }
1152
1153 resolve_to_temp:
1154 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1155 * a temporary texture and blit.
1156 */
1157 memset(&templ, 0, sizeof(templ));
1158 templ.target = PIPE_TEXTURE_2D;
1159 templ.format = info->src.resource->format;
1160 templ.width0 = info->src.resource->width0;
1161 templ.height0 = info->src.resource->height0;
1162 templ.depth0 = 1;
1163 templ.array_size = 1;
1164 templ.usage = PIPE_USAGE_DEFAULT;
1165 templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING |
1166 SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE |
1167 SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(src->surface.micro_tile_mode) |
1168 SI_RESOURCE_FLAG_DISABLE_DCC;
1169
1170 /* The src and dst microtile modes must be the same. */
1171 if (sctx->chip_class <= GFX8 &&
1172 src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1173 templ.bind = PIPE_BIND_SCANOUT;
1174 else
1175 templ.bind = 0;
1176
1177 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1178 if (!tmp)
1179 return false;
1180 stmp = (struct si_texture*)tmp;
1181
1182 assert(!stmp->surface.is_linear);
1183 assert(src->surface.micro_tile_mode == stmp->surface.micro_tile_mode);
1184
1185 /* resolve */
1186 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1187
1188 /* blit */
1189 blit = *info;
1190 blit.src.resource = tmp;
1191 blit.src.box.z = 0;
1192
1193 si_blitter_begin(sctx, SI_BLIT |
1194 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1195 util_blitter_blit(sctx->blitter, &blit);
1196 si_blitter_end(sctx);
1197
1198 pipe_resource_reference(&tmp, NULL);
1199 return true;
1200 }
1201
1202 static void si_blit(struct pipe_context *ctx,
1203 const struct pipe_blit_info *info)
1204 {
1205 struct si_context *sctx = (struct si_context*)ctx;
1206 struct si_texture *dst = (struct si_texture *)info->dst.resource;
1207
1208 if (do_hardware_msaa_resolve(ctx, info)) {
1209 return;
1210 }
1211
1212 /* Using SDMA for copying to a linear texture in GTT is much faster.
1213 * This improves DRI PRIME performance.
1214 *
1215 * resource_copy_region can't do this yet, because dma_copy calls it
1216 * on failure (recursion).
1217 */
1218 if (dst->surface.is_linear &&
1219 util_can_blit_via_copy_region(info, false)) {
1220 sctx->dma_copy(ctx, info->dst.resource, info->dst.level,
1221 info->dst.box.x, info->dst.box.y,
1222 info->dst.box.z,
1223 info->src.resource, info->src.level,
1224 &info->src.box);
1225 return;
1226 }
1227
1228 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1229
1230 /* The driver doesn't decompress resources automatically while
1231 * u_blitter is rendering. */
1232 vi_disable_dcc_if_incompatible_format(sctx, info->src.resource,
1233 info->src.level,
1234 info->src.format);
1235 vi_disable_dcc_if_incompatible_format(sctx, info->dst.resource,
1236 info->dst.level,
1237 info->dst.format);
1238 si_decompress_subresource(ctx, info->src.resource, PIPE_MASK_RGBAZS,
1239 info->src.level,
1240 info->src.box.z,
1241 info->src.box.z + info->src.box.depth - 1);
1242
1243 if (sctx->screen->debug_flags & DBG(FORCE_SDMA) &&
1244 util_try_blit_via_copy_region(ctx, info))
1245 return;
1246
1247 si_blitter_begin(sctx, SI_BLIT |
1248 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1249 util_blitter_blit(sctx->blitter, info);
1250 si_blitter_end(sctx);
1251 }
1252
1253 static bool si_generate_mipmap(struct pipe_context *ctx,
1254 struct pipe_resource *tex,
1255 enum pipe_format format,
1256 unsigned base_level, unsigned last_level,
1257 unsigned first_layer, unsigned last_layer)
1258 {
1259 struct si_context *sctx = (struct si_context*)ctx;
1260 struct si_texture *stex = (struct si_texture *)tex;
1261
1262 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1263 return false;
1264
1265 /* The driver doesn't decompress resources automatically while
1266 * u_blitter is rendering. */
1267 vi_disable_dcc_if_incompatible_format(sctx, tex, base_level,
1268 format);
1269 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1270 base_level, first_layer, last_layer);
1271
1272 /* Clear dirty_level_mask for the levels that will be overwritten. */
1273 assert(base_level < last_level);
1274 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1275 last_level - base_level);
1276
1277 sctx->generate_mipmap_for_depth = stex->is_depth;
1278
1279 si_blitter_begin(sctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1280 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1281 base_level, last_level,
1282 first_layer, last_layer);
1283 si_blitter_end(sctx);
1284
1285 sctx->generate_mipmap_for_depth = false;
1286 return true;
1287 }
1288
1289 static void si_flush_resource(struct pipe_context *ctx,
1290 struct pipe_resource *res)
1291 {
1292 struct si_context *sctx = (struct si_context*)ctx;
1293 struct si_texture *tex = (struct si_texture*)res;
1294
1295 assert(res->target != PIPE_BUFFER);
1296 assert(!tex->dcc_separate_buffer || tex->dcc_gather_statistics);
1297
1298 /* st/dri calls flush twice per frame (not a bug), this prevents double
1299 * decompression. */
1300 if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
1301 return;
1302
1303 if (!tex->is_depth && (tex->cmask_buffer || tex->surface.dcc_offset)) {
1304 si_blit_decompress_color(sctx, tex, 0, res->last_level,
1305 0, util_max_layer(res, 0),
1306 tex->dcc_separate_buffer != NULL, false);
1307
1308 if (tex->surface.display_dcc_offset && tex->displayable_dcc_dirty) {
1309 si_retile_dcc(sctx, tex);
1310 tex->displayable_dcc_dirty = false;
1311 }
1312 }
1313
1314 /* Always do the analysis even if DCC is disabled at the moment. */
1315 if (tex->dcc_gather_statistics) {
1316 bool separate_dcc_dirty = tex->separate_dcc_dirty;
1317
1318 /* If the color buffer hasn't been unbound and fast clear hasn't
1319 * been used, separate_dcc_dirty is false, but there may have been
1320 * new rendering. Check if the color buffer is bound and assume
1321 * it's dirty.
1322 *
1323 * Note that DRI2 never unbinds window colorbuffers, which means
1324 * the DCC pipeline statistics query would never be re-set and would
1325 * keep adding new results until all free memory is exhausted if we
1326 * didn't do this.
1327 */
1328 if (!separate_dcc_dirty) {
1329 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
1330 if (sctx->framebuffer.state.cbufs[i] &&
1331 sctx->framebuffer.state.cbufs[i]->texture == res) {
1332 separate_dcc_dirty = true;
1333 break;
1334 }
1335 }
1336 }
1337
1338 if (separate_dcc_dirty) {
1339 tex->separate_dcc_dirty = false;
1340 vi_separate_dcc_process_and_reset_stats(ctx, tex);
1341 }
1342 }
1343 }
1344
1345 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
1346 {
1347 /* If graphics is disabled, we can't decompress DCC, but it shouldn't
1348 * be compressed either. The caller should simply discard it.
1349 */
1350 if (!tex->surface.dcc_offset || !sctx->has_graphics)
1351 return;
1352
1353 si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level,
1354 0, util_max_layer(&tex->buffer.b.b, 0),
1355 true, false);
1356 }
1357
1358 void si_init_blit_functions(struct si_context *sctx)
1359 {
1360 sctx->b.resource_copy_region = si_resource_copy_region;
1361
1362 if (sctx->has_graphics) {
1363 sctx->b.blit = si_blit;
1364 sctx->b.flush_resource = si_flush_resource;
1365 sctx->b.generate_mipmap = si_generate_mipmap;
1366 }
1367 }