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radeonsi: log decompress blits
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_log.h"
28 #include "util/u_surface.h"
29
30 enum si_blitter_op /* bitmask */
31 {
32 SI_SAVE_TEXTURES = 1,
33 SI_SAVE_FRAMEBUFFER = 2,
34 SI_SAVE_FRAGMENT_STATE = 4,
35 SI_DISABLE_RENDER_COND = 8,
36
37 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
38
39 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
40
41 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
42 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
43
44 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
45 SI_SAVE_FRAGMENT_STATE,
46
47 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
48 SI_DISABLE_RENDER_COND,
49
50 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
51 };
52
53 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
54 {
55 struct si_context *sctx = (struct si_context *)ctx;
56
57 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
58 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
59 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
60 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
61 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
62 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
63 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
64 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
65 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
66
67 if (op & SI_SAVE_FRAGMENT_STATE) {
68 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
69 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
70 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
71 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
72 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
73 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
74 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
75 }
76
77 if (op & SI_SAVE_FRAMEBUFFER)
78 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
79
80 if (op & SI_SAVE_TEXTURES) {
81 util_blitter_save_fragment_sampler_states(
82 sctx->blitter, 2,
83 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
84
85 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
86 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
87 }
88
89 if (op & SI_DISABLE_RENDER_COND)
90 sctx->b.render_cond_force_off = true;
91 }
92
93 static void si_blitter_end(struct pipe_context *ctx)
94 {
95 struct si_context *sctx = (struct si_context *)ctx;
96
97 sctx->b.render_cond_force_off = false;
98 }
99
100 static unsigned u_max_sample(struct pipe_resource *r)
101 {
102 return r->nr_samples ? r->nr_samples - 1 : 0;
103 }
104
105 static unsigned
106 si_blit_dbcb_copy(struct si_context *sctx,
107 struct r600_texture *src,
108 struct r600_texture *dst,
109 unsigned planes, unsigned level_mask,
110 unsigned first_layer, unsigned last_layer,
111 unsigned first_sample, unsigned last_sample)
112 {
113 struct pipe_surface surf_tmpl = {{0}};
114 unsigned layer, sample, checked_last_layer, max_layer;
115 unsigned fully_copied_levels = 0;
116
117 if (planes & PIPE_MASK_Z)
118 sctx->dbcb_depth_copy_enabled = true;
119 if (planes & PIPE_MASK_S)
120 sctx->dbcb_stencil_copy_enabled = true;
121 si_mark_atom_dirty(sctx, &sctx->db_render_state);
122
123 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
124
125 sctx->decompression_enabled = true;
126
127 while (level_mask) {
128 unsigned level = u_bit_scan(&level_mask);
129
130 /* The smaller the mipmap level, the less layers there are
131 * as far as 3D textures are concerned. */
132 max_layer = util_max_layer(&src->resource.b.b, level);
133 checked_last_layer = MIN2(last_layer, max_layer);
134
135 surf_tmpl.u.tex.level = level;
136
137 for (layer = first_layer; layer <= checked_last_layer; layer++) {
138 struct pipe_surface *zsurf, *cbsurf;
139
140 surf_tmpl.format = src->resource.b.b.format;
141 surf_tmpl.u.tex.first_layer = layer;
142 surf_tmpl.u.tex.last_layer = layer;
143
144 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
145
146 surf_tmpl.format = dst->resource.b.b.format;
147 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
148
149 for (sample = first_sample; sample <= last_sample; sample++) {
150 if (sample != sctx->dbcb_copy_sample) {
151 sctx->dbcb_copy_sample = sample;
152 si_mark_atom_dirty(sctx, &sctx->db_render_state);
153 }
154
155 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
156 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
157 sctx->custom_dsa_flush, 1.0f);
158 si_blitter_end(&sctx->b.b);
159 }
160
161 pipe_surface_reference(&zsurf, NULL);
162 pipe_surface_reference(&cbsurf, NULL);
163 }
164
165 if (first_layer == 0 && last_layer >= max_layer &&
166 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
167 fully_copied_levels |= 1u << level;
168 }
169
170 sctx->decompression_enabled = false;
171 sctx->dbcb_depth_copy_enabled = false;
172 sctx->dbcb_stencil_copy_enabled = false;
173 si_mark_atom_dirty(sctx, &sctx->db_render_state);
174
175 return fully_copied_levels;
176 }
177
178 static void si_blit_decompress_depth(struct pipe_context *ctx,
179 struct r600_texture *texture,
180 struct r600_texture *staging,
181 unsigned first_level, unsigned last_level,
182 unsigned first_layer, unsigned last_layer,
183 unsigned first_sample, unsigned last_sample)
184 {
185 const struct util_format_description *desc;
186 unsigned planes = 0;
187
188 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
189
190 desc = util_format_description(staging->resource.b.b.format);
191
192 if (util_format_has_depth(desc))
193 planes |= PIPE_MASK_Z;
194 if (util_format_has_stencil(desc))
195 planes |= PIPE_MASK_S;
196
197 si_blit_dbcb_copy(
198 (struct si_context *)ctx, texture, staging, planes,
199 u_bit_consecutive(first_level, last_level - first_level + 1),
200 first_layer, last_layer, first_sample, last_sample);
201 }
202
203 /* Helper function for si_blit_decompress_zs_in_place.
204 */
205 static void
206 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
207 struct r600_texture *texture,
208 unsigned planes, unsigned level_mask,
209 unsigned first_layer, unsigned last_layer)
210 {
211 struct pipe_surface *zsurf, surf_tmpl = {{0}};
212 unsigned layer, max_layer, checked_last_layer;
213 unsigned fully_decompressed_mask = 0;
214
215 if (!level_mask)
216 return;
217
218 if (planes & PIPE_MASK_S)
219 sctx->db_flush_stencil_inplace = true;
220 if (planes & PIPE_MASK_Z)
221 sctx->db_flush_depth_inplace = true;
222 si_mark_atom_dirty(sctx, &sctx->db_render_state);
223
224 surf_tmpl.format = texture->resource.b.b.format;
225
226 sctx->decompression_enabled = true;
227
228 while (level_mask) {
229 unsigned level = u_bit_scan(&level_mask);
230
231 surf_tmpl.u.tex.level = level;
232
233 /* The smaller the mipmap level, the less layers there are
234 * as far as 3D textures are concerned. */
235 max_layer = util_max_layer(&texture->resource.b.b, level);
236 checked_last_layer = MIN2(last_layer, max_layer);
237
238 for (layer = first_layer; layer <= checked_last_layer; layer++) {
239 surf_tmpl.u.tex.first_layer = layer;
240 surf_tmpl.u.tex.last_layer = layer;
241
242 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
243
244 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
245 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
246 sctx->custom_dsa_flush,
247 1.0f);
248 si_blitter_end(&sctx->b.b);
249
250 pipe_surface_reference(&zsurf, NULL);
251 }
252
253 /* The texture will always be dirty if some layers aren't flushed.
254 * I don't think this case occurs often though. */
255 if (first_layer == 0 && last_layer >= max_layer) {
256 fully_decompressed_mask |= 1u << level;
257 }
258 }
259
260 if (planes & PIPE_MASK_Z)
261 texture->dirty_level_mask &= ~fully_decompressed_mask;
262 if (planes & PIPE_MASK_S)
263 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
264
265 sctx->decompression_enabled = false;
266 sctx->db_flush_depth_inplace = false;
267 sctx->db_flush_stencil_inplace = false;
268 si_mark_atom_dirty(sctx, &sctx->db_render_state);
269 }
270
271 /* Helper function of si_flush_depth_texture: decompress the given levels
272 * of Z and/or S planes in place.
273 */
274 static void
275 si_blit_decompress_zs_in_place(struct si_context *sctx,
276 struct r600_texture *texture,
277 unsigned levels_z, unsigned levels_s,
278 unsigned first_layer, unsigned last_layer)
279 {
280 unsigned both = levels_z & levels_s;
281
282 /* First, do combined Z & S decompresses for levels that need it. */
283 if (both) {
284 si_blit_decompress_zs_planes_in_place(
285 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
286 both,
287 first_layer, last_layer);
288 levels_z &= ~both;
289 levels_s &= ~both;
290 }
291
292 /* Now do separate Z and S decompresses. */
293 if (levels_z) {
294 si_blit_decompress_zs_planes_in_place(
295 sctx, texture, PIPE_MASK_Z,
296 levels_z,
297 first_layer, last_layer);
298 }
299
300 if (levels_s) {
301 si_blit_decompress_zs_planes_in_place(
302 sctx, texture, PIPE_MASK_S,
303 levels_s,
304 first_layer, last_layer);
305 }
306 }
307
308 static void
309 si_decompress_depth(struct si_context *sctx,
310 struct r600_texture *tex,
311 unsigned required_planes,
312 unsigned first_level, unsigned last_level,
313 unsigned first_layer, unsigned last_layer)
314 {
315 unsigned inplace_planes = 0;
316 unsigned copy_planes = 0;
317 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
318 unsigned levels_z = 0;
319 unsigned levels_s = 0;
320
321 if (required_planes & PIPE_MASK_Z) {
322 levels_z = level_mask & tex->dirty_level_mask;
323
324 if (levels_z) {
325 if (r600_can_sample_zs(tex, false))
326 inplace_planes |= PIPE_MASK_Z;
327 else
328 copy_planes |= PIPE_MASK_Z;
329 }
330 }
331 if (required_planes & PIPE_MASK_S) {
332 levels_s = level_mask & tex->stencil_dirty_level_mask;
333
334 if (levels_s) {
335 if (r600_can_sample_zs(tex, true))
336 inplace_planes |= PIPE_MASK_S;
337 else
338 copy_planes |= PIPE_MASK_S;
339 }
340 }
341
342 if (unlikely(sctx->b.log))
343 u_log_printf(sctx->b.log,
344 "\n------------------------------------------------\n"
345 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
346 first_level, last_level, levels_z, levels_s);
347
348 /* We may have to allocate the flushed texture here when called from
349 * si_decompress_subresource.
350 */
351 if (copy_planes &&
352 (tex->flushed_depth_texture ||
353 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
354 struct r600_texture *dst = tex->flushed_depth_texture;
355 unsigned fully_copied_levels;
356 unsigned levels = 0;
357
358 assert(tex->flushed_depth_texture);
359
360 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
361 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
362
363 if (copy_planes & PIPE_MASK_Z) {
364 levels |= levels_z;
365 levels_z = 0;
366 }
367 if (copy_planes & PIPE_MASK_S) {
368 levels |= levels_s;
369 levels_s = 0;
370 }
371
372 fully_copied_levels = si_blit_dbcb_copy(
373 sctx, tex, dst, copy_planes, levels,
374 first_layer, last_layer,
375 0, u_max_sample(&tex->resource.b.b));
376
377 if (copy_planes & PIPE_MASK_Z)
378 tex->dirty_level_mask &= ~fully_copied_levels;
379 if (copy_planes & PIPE_MASK_S)
380 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
381 }
382
383 if (inplace_planes) {
384 if (!tex->tc_compatible_htile) {
385 si_blit_decompress_zs_in_place(
386 sctx, tex,
387 levels_z, levels_s,
388 first_layer, last_layer);
389 }
390
391 /* Only in-place decompression needs to flush DB caches, or
392 * when we don't decompress but TC-compatible planes are dirty.
393 */
394 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
395 SI_CONTEXT_INV_GLOBAL_L2 |
396 SI_CONTEXT_INV_VMEM_L1;
397
398 /* If we flush DB caches for TC-compatible depth, the dirty
399 * state becomes 0 for the whole mipmap tree and all planes.
400 * (there is nothing else to flush)
401 */
402 if (tex->tc_compatible_htile) {
403 if (r600_can_sample_zs(tex, false))
404 tex->dirty_level_mask = 0;
405 if (r600_can_sample_zs(tex, true))
406 tex->stencil_dirty_level_mask = 0;
407 }
408 }
409 /* set_framebuffer_state takes care of coherency for single-sample.
410 * The DB->CB copy uses CB for the final writes.
411 */
412 if (copy_planes && tex->resource.b.b.nr_samples > 1) {
413 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
414 SI_CONTEXT_INV_GLOBAL_L2 |
415 SI_CONTEXT_FLUSH_AND_INV_CB;
416 }
417 }
418
419 static void
420 si_decompress_sampler_depth_textures(struct si_context *sctx,
421 struct si_textures_info *textures)
422 {
423 unsigned i;
424 unsigned mask = textures->needs_depth_decompress_mask;
425
426 while (mask) {
427 struct pipe_sampler_view *view;
428 struct si_sampler_view *sview;
429 struct r600_texture *tex;
430
431 i = u_bit_scan(&mask);
432
433 view = textures->views.views[i];
434 assert(view);
435 sview = (struct si_sampler_view*)view;
436
437 tex = (struct r600_texture *)view->texture;
438 assert(tex->db_compatible);
439
440 si_decompress_depth(sctx, tex,
441 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
442 view->u.tex.first_level, view->u.tex.last_level,
443 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
444 }
445 }
446
447 static void si_blit_decompress_color(struct pipe_context *ctx,
448 struct r600_texture *rtex,
449 unsigned first_level, unsigned last_level,
450 unsigned first_layer, unsigned last_layer,
451 bool need_dcc_decompress)
452 {
453 struct si_context *sctx = (struct si_context *)ctx;
454 void* custom_blend;
455 unsigned layer, checked_last_layer, max_layer;
456 unsigned level_mask =
457 u_bit_consecutive(first_level, last_level - first_level + 1);
458
459 if (!need_dcc_decompress)
460 level_mask &= rtex->dirty_level_mask;
461 if (!level_mask)
462 return;
463
464 if (unlikely(sctx->b.log))
465 u_log_printf(sctx->b.log,
466 "\n------------------------------------------------\n"
467 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
468 first_level, last_level, level_mask);
469
470 if (rtex->dcc_offset && need_dcc_decompress) {
471 custom_blend = sctx->custom_blend_dcc_decompress;
472
473 /* disable levels without DCC */
474 for (int i = first_level; i <= last_level; i++) {
475 if (!vi_dcc_enabled(rtex, i))
476 level_mask &= ~(1 << i);
477 }
478 } else if (rtex->fmask.size) {
479 custom_blend = sctx->custom_blend_fmask_decompress;
480 } else {
481 custom_blend = sctx->custom_blend_eliminate_fastclear;
482 }
483
484 sctx->decompression_enabled = true;
485
486 while (level_mask) {
487 unsigned level = u_bit_scan(&level_mask);
488
489 /* The smaller the mipmap level, the less layers there are
490 * as far as 3D textures are concerned. */
491 max_layer = util_max_layer(&rtex->resource.b.b, level);
492 checked_last_layer = MIN2(last_layer, max_layer);
493
494 for (layer = first_layer; layer <= checked_last_layer; layer++) {
495 struct pipe_surface *cbsurf, surf_tmpl;
496
497 surf_tmpl.format = rtex->resource.b.b.format;
498 surf_tmpl.u.tex.level = level;
499 surf_tmpl.u.tex.first_layer = layer;
500 surf_tmpl.u.tex.last_layer = layer;
501 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
502
503 /* Required before and after FMASK and DCC_DECOMPRESS. */
504 if (custom_blend == sctx->custom_blend_fmask_decompress ||
505 custom_blend == sctx->custom_blend_dcc_decompress)
506 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
507
508 si_blitter_begin(ctx, SI_DECOMPRESS);
509 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
510 si_blitter_end(ctx);
511
512 if (custom_blend == sctx->custom_blend_fmask_decompress ||
513 custom_blend == sctx->custom_blend_dcc_decompress)
514 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
515
516 pipe_surface_reference(&cbsurf, NULL);
517 }
518
519 /* The texture will always be dirty if some layers aren't flushed.
520 * I don't think this case occurs often though. */
521 if (first_layer == 0 && last_layer >= max_layer) {
522 rtex->dirty_level_mask &= ~(1 << level);
523 }
524 }
525
526 sctx->decompression_enabled = false;
527
528 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
529 SI_CONTEXT_INV_GLOBAL_L2 |
530 SI_CONTEXT_INV_VMEM_L1;
531 }
532
533 static void
534 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
535 unsigned first_level, unsigned last_level)
536 {
537 /* CMASK or DCC can be discarded and we can still end up here. */
538 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
539 return;
540
541 si_blit_decompress_color(&sctx->b.b, tex, first_level, last_level, 0,
542 util_max_layer(&tex->resource.b.b, first_level),
543 false);
544 }
545
546 static void
547 si_decompress_sampler_color_textures(struct si_context *sctx,
548 struct si_textures_info *textures)
549 {
550 unsigned i;
551 unsigned mask = textures->needs_color_decompress_mask;
552
553 while (mask) {
554 struct pipe_sampler_view *view;
555 struct r600_texture *tex;
556
557 i = u_bit_scan(&mask);
558
559 view = textures->views.views[i];
560 assert(view);
561
562 tex = (struct r600_texture *)view->texture;
563
564 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
565 view->u.tex.last_level);
566 }
567 }
568
569 static void
570 si_decompress_image_color_textures(struct si_context *sctx,
571 struct si_images_info *images)
572 {
573 unsigned i;
574 unsigned mask = images->needs_color_decompress_mask;
575
576 while (mask) {
577 const struct pipe_image_view *view;
578 struct r600_texture *tex;
579
580 i = u_bit_scan(&mask);
581
582 view = &images->views[i];
583 assert(view->resource->target != PIPE_BUFFER);
584
585 tex = (struct r600_texture *)view->resource;
586
587 si_decompress_color_texture(sctx, tex, view->u.tex.level,
588 view->u.tex.level);
589 }
590 }
591
592 static void si_check_render_feedback_texture(struct si_context *sctx,
593 struct r600_texture *tex,
594 unsigned first_level,
595 unsigned last_level,
596 unsigned first_layer,
597 unsigned last_layer)
598 {
599 bool render_feedback = false;
600
601 if (!tex->dcc_offset)
602 return;
603
604 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
605 struct r600_surface * surf;
606
607 if (!sctx->framebuffer.state.cbufs[j])
608 continue;
609
610 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
611
612 if (tex == (struct r600_texture *)surf->base.texture &&
613 surf->base.u.tex.level >= first_level &&
614 surf->base.u.tex.level <= last_level &&
615 surf->base.u.tex.first_layer <= last_layer &&
616 surf->base.u.tex.last_layer >= first_layer) {
617 render_feedback = true;
618 break;
619 }
620 }
621
622 if (render_feedback)
623 r600_texture_disable_dcc(&sctx->b, tex);
624 }
625
626 static void si_check_render_feedback_textures(struct si_context *sctx,
627 struct si_textures_info *textures)
628 {
629 uint32_t mask = textures->views.enabled_mask;
630
631 while (mask) {
632 const struct pipe_sampler_view *view;
633 struct r600_texture *tex;
634
635 unsigned i = u_bit_scan(&mask);
636
637 view = textures->views.views[i];
638 if(view->texture->target == PIPE_BUFFER)
639 continue;
640
641 tex = (struct r600_texture *)view->texture;
642
643 si_check_render_feedback_texture(sctx, tex,
644 view->u.tex.first_level,
645 view->u.tex.last_level,
646 view->u.tex.first_layer,
647 view->u.tex.last_layer);
648 }
649 }
650
651 static void si_check_render_feedback_images(struct si_context *sctx,
652 struct si_images_info *images)
653 {
654 uint32_t mask = images->enabled_mask;
655
656 while (mask) {
657 const struct pipe_image_view *view;
658 struct r600_texture *tex;
659
660 unsigned i = u_bit_scan(&mask);
661
662 view = &images->views[i];
663 if (view->resource->target == PIPE_BUFFER)
664 continue;
665
666 tex = (struct r600_texture *)view->resource;
667
668 si_check_render_feedback_texture(sctx, tex,
669 view->u.tex.level,
670 view->u.tex.level,
671 view->u.tex.first_layer,
672 view->u.tex.last_layer);
673 }
674 }
675
676 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
677 {
678 util_dynarray_foreach(&sctx->resident_tex_handles,
679 struct si_texture_handle *, tex_handle) {
680 struct pipe_sampler_view *view;
681 struct r600_texture *tex;
682
683 view = (*tex_handle)->view;
684 if (view->texture->target == PIPE_BUFFER)
685 continue;
686
687 tex = (struct r600_texture *)view->texture;
688
689 si_check_render_feedback_texture(sctx, tex,
690 view->u.tex.first_level,
691 view->u.tex.last_level,
692 view->u.tex.first_layer,
693 view->u.tex.last_layer);
694 }
695 }
696
697 static void si_check_render_feedback_resident_images(struct si_context *sctx)
698 {
699 util_dynarray_foreach(&sctx->resident_img_handles,
700 struct si_image_handle *, img_handle) {
701 struct pipe_image_view *view;
702 struct r600_texture *tex;
703
704 view = &(*img_handle)->view;
705 if (view->resource->target == PIPE_BUFFER)
706 continue;
707
708 tex = (struct r600_texture *)view->resource;
709
710 si_check_render_feedback_texture(sctx, tex,
711 view->u.tex.level,
712 view->u.tex.level,
713 view->u.tex.first_layer,
714 view->u.tex.last_layer);
715 }
716 }
717
718 static void si_check_render_feedback(struct si_context *sctx)
719 {
720
721 if (!sctx->need_check_render_feedback)
722 return;
723
724 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
725 si_check_render_feedback_images(sctx, &sctx->images[i]);
726 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
727 }
728
729 si_check_render_feedback_resident_images(sctx);
730 si_check_render_feedback_resident_textures(sctx);
731
732 sctx->need_check_render_feedback = false;
733 }
734
735 static void si_decompress_resident_textures(struct si_context *sctx)
736 {
737 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
738 struct si_texture_handle *, tex_handle) {
739 struct pipe_sampler_view *view = (*tex_handle)->view;
740 struct r600_texture *tex = (struct r600_texture *)view->texture;
741
742 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
743 view->u.tex.last_level);
744 }
745
746 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
747 struct si_texture_handle *, tex_handle) {
748 struct pipe_sampler_view *view = (*tex_handle)->view;
749 struct si_sampler_view *sview = (struct si_sampler_view *)view;
750 struct r600_texture *tex = (struct r600_texture *)view->texture;
751
752 si_decompress_depth(sctx, tex,
753 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
754 view->u.tex.first_level, view->u.tex.last_level,
755 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
756 }
757 }
758
759 static void si_decompress_resident_images(struct si_context *sctx)
760 {
761 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
762 struct si_image_handle *, img_handle) {
763 struct pipe_image_view *view = &(*img_handle)->view;
764 struct r600_texture *tex = (struct r600_texture *)view->resource;
765
766 si_decompress_color_texture(sctx, tex, view->u.tex.level,
767 view->u.tex.level);
768 }
769 }
770
771 static void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
772 {
773 unsigned compressed_colortex_counter, mask;
774
775 if (sctx->blitter->running)
776 return;
777
778 /* Update the compressed_colortex_mask if necessary. */
779 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
780 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
781 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
782 si_update_needs_color_decompress_masks(sctx);
783 }
784
785 /* Decompress color & depth textures if needed. */
786 mask = sctx->shader_needs_decompress_mask & shader_mask;
787 while (mask) {
788 unsigned i = u_bit_scan(&mask);
789
790 if (sctx->samplers[i].needs_depth_decompress_mask) {
791 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
792 }
793 if (sctx->samplers[i].needs_color_decompress_mask) {
794 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
795 }
796 if (sctx->images[i].needs_color_decompress_mask) {
797 si_decompress_image_color_textures(sctx, &sctx->images[i]);
798 }
799 }
800
801 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
802 if (sctx->uses_bindless_samplers)
803 si_decompress_resident_textures(sctx);
804 if (sctx->uses_bindless_images)
805 si_decompress_resident_images(sctx);
806 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
807 if (sctx->cs_shader_state.program->uses_bindless_samplers)
808 si_decompress_resident_textures(sctx);
809 if (sctx->cs_shader_state.program->uses_bindless_images)
810 si_decompress_resident_images(sctx);
811 }
812
813 si_check_render_feedback(sctx);
814 }
815
816 void si_decompress_graphics_textures(struct si_context *sctx)
817 {
818 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
819 }
820
821 void si_decompress_compute_textures(struct si_context *sctx)
822 {
823 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
824 }
825
826 static void si_clear(struct pipe_context *ctx, unsigned buffers,
827 const union pipe_color_union *color,
828 double depth, unsigned stencil)
829 {
830 struct si_context *sctx = (struct si_context *)ctx;
831 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
832 struct pipe_surface *zsbuf = fb->zsbuf;
833 struct r600_texture *zstex =
834 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
835
836 if (buffers & PIPE_CLEAR_COLOR) {
837 evergreen_do_fast_color_clear(&sctx->b, fb,
838 &sctx->framebuffer.atom, &buffers,
839 &sctx->framebuffer.dirty_cbufs,
840 color);
841 if (!buffers)
842 return; /* all buffers have been fast cleared */
843 }
844
845 if (buffers & PIPE_CLEAR_COLOR) {
846 int i;
847
848 /* These buffers cannot use fast clear, make sure to disable expansion. */
849 for (i = 0; i < fb->nr_cbufs; i++) {
850 struct r600_texture *tex;
851
852 /* If not clearing this buffer, skip. */
853 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
854 continue;
855
856 if (!fb->cbufs[i])
857 continue;
858
859 tex = (struct r600_texture *)fb->cbufs[i]->texture;
860 if (tex->fmask.size == 0)
861 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
862 }
863 }
864
865 if (zstex && zstex->htile_offset &&
866 zsbuf->u.tex.level == 0 &&
867 zsbuf->u.tex.first_layer == 0 &&
868 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
869 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
870 if (buffers & PIPE_CLEAR_DEPTH &&
871 (!zstex->tc_compatible_htile ||
872 depth == 0 || depth == 1)) {
873 /* Need to disable EXPCLEAR temporarily if clearing
874 * to a new value. */
875 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
876 sctx->db_depth_disable_expclear = true;
877 }
878
879 zstex->depth_clear_value = depth;
880 sctx->framebuffer.dirty_zsbuf = true;
881 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
882 sctx->db_depth_clear = true;
883 si_mark_atom_dirty(sctx, &sctx->db_render_state);
884 }
885
886 /* TC-compatible HTILE only supports stencil clears to 0. */
887 if (buffers & PIPE_CLEAR_STENCIL &&
888 (!zstex->tc_compatible_htile || stencil == 0)) {
889 stencil &= 0xff;
890
891 /* Need to disable EXPCLEAR temporarily if clearing
892 * to a new value. */
893 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
894 sctx->db_stencil_disable_expclear = true;
895 }
896
897 zstex->stencil_clear_value = stencil;
898 sctx->framebuffer.dirty_zsbuf = true;
899 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
900 sctx->db_stencil_clear = true;
901 si_mark_atom_dirty(sctx, &sctx->db_render_state);
902 }
903 }
904
905 si_blitter_begin(ctx, SI_CLEAR);
906 util_blitter_clear(sctx->blitter, fb->width, fb->height,
907 util_framebuffer_get_num_layers(fb),
908 buffers, color, depth, stencil);
909 si_blitter_end(ctx);
910
911 if (sctx->db_depth_clear) {
912 sctx->db_depth_clear = false;
913 sctx->db_depth_disable_expclear = false;
914 zstex->depth_cleared = true;
915 si_mark_atom_dirty(sctx, &sctx->db_render_state);
916 }
917
918 if (sctx->db_stencil_clear) {
919 sctx->db_stencil_clear = false;
920 sctx->db_stencil_disable_expclear = false;
921 zstex->stencil_cleared = true;
922 si_mark_atom_dirty(sctx, &sctx->db_render_state);
923 }
924 }
925
926 static void si_clear_render_target(struct pipe_context *ctx,
927 struct pipe_surface *dst,
928 const union pipe_color_union *color,
929 unsigned dstx, unsigned dsty,
930 unsigned width, unsigned height,
931 bool render_condition_enabled)
932 {
933 struct si_context *sctx = (struct si_context *)ctx;
934
935 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
936 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
937 util_blitter_clear_render_target(sctx->blitter, dst, color,
938 dstx, dsty, width, height);
939 si_blitter_end(ctx);
940 }
941
942 static void si_clear_depth_stencil(struct pipe_context *ctx,
943 struct pipe_surface *dst,
944 unsigned clear_flags,
945 double depth,
946 unsigned stencil,
947 unsigned dstx, unsigned dsty,
948 unsigned width, unsigned height,
949 bool render_condition_enabled)
950 {
951 struct si_context *sctx = (struct si_context *)ctx;
952
953 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
954 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
955 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
956 dstx, dsty, width, height);
957 si_blitter_end(ctx);
958 }
959
960 /* Helper for decompressing a portion of a color or depth resource before
961 * blitting if any decompression is needed.
962 * The driver doesn't decompress resources automatically while u_blitter is
963 * rendering. */
964 static void si_decompress_subresource(struct pipe_context *ctx,
965 struct pipe_resource *tex,
966 unsigned planes, unsigned level,
967 unsigned first_layer, unsigned last_layer)
968 {
969 struct si_context *sctx = (struct si_context *)ctx;
970 struct r600_texture *rtex = (struct r600_texture*)tex;
971
972 if (rtex->db_compatible) {
973 planes &= PIPE_MASK_Z | PIPE_MASK_S;
974
975 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
976 planes &= ~PIPE_MASK_S;
977
978 /* If we've rendered into the framebuffer and it's a blitting
979 * source, make sure the decompression pass is invoked
980 * by dirtying the framebuffer.
981 */
982 if (sctx->framebuffer.state.zsbuf &&
983 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
984 sctx->framebuffer.state.zsbuf->texture == tex)
985 si_update_fb_dirtiness_after_rendering(sctx);
986
987 si_decompress_depth(sctx, rtex, planes,
988 level, level,
989 first_layer, last_layer);
990 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
991 /* If we've rendered into the framebuffer and it's a blitting
992 * source, make sure the decompression pass is invoked
993 * by dirtying the framebuffer.
994 */
995 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
996 if (sctx->framebuffer.state.cbufs[i] &&
997 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
998 sctx->framebuffer.state.cbufs[i]->texture == tex) {
999 si_update_fb_dirtiness_after_rendering(sctx);
1000 break;
1001 }
1002 }
1003
1004 si_blit_decompress_color(ctx, rtex, level, level,
1005 first_layer, last_layer, false);
1006 }
1007 }
1008
1009 struct texture_orig_info {
1010 unsigned format;
1011 unsigned width0;
1012 unsigned height0;
1013 unsigned npix_x;
1014 unsigned npix_y;
1015 unsigned npix0_x;
1016 unsigned npix0_y;
1017 };
1018
1019 void si_resource_copy_region(struct pipe_context *ctx,
1020 struct pipe_resource *dst,
1021 unsigned dst_level,
1022 unsigned dstx, unsigned dsty, unsigned dstz,
1023 struct pipe_resource *src,
1024 unsigned src_level,
1025 const struct pipe_box *src_box)
1026 {
1027 struct si_context *sctx = (struct si_context *)ctx;
1028 struct r600_texture *rsrc = (struct r600_texture*)src;
1029 struct pipe_surface *dst_view, dst_templ;
1030 struct pipe_sampler_view src_templ, *src_view;
1031 unsigned dst_width, dst_height, src_width0, src_height0;
1032 unsigned dst_width0, dst_height0, src_force_level = 0;
1033 struct pipe_box sbox, dstbox;
1034
1035 /* Handle buffers first. */
1036 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
1037 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
1038 return;
1039 }
1040
1041 assert(u_max_sample(dst) == u_max_sample(src));
1042
1043 /* The driver doesn't decompress resources automatically while
1044 * u_blitter is rendering. */
1045 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
1046 src_box->z, src_box->z + src_box->depth - 1);
1047
1048 dst_width = u_minify(dst->width0, dst_level);
1049 dst_height = u_minify(dst->height0, dst_level);
1050 dst_width0 = dst->width0;
1051 dst_height0 = dst->height0;
1052 src_width0 = src->width0;
1053 src_height0 = src->height0;
1054
1055 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
1056 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
1057
1058 if (util_format_is_compressed(src->format) ||
1059 util_format_is_compressed(dst->format)) {
1060 unsigned blocksize = rsrc->surface.bpe;
1061
1062 if (blocksize == 8)
1063 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
1064 else
1065 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
1066 dst_templ.format = src_templ.format;
1067
1068 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1069 dst_height = util_format_get_nblocksy(dst->format, dst_height);
1070 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1071 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
1072 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1073 src_height0 = util_format_get_nblocksy(src->format, src_height0);
1074
1075 dstx = util_format_get_nblocksx(dst->format, dstx);
1076 dsty = util_format_get_nblocksy(dst->format, dsty);
1077
1078 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1079 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
1080 sbox.z = src_box->z;
1081 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1082 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
1083 sbox.depth = src_box->depth;
1084 src_box = &sbox;
1085
1086 src_force_level = src_level;
1087 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
1088 if (util_format_is_subsampled_422(src->format)) {
1089 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1090 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1091
1092 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1093 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1094 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1095
1096 dstx = util_format_get_nblocksx(dst->format, dstx);
1097
1098 sbox = *src_box;
1099 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1100 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1101 src_box = &sbox;
1102 } else {
1103 unsigned blocksize = rsrc->surface.bpe;
1104
1105 switch (blocksize) {
1106 case 1:
1107 dst_templ.format = PIPE_FORMAT_R8_UNORM;
1108 src_templ.format = PIPE_FORMAT_R8_UNORM;
1109 break;
1110 case 2:
1111 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
1112 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
1113 break;
1114 case 4:
1115 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1116 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1117 break;
1118 case 8:
1119 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1120 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1121 break;
1122 case 16:
1123 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1124 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1125 break;
1126 default:
1127 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1128 util_format_short_name(src->format), blocksize);
1129 assert(0);
1130 }
1131 }
1132 }
1133
1134 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1135 * equivalent instead, which doesn't force DCC decompression.
1136 * Note that some chips avoid this issue by using SDMA.
1137 */
1138 if (util_format_is_snorm8(dst_templ.format)) {
1139 switch (dst_templ.format) {
1140 case PIPE_FORMAT_R8_SNORM:
1141 dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
1142 break;
1143 case PIPE_FORMAT_R8G8_SNORM:
1144 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
1145 break;
1146 case PIPE_FORMAT_R8G8B8X8_SNORM:
1147 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
1148 break;
1149 case PIPE_FORMAT_R8G8B8A8_SNORM:
1150 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1151 case PIPE_FORMAT_A8B8G8R8_SNORM:
1152 case PIPE_FORMAT_X8B8G8R8_SNORM:
1153 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
1154 break;
1155 case PIPE_FORMAT_A8_SNORM:
1156 dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
1157 break;
1158 case PIPE_FORMAT_L8_SNORM:
1159 dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
1160 break;
1161 case PIPE_FORMAT_L8A8_SNORM:
1162 dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
1163 break;
1164 case PIPE_FORMAT_I8_SNORM:
1165 dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
1166 break;
1167 default:; /* fall through */
1168 }
1169 }
1170
1171 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
1172 dst_templ.format);
1173 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
1174 src_templ.format);
1175
1176 /* Initialize the surface. */
1177 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
1178 dst_width0, dst_height0,
1179 dst_width, dst_height);
1180
1181 /* Initialize the sampler view. */
1182 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1183 src_width0, src_height0,
1184 src_force_level);
1185
1186 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1187 abs(src_box->depth), &dstbox);
1188
1189 /* Copy. */
1190 si_blitter_begin(ctx, SI_COPY);
1191 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1192 src_view, src_box, src_width0, src_height0,
1193 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1194 false);
1195 si_blitter_end(ctx);
1196
1197 pipe_surface_reference(&dst_view, NULL);
1198 pipe_sampler_view_reference(&src_view, NULL);
1199 }
1200
1201 static void si_do_CB_resolve(struct si_context *sctx,
1202 const struct pipe_blit_info *info,
1203 struct pipe_resource *dst,
1204 unsigned dst_level, unsigned dst_z,
1205 enum pipe_format format)
1206 {
1207 /* Required before and after CB_RESOLVE. */
1208 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1209
1210 si_blitter_begin(&sctx->b.b, SI_COLOR_RESOLVE |
1211 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1212 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1213 info->src.resource, info->src.box.z,
1214 ~0, sctx->custom_blend_resolve,
1215 format);
1216 si_blitter_end(&sctx->b.b);
1217
1218 /* Flush caches for possible texturing. */
1219 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1220 SI_CONTEXT_INV_GLOBAL_L2 |
1221 SI_CONTEXT_INV_VMEM_L1;
1222 }
1223
1224 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1225 const struct pipe_blit_info *info)
1226 {
1227 struct si_context *sctx = (struct si_context*)ctx;
1228 struct r600_texture *src = (struct r600_texture*)info->src.resource;
1229 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
1230 MAYBE_UNUSED struct r600_texture *rtmp;
1231 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1232 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1233 enum pipe_format format = info->src.format;
1234 struct pipe_resource *tmp, templ;
1235 struct pipe_blit_info blit;
1236
1237 /* Check basic requirements for hw resolve. */
1238 if (!(info->src.resource->nr_samples > 1 &&
1239 info->dst.resource->nr_samples <= 1 &&
1240 !util_format_is_pure_integer(format) &&
1241 !util_format_is_depth_or_stencil(format) &&
1242 util_max_layer(info->src.resource, 0) == 0))
1243 return false;
1244
1245 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1246 * the format is R16G16. Use R16A16, which does work.
1247 */
1248 if (format == PIPE_FORMAT_R16G16_UNORM)
1249 format = PIPE_FORMAT_R16A16_UNORM;
1250 if (format == PIPE_FORMAT_R16G16_SNORM)
1251 format = PIPE_FORMAT_R16A16_SNORM;
1252
1253 /* Check the remaining requirements for hw resolve. */
1254 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1255 !info->scissor_enable &&
1256 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1257 util_is_format_compatible(util_format_description(info->src.format),
1258 util_format_description(info->dst.format)) &&
1259 dst_width == info->src.resource->width0 &&
1260 dst_height == info->src.resource->height0 &&
1261 info->dst.box.x == 0 &&
1262 info->dst.box.y == 0 &&
1263 info->dst.box.width == dst_width &&
1264 info->dst.box.height == dst_height &&
1265 info->dst.box.depth == 1 &&
1266 info->src.box.x == 0 &&
1267 info->src.box.y == 0 &&
1268 info->src.box.width == dst_width &&
1269 info->src.box.height == dst_height &&
1270 info->src.box.depth == 1 &&
1271 !dst->surface.is_linear &&
1272 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1273 /* Check the last constraint. */
1274 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1275 /* The next fast clear will switch to this mode to
1276 * get direct hw resolve next time if the mode is
1277 * different now.
1278 */
1279 src->last_msaa_resolve_target_micro_mode =
1280 dst->surface.micro_tile_mode;
1281 goto resolve_to_temp;
1282 }
1283
1284 /* Resolving into a surface with DCC is unsupported. Since
1285 * it's being overwritten anyway, clear it to uncompressed.
1286 * This is still the fastest codepath even with this clear.
1287 */
1288 if (vi_dcc_enabled(dst, info->dst.level)) {
1289 /* TODO: Implement per-level DCC clears for GFX9. */
1290 if (sctx->b.chip_class >= GFX9 &&
1291 info->dst.resource->last_level != 0)
1292 goto resolve_to_temp;
1293
1294 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1295 0xFFFFFFFF);
1296 dst->dirty_level_mask &= ~(1 << info->dst.level);
1297 }
1298
1299 /* Resolve directly from src to dst. */
1300 si_do_CB_resolve(sctx, info, info->dst.resource,
1301 info->dst.level, info->dst.box.z, format);
1302 return true;
1303 }
1304
1305 resolve_to_temp:
1306 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1307 * a temporary texture and blit.
1308 */
1309 memset(&templ, 0, sizeof(templ));
1310 templ.target = PIPE_TEXTURE_2D;
1311 templ.format = info->src.resource->format;
1312 templ.width0 = info->src.resource->width0;
1313 templ.height0 = info->src.resource->height0;
1314 templ.depth0 = 1;
1315 templ.array_size = 1;
1316 templ.usage = PIPE_USAGE_DEFAULT;
1317 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1318 R600_RESOURCE_FLAG_DISABLE_DCC;
1319
1320 /* The src and dst microtile modes must be the same. */
1321 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1322 templ.bind = PIPE_BIND_SCANOUT;
1323 else
1324 templ.bind = 0;
1325
1326 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1327 if (!tmp)
1328 return false;
1329 rtmp = (struct r600_texture*)tmp;
1330
1331 assert(!rtmp->surface.is_linear);
1332 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1333
1334 /* resolve */
1335 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1336
1337 /* blit */
1338 blit = *info;
1339 blit.src.resource = tmp;
1340 blit.src.box.z = 0;
1341
1342 si_blitter_begin(ctx, SI_BLIT |
1343 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1344 util_blitter_blit(sctx->blitter, &blit);
1345 si_blitter_end(ctx);
1346
1347 pipe_resource_reference(&tmp, NULL);
1348 return true;
1349 }
1350
1351 static void si_blit(struct pipe_context *ctx,
1352 const struct pipe_blit_info *info)
1353 {
1354 struct si_context *sctx = (struct si_context*)ctx;
1355 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1356
1357 if (do_hardware_msaa_resolve(ctx, info)) {
1358 return;
1359 }
1360
1361 /* Using SDMA for copying to a linear texture in GTT is much faster.
1362 * This improves DRI PRIME performance.
1363 *
1364 * resource_copy_region can't do this yet, because dma_copy calls it
1365 * on failure (recursion).
1366 */
1367 if (rdst->surface.is_linear &&
1368 sctx->b.dma_copy &&
1369 util_can_blit_via_copy_region(info, false)) {
1370 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1371 info->dst.box.x, info->dst.box.y,
1372 info->dst.box.z,
1373 info->src.resource, info->src.level,
1374 &info->src.box);
1375 return;
1376 }
1377
1378 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1379
1380 /* The driver doesn't decompress resources automatically while
1381 * u_blitter is rendering. */
1382 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1383 info->src.level,
1384 info->src.format);
1385 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1386 info->dst.level,
1387 info->dst.format);
1388 si_decompress_subresource(ctx, info->src.resource, info->mask,
1389 info->src.level,
1390 info->src.box.z,
1391 info->src.box.z + info->src.box.depth - 1);
1392
1393 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1394 util_try_blit_via_copy_region(ctx, info))
1395 return;
1396
1397 si_blitter_begin(ctx, SI_BLIT |
1398 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1399 util_blitter_blit(sctx->blitter, info);
1400 si_blitter_end(ctx);
1401 }
1402
1403 static boolean si_generate_mipmap(struct pipe_context *ctx,
1404 struct pipe_resource *tex,
1405 enum pipe_format format,
1406 unsigned base_level, unsigned last_level,
1407 unsigned first_layer, unsigned last_layer)
1408 {
1409 struct si_context *sctx = (struct si_context*)ctx;
1410 struct r600_texture *rtex = (struct r600_texture *)tex;
1411
1412 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1413 return false;
1414
1415 /* The driver doesn't decompress resources automatically while
1416 * u_blitter is rendering. */
1417 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1418 format);
1419 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1420 base_level, first_layer, last_layer);
1421
1422 /* Clear dirty_level_mask for the levels that will be overwritten. */
1423 assert(base_level < last_level);
1424 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1425 last_level - base_level);
1426
1427 sctx->generate_mipmap_for_depth = rtex->is_depth;
1428
1429 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1430 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1431 base_level, last_level,
1432 first_layer, last_layer);
1433 si_blitter_end(ctx);
1434
1435 sctx->generate_mipmap_for_depth = false;
1436 return true;
1437 }
1438
1439 static void si_flush_resource(struct pipe_context *ctx,
1440 struct pipe_resource *res)
1441 {
1442 struct r600_texture *rtex = (struct r600_texture*)res;
1443
1444 assert(res->target != PIPE_BUFFER);
1445 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1446
1447 /* st/dri calls flush twice per frame (not a bug), this prevents double
1448 * decompression. */
1449 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1450 return;
1451
1452 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1453 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1454 0, util_max_layer(res, 0),
1455 rtex->dcc_separate_buffer != NULL);
1456 }
1457
1458 /* Always do the analysis even if DCC is disabled at the moment. */
1459 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1460 rtex->separate_dcc_dirty = false;
1461 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1462 }
1463 }
1464
1465 static void si_decompress_dcc(struct pipe_context *ctx,
1466 struct r600_texture *rtex)
1467 {
1468 if (!rtex->dcc_offset)
1469 return;
1470
1471 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1472 0, util_max_layer(&rtex->resource.b.b, 0),
1473 true);
1474 }
1475
1476 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1477 struct pipe_resource *dst,
1478 unsigned offset, unsigned size,
1479 const void *clear_value_ptr,
1480 int clear_value_size)
1481 {
1482 struct si_context *sctx = (struct si_context*)ctx;
1483 uint32_t dword_value;
1484 unsigned i;
1485
1486 assert(offset % clear_value_size == 0);
1487 assert(size % clear_value_size == 0);
1488
1489 if (clear_value_size > 4) {
1490 const uint32_t *u32 = clear_value_ptr;
1491 bool clear_dword_duplicated = true;
1492
1493 /* See if we can lower large fills to dword fills. */
1494 for (i = 1; i < clear_value_size / 4; i++)
1495 if (u32[0] != u32[i]) {
1496 clear_dword_duplicated = false;
1497 break;
1498 }
1499
1500 if (!clear_dword_duplicated) {
1501 /* Use transform feedback for 64-bit, 96-bit, and
1502 * 128-bit fills.
1503 */
1504 union pipe_color_union clear_value;
1505
1506 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1507 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1508 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1509 size, clear_value_size / 4,
1510 &clear_value);
1511 si_blitter_end(ctx);
1512 return;
1513 }
1514 }
1515
1516 /* Expand the clear value to a dword. */
1517 switch (clear_value_size) {
1518 case 1:
1519 dword_value = *(uint8_t*)clear_value_ptr;
1520 dword_value |= (dword_value << 8) |
1521 (dword_value << 16) |
1522 (dword_value << 24);
1523 break;
1524 case 2:
1525 dword_value = *(uint16_t*)clear_value_ptr;
1526 dword_value |= dword_value << 16;
1527 break;
1528 default:
1529 dword_value = *(uint32_t*)clear_value_ptr;
1530 }
1531
1532 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1533 R600_COHERENCY_SHADER);
1534 }
1535
1536 void si_init_blit_functions(struct si_context *sctx)
1537 {
1538 sctx->b.b.clear = si_clear;
1539 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1540 sctx->b.b.clear_render_target = si_clear_render_target;
1541 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1542 sctx->b.b.resource_copy_region = si_resource_copy_region;
1543 sctx->b.b.blit = si_blit;
1544 sctx->b.b.flush_resource = si_flush_resource;
1545 sctx->b.b.generate_mipmap = si_generate_mipmap;
1546 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1547 sctx->b.decompress_dcc = si_decompress_dcc;
1548 }