2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "si_compute.h"
28 #include "util/format/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_surface.h"
35 SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
| SI_SAVE_FRAGMENT_STATE
| SI_DISABLE_RENDER_COND
,
37 SI_BLIT
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
| SI_SAVE_FRAGMENT_STATE
,
39 SI_DECOMPRESS
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
| SI_DISABLE_RENDER_COND
,
41 SI_COLOR_RESOLVE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
44 void si_blitter_begin(struct si_context
*sctx
, enum si_blitter_op op
)
46 util_blitter_save_vertex_shader(sctx
->blitter
, sctx
->vs_shader
.cso
);
47 util_blitter_save_tessctrl_shader(sctx
->blitter
, sctx
->tcs_shader
.cso
);
48 util_blitter_save_tesseval_shader(sctx
->blitter
, sctx
->tes_shader
.cso
);
49 util_blitter_save_geometry_shader(sctx
->blitter
, sctx
->gs_shader
.cso
);
50 util_blitter_save_so_targets(sctx
->blitter
, sctx
->streamout
.num_targets
,
51 (struct pipe_stream_output_target
**)sctx
->streamout
.targets
);
52 util_blitter_save_rasterizer(sctx
->blitter
, sctx
->queued
.named
.rasterizer
);
54 if (op
& SI_SAVE_FRAGMENT_STATE
) {
55 util_blitter_save_blend(sctx
->blitter
, sctx
->queued
.named
.blend
);
56 util_blitter_save_depth_stencil_alpha(sctx
->blitter
, sctx
->queued
.named
.dsa
);
57 util_blitter_save_stencil_ref(sctx
->blitter
, &sctx
->stencil_ref
.state
);
58 util_blitter_save_fragment_shader(sctx
->blitter
, sctx
->ps_shader
.cso
);
59 util_blitter_save_sample_mask(sctx
->blitter
, sctx
->sample_mask
);
60 util_blitter_save_scissor(sctx
->blitter
, &sctx
->scissors
[0]);
61 util_blitter_save_window_rectangles(sctx
->blitter
, sctx
->window_rectangles_include
,
62 sctx
->num_window_rectangles
, sctx
->window_rectangles
);
65 if (op
& SI_SAVE_FRAMEBUFFER
)
66 util_blitter_save_framebuffer(sctx
->blitter
, &sctx
->framebuffer
.state
);
68 if (op
& SI_SAVE_TEXTURES
) {
69 util_blitter_save_fragment_sampler_states(
70 sctx
->blitter
, 2, (void **)sctx
->samplers
[PIPE_SHADER_FRAGMENT
].sampler_states
);
72 util_blitter_save_fragment_sampler_views(sctx
->blitter
, 2,
73 sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
);
76 if (op
& SI_DISABLE_RENDER_COND
)
77 sctx
->render_cond_force_off
= true;
79 if (sctx
->screen
->dpbb_allowed
) {
80 sctx
->dpbb_force_off
= true;
81 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
85 void si_blitter_end(struct si_context
*sctx
)
87 if (sctx
->screen
->dpbb_allowed
) {
88 sctx
->dpbb_force_off
= false;
89 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
92 sctx
->render_cond_force_off
= false;
94 /* Restore shader pointers because the VS blit shader changed all
95 * non-global VS user SGPRs. */
96 sctx
->shader_pointers_dirty
|= SI_DESCS_SHADER_MASK(VERTEX
);
97 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
98 sctx
->vertex_buffer_user_sgprs_dirty
= sctx
->num_vertex_elements
> 0;
99 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.shader_pointers
);
102 static unsigned u_max_sample(struct pipe_resource
*r
)
104 return r
->nr_samples
? r
->nr_samples
- 1 : 0;
107 static unsigned si_blit_dbcb_copy(struct si_context
*sctx
, struct si_texture
*src
,
108 struct si_texture
*dst
, unsigned planes
, unsigned level_mask
,
109 unsigned first_layer
, unsigned last_layer
, unsigned first_sample
,
110 unsigned last_sample
)
112 struct pipe_surface surf_tmpl
= {{0}};
113 unsigned layer
, sample
, checked_last_layer
, max_layer
;
114 unsigned fully_copied_levels
= 0;
116 if (planes
& PIPE_MASK_Z
)
117 sctx
->dbcb_depth_copy_enabled
= true;
118 if (planes
& PIPE_MASK_S
)
119 sctx
->dbcb_stencil_copy_enabled
= true;
120 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
122 assert(sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
);
124 sctx
->decompression_enabled
= true;
127 unsigned level
= u_bit_scan(&level_mask
);
129 /* The smaller the mipmap level, the less layers there are
130 * as far as 3D textures are concerned. */
131 max_layer
= util_max_layer(&src
->buffer
.b
.b
, level
);
132 checked_last_layer
= MIN2(last_layer
, max_layer
);
134 surf_tmpl
.u
.tex
.level
= level
;
136 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
137 struct pipe_surface
*zsurf
, *cbsurf
;
139 surf_tmpl
.format
= src
->buffer
.b
.b
.format
;
140 surf_tmpl
.u
.tex
.first_layer
= layer
;
141 surf_tmpl
.u
.tex
.last_layer
= layer
;
143 zsurf
= sctx
->b
.create_surface(&sctx
->b
, &src
->buffer
.b
.b
, &surf_tmpl
);
145 surf_tmpl
.format
= dst
->buffer
.b
.b
.format
;
146 cbsurf
= sctx
->b
.create_surface(&sctx
->b
, &dst
->buffer
.b
.b
, &surf_tmpl
);
148 for (sample
= first_sample
; sample
<= last_sample
; sample
++) {
149 if (sample
!= sctx
->dbcb_copy_sample
) {
150 sctx
->dbcb_copy_sample
= sample
;
151 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
154 si_blitter_begin(sctx
, SI_DECOMPRESS
);
155 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, cbsurf
, 1 << sample
,
156 sctx
->custom_dsa_flush
, 1.0f
);
157 si_blitter_end(sctx
);
160 pipe_surface_reference(&zsurf
, NULL
);
161 pipe_surface_reference(&cbsurf
, NULL
);
164 if (first_layer
== 0 && last_layer
>= max_layer
&& first_sample
== 0 &&
165 last_sample
>= u_max_sample(&src
->buffer
.b
.b
))
166 fully_copied_levels
|= 1u << level
;
169 sctx
->decompression_enabled
= false;
170 sctx
->dbcb_depth_copy_enabled
= false;
171 sctx
->dbcb_stencil_copy_enabled
= false;
172 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
174 return fully_copied_levels
;
177 /* Helper function for si_blit_decompress_zs_in_place.
179 static void si_blit_decompress_zs_planes_in_place(struct si_context
*sctx
,
180 struct si_texture
*texture
, unsigned planes
,
181 unsigned level_mask
, unsigned first_layer
,
184 struct pipe_surface
*zsurf
, surf_tmpl
= {{0}};
185 unsigned layer
, max_layer
, checked_last_layer
;
186 unsigned fully_decompressed_mask
= 0;
191 if (planes
& PIPE_MASK_S
)
192 sctx
->db_flush_stencil_inplace
= true;
193 if (planes
& PIPE_MASK_Z
)
194 sctx
->db_flush_depth_inplace
= true;
195 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
197 surf_tmpl
.format
= texture
->buffer
.b
.b
.format
;
199 sctx
->decompression_enabled
= true;
202 unsigned level
= u_bit_scan(&level_mask
);
204 surf_tmpl
.u
.tex
.level
= level
;
206 /* The smaller the mipmap level, the less layers there are
207 * as far as 3D textures are concerned. */
208 max_layer
= util_max_layer(&texture
->buffer
.b
.b
, level
);
209 checked_last_layer
= MIN2(last_layer
, max_layer
);
211 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
212 surf_tmpl
.u
.tex
.first_layer
= layer
;
213 surf_tmpl
.u
.tex
.last_layer
= layer
;
215 zsurf
= sctx
->b
.create_surface(&sctx
->b
, &texture
->buffer
.b
.b
, &surf_tmpl
);
217 si_blitter_begin(sctx
, SI_DECOMPRESS
);
218 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, NULL
, ~0, sctx
->custom_dsa_flush
,
220 si_blitter_end(sctx
);
222 pipe_surface_reference(&zsurf
, NULL
);
225 /* The texture will always be dirty if some layers aren't flushed.
226 * I don't think this case occurs often though. */
227 if (first_layer
== 0 && last_layer
>= max_layer
) {
228 fully_decompressed_mask
|= 1u << level
;
232 if (planes
& PIPE_MASK_Z
)
233 texture
->dirty_level_mask
&= ~fully_decompressed_mask
;
234 if (planes
& PIPE_MASK_S
)
235 texture
->stencil_dirty_level_mask
&= ~fully_decompressed_mask
;
237 sctx
->decompression_enabled
= false;
238 sctx
->db_flush_depth_inplace
= false;
239 sctx
->db_flush_stencil_inplace
= false;
240 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
243 /* Helper function of si_flush_depth_texture: decompress the given levels
244 * of Z and/or S planes in place.
246 static void si_blit_decompress_zs_in_place(struct si_context
*sctx
, struct si_texture
*texture
,
247 unsigned levels_z
, unsigned levels_s
,
248 unsigned first_layer
, unsigned last_layer
)
250 unsigned both
= levels_z
& levels_s
;
252 /* First, do combined Z & S decompresses for levels that need it. */
254 si_blit_decompress_zs_planes_in_place(sctx
, texture
, PIPE_MASK_Z
| PIPE_MASK_S
, both
,
255 first_layer
, last_layer
);
260 /* Now do separate Z and S decompresses. */
262 si_blit_decompress_zs_planes_in_place(sctx
, texture
, PIPE_MASK_Z
, levels_z
, first_layer
,
267 si_blit_decompress_zs_planes_in_place(sctx
, texture
, PIPE_MASK_S
, levels_s
, first_layer
,
272 static void si_decompress_depth(struct si_context
*sctx
, struct si_texture
*tex
,
273 unsigned required_planes
, unsigned first_level
, unsigned last_level
,
274 unsigned first_layer
, unsigned last_layer
)
276 unsigned inplace_planes
= 0;
277 unsigned copy_planes
= 0;
278 unsigned level_mask
= u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
279 unsigned levels_z
= 0;
280 unsigned levels_s
= 0;
282 if (required_planes
& PIPE_MASK_Z
) {
283 levels_z
= level_mask
& tex
->dirty_level_mask
;
286 if (si_can_sample_zs(tex
, false))
287 inplace_planes
|= PIPE_MASK_Z
;
289 copy_planes
|= PIPE_MASK_Z
;
292 if (required_planes
& PIPE_MASK_S
) {
293 levels_s
= level_mask
& tex
->stencil_dirty_level_mask
;
296 if (si_can_sample_zs(tex
, true))
297 inplace_planes
|= PIPE_MASK_S
;
299 copy_planes
|= PIPE_MASK_S
;
303 if (unlikely(sctx
->log
))
304 u_log_printf(sctx
->log
,
305 "\n------------------------------------------------\n"
306 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
307 first_level
, last_level
, levels_z
, levels_s
);
309 /* We may have to allocate the flushed texture here when called from
310 * si_decompress_subresource.
313 (tex
->flushed_depth_texture
|| si_init_flushed_depth_texture(&sctx
->b
, &tex
->buffer
.b
.b
))) {
314 struct si_texture
*dst
= tex
->flushed_depth_texture
;
315 unsigned fully_copied_levels
;
318 assert(tex
->flushed_depth_texture
);
320 if (util_format_is_depth_and_stencil(dst
->buffer
.b
.b
.format
))
321 copy_planes
= PIPE_MASK_Z
| PIPE_MASK_S
;
323 if (copy_planes
& PIPE_MASK_Z
) {
327 if (copy_planes
& PIPE_MASK_S
) {
332 fully_copied_levels
= si_blit_dbcb_copy(sctx
, tex
, dst
, copy_planes
, levels
, first_layer
,
333 last_layer
, 0, u_max_sample(&tex
->buffer
.b
.b
));
335 if (copy_planes
& PIPE_MASK_Z
)
336 tex
->dirty_level_mask
&= ~fully_copied_levels
;
337 if (copy_planes
& PIPE_MASK_S
)
338 tex
->stencil_dirty_level_mask
&= ~fully_copied_levels
;
341 if (inplace_planes
) {
342 bool has_htile
= si_htile_enabled(tex
, first_level
, inplace_planes
);
343 bool tc_compat_htile
= vi_tc_compat_htile_enabled(tex
, first_level
, inplace_planes
);
345 /* Don't decompress if there is no HTILE or when HTILE is
347 if (has_htile
&& !tc_compat_htile
) {
348 si_blit_decompress_zs_in_place(sctx
, tex
, levels_z
, levels_s
, first_layer
, last_layer
);
350 /* This is only a cache flush.
352 * Only clear the mask that we are flushing, because
353 * si_make_DB_shader_coherent() treats different levels
354 * and depth and stencil differently.
356 if (inplace_planes
& PIPE_MASK_Z
)
357 tex
->dirty_level_mask
&= ~levels_z
;
358 if (inplace_planes
& PIPE_MASK_S
)
359 tex
->stencil_dirty_level_mask
&= ~levels_s
;
362 /* We just had to completely decompress Z/S for texturing. Enable
363 * TC-compatible HTILE on the next clear, so that the decompression
364 * doesn't have to be done for this texture ever again.
366 * TC-compatible HTILE might slightly reduce Z/S performance, but
367 * the decompression is much worse.
369 if (has_htile
&& !tc_compat_htile
&&
370 tex
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
)
371 tex
->enable_tc_compatible_htile_next_clear
= true;
373 /* Only in-place decompression needs to flush DB caches, or
374 * when we don't decompress but TC-compatible planes are dirty.
376 si_make_DB_shader_coherent(sctx
, tex
->buffer
.b
.b
.nr_samples
, inplace_planes
& PIPE_MASK_S
,
379 /* set_framebuffer_state takes care of coherency for single-sample.
380 * The DB->CB copy uses CB for the final writes.
382 if (copy_planes
&& tex
->buffer
.b
.b
.nr_samples
> 1)
383 si_make_CB_shader_coherent(sctx
, tex
->buffer
.b
.b
.nr_samples
, false, true /* no DCC */);
386 static void si_decompress_sampler_depth_textures(struct si_context
*sctx
,
387 struct si_samplers
*textures
)
390 unsigned mask
= textures
->needs_depth_decompress_mask
;
393 struct pipe_sampler_view
*view
;
394 struct si_sampler_view
*sview
;
395 struct si_texture
*tex
;
397 i
= u_bit_scan(&mask
);
399 view
= textures
->views
[i
];
401 sview
= (struct si_sampler_view
*)view
;
403 tex
= (struct si_texture
*)view
->texture
;
404 assert(tex
->db_compatible
);
406 si_decompress_depth(sctx
, tex
, sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
407 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
, 0,
408 util_max_layer(&tex
->buffer
.b
.b
, view
->u
.tex
.first_level
));
412 static void si_blit_decompress_color(struct si_context
*sctx
, struct si_texture
*tex
,
413 unsigned first_level
, unsigned last_level
,
414 unsigned first_layer
, unsigned last_layer
,
415 bool need_dcc_decompress
, bool need_fmask_expand
)
418 unsigned layer
, checked_last_layer
, max_layer
;
419 unsigned level_mask
= u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
421 if (!need_dcc_decompress
)
422 level_mask
&= tex
->dirty_level_mask
;
426 if (unlikely(sctx
->log
))
427 u_log_printf(sctx
->log
,
428 "\n------------------------------------------------\n"
429 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
430 first_level
, last_level
, level_mask
);
432 if (need_dcc_decompress
) {
433 assert(sctx
->chip_class
== GFX8
);
434 custom_blend
= sctx
->custom_blend_dcc_decompress
;
436 assert(tex
->surface
.dcc_offset
);
438 /* disable levels without DCC */
439 for (int i
= first_level
; i
<= last_level
; i
++) {
440 if (!vi_dcc_enabled(tex
, i
))
441 level_mask
&= ~(1 << i
);
443 } else if (tex
->surface
.fmask_size
) {
444 custom_blend
= sctx
->custom_blend_fmask_decompress
;
446 custom_blend
= sctx
->custom_blend_eliminate_fastclear
;
449 sctx
->decompression_enabled
= true;
452 unsigned level
= u_bit_scan(&level_mask
);
454 /* The smaller the mipmap level, the less layers there are
455 * as far as 3D textures are concerned. */
456 max_layer
= util_max_layer(&tex
->buffer
.b
.b
, level
);
457 checked_last_layer
= MIN2(last_layer
, max_layer
);
459 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
460 struct pipe_surface
*cbsurf
, surf_tmpl
;
462 surf_tmpl
.format
= tex
->buffer
.b
.b
.format
;
463 surf_tmpl
.u
.tex
.level
= level
;
464 surf_tmpl
.u
.tex
.first_layer
= layer
;
465 surf_tmpl
.u
.tex
.last_layer
= layer
;
466 cbsurf
= sctx
->b
.create_surface(&sctx
->b
, &tex
->buffer
.b
.b
, &surf_tmpl
);
468 /* Required before and after FMASK and DCC_DECOMPRESS. */
469 if (custom_blend
== sctx
->custom_blend_fmask_decompress
||
470 custom_blend
== sctx
->custom_blend_dcc_decompress
)
471 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
473 si_blitter_begin(sctx
, SI_DECOMPRESS
);
474 util_blitter_custom_color(sctx
->blitter
, cbsurf
, custom_blend
);
475 si_blitter_end(sctx
);
477 if (custom_blend
== sctx
->custom_blend_fmask_decompress
||
478 custom_blend
== sctx
->custom_blend_dcc_decompress
)
479 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
481 pipe_surface_reference(&cbsurf
, NULL
);
484 /* The texture will always be dirty if some layers aren't flushed.
485 * I don't think this case occurs often though. */
486 if (first_layer
== 0 && last_layer
>= max_layer
) {
487 tex
->dirty_level_mask
&= ~(1 << level
);
491 sctx
->decompression_enabled
= false;
492 si_make_CB_shader_coherent(sctx
, tex
->buffer
.b
.b
.nr_samples
, vi_dcc_enabled(tex
, first_level
),
493 tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
496 if (need_fmask_expand
&& tex
->surface
.fmask_offset
&& !tex
->fmask_is_identity
) {
497 si_compute_expand_fmask(&sctx
->b
, &tex
->buffer
.b
.b
);
498 tex
->fmask_is_identity
= true;
502 static void si_decompress_color_texture(struct si_context
*sctx
, struct si_texture
*tex
,
503 unsigned first_level
, unsigned last_level
,
504 bool need_fmask_expand
)
506 /* CMASK or DCC can be discarded and we can still end up here. */
507 if (!tex
->cmask_buffer
&& !tex
->surface
.fmask_size
&& !tex
->surface
.dcc_offset
)
510 si_blit_decompress_color(sctx
, tex
, first_level
, last_level
, 0,
511 util_max_layer(&tex
->buffer
.b
.b
, first_level
), false,
515 static void si_decompress_sampler_color_textures(struct si_context
*sctx
,
516 struct si_samplers
*textures
)
519 unsigned mask
= textures
->needs_color_decompress_mask
;
522 struct pipe_sampler_view
*view
;
523 struct si_texture
*tex
;
525 i
= u_bit_scan(&mask
);
527 view
= textures
->views
[i
];
530 tex
= (struct si_texture
*)view
->texture
;
532 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
537 static void si_decompress_image_color_textures(struct si_context
*sctx
, struct si_images
*images
)
540 unsigned mask
= images
->needs_color_decompress_mask
;
543 const struct pipe_image_view
*view
;
544 struct si_texture
*tex
;
546 i
= u_bit_scan(&mask
);
548 view
= &images
->views
[i
];
549 assert(view
->resource
->target
!= PIPE_BUFFER
);
551 tex
= (struct si_texture
*)view
->resource
;
553 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
, view
->u
.tex
.level
,
554 view
->access
& PIPE_IMAGE_ACCESS_WRITE
);
558 static void si_check_render_feedback_texture(struct si_context
*sctx
, struct si_texture
*tex
,
559 unsigned first_level
, unsigned last_level
,
560 unsigned first_layer
, unsigned last_layer
)
562 bool render_feedback
= false;
564 if (!tex
->surface
.dcc_offset
)
567 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
568 struct si_surface
*surf
;
570 if (!sctx
->framebuffer
.state
.cbufs
[j
])
573 surf
= (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
575 if (tex
== (struct si_texture
*)surf
->base
.texture
&& surf
->base
.u
.tex
.level
>= first_level
&&
576 surf
->base
.u
.tex
.level
<= last_level
&& surf
->base
.u
.tex
.first_layer
<= last_layer
&&
577 surf
->base
.u
.tex
.last_layer
>= first_layer
) {
578 render_feedback
= true;
584 si_texture_disable_dcc(sctx
, tex
);
587 static void si_check_render_feedback_textures(struct si_context
*sctx
, struct si_samplers
*textures
)
589 uint32_t mask
= textures
->enabled_mask
;
592 const struct pipe_sampler_view
*view
;
593 struct si_texture
*tex
;
595 unsigned i
= u_bit_scan(&mask
);
597 view
= textures
->views
[i
];
598 if (view
->texture
->target
== PIPE_BUFFER
)
601 tex
= (struct si_texture
*)view
->texture
;
603 si_check_render_feedback_texture(sctx
, tex
, view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
604 view
->u
.tex
.first_layer
, view
->u
.tex
.last_layer
);
608 static void si_check_render_feedback_images(struct si_context
*sctx
, struct si_images
*images
)
610 uint32_t mask
= images
->enabled_mask
;
613 const struct pipe_image_view
*view
;
614 struct si_texture
*tex
;
616 unsigned i
= u_bit_scan(&mask
);
618 view
= &images
->views
[i
];
619 if (view
->resource
->target
== PIPE_BUFFER
)
622 tex
= (struct si_texture
*)view
->resource
;
624 si_check_render_feedback_texture(sctx
, tex
, view
->u
.tex
.level
, view
->u
.tex
.level
,
625 view
->u
.tex
.first_layer
, view
->u
.tex
.last_layer
);
629 static void si_check_render_feedback_resident_textures(struct si_context
*sctx
)
631 util_dynarray_foreach (&sctx
->resident_tex_handles
, struct si_texture_handle
*, tex_handle
) {
632 struct pipe_sampler_view
*view
;
633 struct si_texture
*tex
;
635 view
= (*tex_handle
)->view
;
636 if (view
->texture
->target
== PIPE_BUFFER
)
639 tex
= (struct si_texture
*)view
->texture
;
641 si_check_render_feedback_texture(sctx
, tex
, view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
642 view
->u
.tex
.first_layer
, view
->u
.tex
.last_layer
);
646 static void si_check_render_feedback_resident_images(struct si_context
*sctx
)
648 util_dynarray_foreach (&sctx
->resident_img_handles
, struct si_image_handle
*, img_handle
) {
649 struct pipe_image_view
*view
;
650 struct si_texture
*tex
;
652 view
= &(*img_handle
)->view
;
653 if (view
->resource
->target
== PIPE_BUFFER
)
656 tex
= (struct si_texture
*)view
->resource
;
658 si_check_render_feedback_texture(sctx
, tex
, view
->u
.tex
.level
, view
->u
.tex
.level
,
659 view
->u
.tex
.first_layer
, view
->u
.tex
.last_layer
);
663 static void si_check_render_feedback(struct si_context
*sctx
)
665 if (!sctx
->need_check_render_feedback
)
668 /* There is no render feedback if color writes are disabled.
669 * (e.g. a pixel shader with image stores)
671 if (!si_get_total_colormask(sctx
))
674 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
675 si_check_render_feedback_images(sctx
, &sctx
->images
[i
]);
676 si_check_render_feedback_textures(sctx
, &sctx
->samplers
[i
]);
679 si_check_render_feedback_resident_images(sctx
);
680 si_check_render_feedback_resident_textures(sctx
);
682 sctx
->need_check_render_feedback
= false;
685 static void si_decompress_resident_textures(struct si_context
*sctx
)
687 util_dynarray_foreach (&sctx
->resident_tex_needs_color_decompress
, struct si_texture_handle
*,
689 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
690 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
692 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
696 util_dynarray_foreach (&sctx
->resident_tex_needs_depth_decompress
, struct si_texture_handle
*,
698 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
699 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
700 struct si_texture
*tex
= (struct si_texture
*)view
->texture
;
702 si_decompress_depth(sctx
, tex
, sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
703 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
, 0,
704 util_max_layer(&tex
->buffer
.b
.b
, view
->u
.tex
.first_level
));
708 static void si_decompress_resident_images(struct si_context
*sctx
)
710 util_dynarray_foreach (&sctx
->resident_img_needs_color_decompress
, struct si_image_handle
*,
712 struct pipe_image_view
*view
= &(*img_handle
)->view
;
713 struct si_texture
*tex
= (struct si_texture
*)view
->resource
;
715 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
, view
->u
.tex
.level
,
716 view
->access
& PIPE_IMAGE_ACCESS_WRITE
);
720 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
)
722 unsigned compressed_colortex_counter
, mask
;
724 if (sctx
->blitter
->running
)
727 /* Update the compressed_colortex_mask if necessary. */
728 compressed_colortex_counter
= p_atomic_read(&sctx
->screen
->compressed_colortex_counter
);
729 if (compressed_colortex_counter
!= sctx
->last_compressed_colortex_counter
) {
730 sctx
->last_compressed_colortex_counter
= compressed_colortex_counter
;
731 si_update_needs_color_decompress_masks(sctx
);
734 /* Decompress color & depth textures if needed. */
735 mask
= sctx
->shader_needs_decompress_mask
& shader_mask
;
737 unsigned i
= u_bit_scan(&mask
);
739 if (sctx
->samplers
[i
].needs_depth_decompress_mask
) {
740 si_decompress_sampler_depth_textures(sctx
, &sctx
->samplers
[i
]);
742 if (sctx
->samplers
[i
].needs_color_decompress_mask
) {
743 si_decompress_sampler_color_textures(sctx
, &sctx
->samplers
[i
]);
745 if (sctx
->images
[i
].needs_color_decompress_mask
) {
746 si_decompress_image_color_textures(sctx
, &sctx
->images
[i
]);
750 if (shader_mask
& u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
)) {
751 if (sctx
->uses_bindless_samplers
)
752 si_decompress_resident_textures(sctx
);
753 if (sctx
->uses_bindless_images
)
754 si_decompress_resident_images(sctx
);
756 if (sctx
->ps_uses_fbfetch
) {
757 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
758 si_decompress_color_texture(sctx
, (struct si_texture
*)cb0
->texture
,
759 cb0
->u
.tex
.first_layer
, cb0
->u
.tex
.last_layer
, false);
762 si_check_render_feedback(sctx
);
763 } else if (shader_mask
& (1 << PIPE_SHADER_COMPUTE
)) {
764 if (sctx
->cs_shader_state
.program
->sel
.info
.uses_bindless_samplers
)
765 si_decompress_resident_textures(sctx
);
766 if (sctx
->cs_shader_state
.program
->sel
.info
.uses_bindless_images
)
767 si_decompress_resident_images(sctx
);
771 /* Helper for decompressing a portion of a color or depth resource before
772 * blitting if any decompression is needed.
773 * The driver doesn't decompress resources automatically while u_blitter is
775 void si_decompress_subresource(struct pipe_context
*ctx
, struct pipe_resource
*tex
, unsigned planes
,
776 unsigned level
, unsigned first_layer
, unsigned last_layer
)
778 struct si_context
*sctx
= (struct si_context
*)ctx
;
779 struct si_texture
*stex
= (struct si_texture
*)tex
;
781 if (stex
->db_compatible
) {
782 planes
&= PIPE_MASK_Z
| PIPE_MASK_S
;
784 if (!stex
->surface
.has_stencil
)
785 planes
&= ~PIPE_MASK_S
;
787 /* If we've rendered into the framebuffer and it's a blitting
788 * source, make sure the decompression pass is invoked
789 * by dirtying the framebuffer.
791 if (sctx
->framebuffer
.state
.zsbuf
&& sctx
->framebuffer
.state
.zsbuf
->u
.tex
.level
== level
&&
792 sctx
->framebuffer
.state
.zsbuf
->texture
== tex
)
793 si_update_fb_dirtiness_after_rendering(sctx
);
795 si_decompress_depth(sctx
, stex
, planes
, level
, level
, first_layer
, last_layer
);
796 } else if (stex
->surface
.fmask_size
|| stex
->cmask_buffer
|| stex
->surface
.dcc_offset
) {
797 /* If we've rendered into the framebuffer and it's a blitting
798 * source, make sure the decompression pass is invoked
799 * by dirtying the framebuffer.
801 for (unsigned i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
802 if (sctx
->framebuffer
.state
.cbufs
[i
] &&
803 sctx
->framebuffer
.state
.cbufs
[i
]->u
.tex
.level
== level
&&
804 sctx
->framebuffer
.state
.cbufs
[i
]->texture
== tex
) {
805 si_update_fb_dirtiness_after_rendering(sctx
);
810 si_blit_decompress_color(sctx
, stex
, level
, level
, first_layer
, last_layer
, false, false);
814 struct texture_orig_info
{
824 void si_resource_copy_region(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
825 unsigned dst_level
, unsigned dstx
, unsigned dsty
, unsigned dstz
,
826 struct pipe_resource
*src
, unsigned src_level
,
827 const struct pipe_box
*src_box
)
829 struct si_context
*sctx
= (struct si_context
*)ctx
;
830 struct si_texture
*ssrc
= (struct si_texture
*)src
;
831 struct si_texture
*sdst
= (struct si_texture
*)dst
;
832 struct pipe_surface
*dst_view
, dst_templ
;
833 struct pipe_sampler_view src_templ
, *src_view
;
834 unsigned dst_width
, dst_height
, src_width0
, src_height0
;
835 unsigned dst_width0
, dst_height0
, src_force_level
= 0;
836 struct pipe_box sbox
, dstbox
;
838 /* Handle buffers first. */
839 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
840 si_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
);
844 if (!util_format_is_compressed(src
->format
) && !util_format_is_compressed(dst
->format
) &&
845 !util_format_is_depth_or_stencil(src
->format
) && src
->nr_samples
<= 1 &&
846 !sdst
->surface
.dcc_offset
&&
847 !(dst
->target
!= src
->target
&&
848 (src
->target
== PIPE_TEXTURE_1D_ARRAY
|| dst
->target
== PIPE_TEXTURE_1D_ARRAY
))) {
849 si_compute_copy_image(sctx
, dst
, dst_level
, src
, src_level
, dstx
, dsty
, dstz
,
854 assert(u_max_sample(dst
) == u_max_sample(src
));
856 /* The driver doesn't decompress resources automatically while
857 * u_blitter is rendering. */
858 si_decompress_subresource(ctx
, src
, PIPE_MASK_RGBAZS
, src_level
, src_box
->z
,
859 src_box
->z
+ src_box
->depth
- 1);
861 dst_width
= u_minify(dst
->width0
, dst_level
);
862 dst_height
= u_minify(dst
->height0
, dst_level
);
863 dst_width0
= dst
->width0
;
864 dst_height0
= dst
->height0
;
865 src_width0
= src
->width0
;
866 src_height0
= src
->height0
;
868 util_blitter_default_dst_texture(&dst_templ
, dst
, dst_level
, dstz
);
869 util_blitter_default_src_texture(sctx
->blitter
, &src_templ
, src
, src_level
);
871 if (util_format_is_compressed(src
->format
) || util_format_is_compressed(dst
->format
)) {
872 unsigned blocksize
= ssrc
->surface
.bpe
;
875 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; /* 64-bit block */
877 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; /* 128-bit block */
878 dst_templ
.format
= src_templ
.format
;
880 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
881 dst_height
= util_format_get_nblocksy(dst
->format
, dst_height
);
882 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
883 dst_height0
= util_format_get_nblocksy(dst
->format
, dst_height0
);
884 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
885 src_height0
= util_format_get_nblocksy(src
->format
, src_height0
);
887 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
888 dsty
= util_format_get_nblocksy(dst
->format
, dsty
);
890 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
891 sbox
.y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
893 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
894 sbox
.height
= util_format_get_nblocksy(src
->format
, src_box
->height
);
895 sbox
.depth
= src_box
->depth
;
898 src_force_level
= src_level
;
899 } else if (!util_blitter_is_copy_supported(sctx
->blitter
, dst
, src
)) {
900 if (util_format_is_subsampled_422(src
->format
)) {
901 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
902 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
904 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
905 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
906 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
908 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
911 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
912 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
915 unsigned blocksize
= ssrc
->surface
.bpe
;
919 dst_templ
.format
= PIPE_FORMAT_R8_UNORM
;
920 src_templ
.format
= PIPE_FORMAT_R8_UNORM
;
923 dst_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
924 src_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
927 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
928 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
931 dst_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
932 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
935 dst_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
936 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
939 fprintf(stderr
, "Unhandled format %s with blocksize %u\n",
940 util_format_short_name(src
->format
), blocksize
);
946 /* SNORM8 blitting has precision issues on some chips. Use the SINT
947 * equivalent instead, which doesn't force DCC decompression.
948 * Note that some chips avoid this issue by using SDMA.
950 if (util_format_is_snorm8(dst_templ
.format
)) {
951 dst_templ
.format
= src_templ
.format
= util_format_snorm8_to_sint8(dst_templ
.format
);
954 vi_disable_dcc_if_incompatible_format(sctx
, dst
, dst_level
, dst_templ
.format
);
955 vi_disable_dcc_if_incompatible_format(sctx
, src
, src_level
, src_templ
.format
);
957 /* Initialize the surface. */
958 dst_view
= si_create_surface_custom(ctx
, dst
, &dst_templ
, dst_width0
, dst_height0
, dst_width
,
961 /* Initialize the sampler view. */
963 si_create_sampler_view_custom(ctx
, src
, &src_templ
, src_width0
, src_height0
, src_force_level
);
965 u_box_3d(dstx
, dsty
, dstz
, abs(src_box
->width
), abs(src_box
->height
), abs(src_box
->depth
),
969 si_blitter_begin(sctx
, SI_COPY
);
970 util_blitter_blit_generic(sctx
->blitter
, dst_view
, &dstbox
, src_view
, src_box
, src_width0
,
971 src_height0
, PIPE_MASK_RGBAZS
, PIPE_TEX_FILTER_NEAREST
, NULL
, false);
972 si_blitter_end(sctx
);
974 pipe_surface_reference(&dst_view
, NULL
);
975 pipe_sampler_view_reference(&src_view
, NULL
);
978 static void si_do_CB_resolve(struct si_context
*sctx
, const struct pipe_blit_info
*info
,
979 struct pipe_resource
*dst
, unsigned dst_level
, unsigned dst_z
,
980 enum pipe_format format
)
982 /* Required before and after CB_RESOLVE. */
983 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
986 sctx
, SI_COLOR_RESOLVE
| (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
987 util_blitter_custom_resolve_color(sctx
->blitter
, dst
, dst_level
, dst_z
, info
->src
.resource
,
988 info
->src
.box
.z
, ~0, sctx
->custom_blend_resolve
, format
);
989 si_blitter_end(sctx
);
991 /* Flush caches for possible texturing. */
992 si_make_CB_shader_coherent(sctx
, 1, false, true /* no DCC */);
995 static bool do_hardware_msaa_resolve(struct pipe_context
*ctx
, const struct pipe_blit_info
*info
)
997 struct si_context
*sctx
= (struct si_context
*)ctx
;
998 struct si_texture
*src
= (struct si_texture
*)info
->src
.resource
;
999 struct si_texture
*dst
= (struct si_texture
*)info
->dst
.resource
;
1000 ASSERTED
struct si_texture
*stmp
;
1001 unsigned dst_width
= u_minify(info
->dst
.resource
->width0
, info
->dst
.level
);
1002 unsigned dst_height
= u_minify(info
->dst
.resource
->height0
, info
->dst
.level
);
1003 enum pipe_format format
= info
->src
.format
;
1004 struct pipe_resource
*tmp
, templ
;
1005 struct pipe_blit_info blit
;
1007 /* Check basic requirements for hw resolve. */
1008 if (!(info
->src
.resource
->nr_samples
> 1 && info
->dst
.resource
->nr_samples
<= 1 &&
1009 !util_format_is_pure_integer(format
) && !util_format_is_depth_or_stencil(format
) &&
1010 util_max_layer(info
->src
.resource
, 0) == 0))
1013 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1014 * the format is R16G16. Use R16A16, which does work.
1016 if (format
== PIPE_FORMAT_R16G16_UNORM
)
1017 format
= PIPE_FORMAT_R16A16_UNORM
;
1018 if (format
== PIPE_FORMAT_R16G16_SNORM
)
1019 format
= PIPE_FORMAT_R16A16_SNORM
;
1021 /* Check the remaining requirements for hw resolve. */
1022 if (util_max_layer(info
->dst
.resource
, info
->dst
.level
) == 0 && !info
->scissor_enable
&&
1023 (info
->mask
& PIPE_MASK_RGBA
) == PIPE_MASK_RGBA
&&
1024 util_is_format_compatible(util_format_description(info
->src
.format
),
1025 util_format_description(info
->dst
.format
)) &&
1026 dst_width
== info
->src
.resource
->width0
&& dst_height
== info
->src
.resource
->height0
&&
1027 info
->dst
.box
.x
== 0 && info
->dst
.box
.y
== 0 && info
->dst
.box
.width
== dst_width
&&
1028 info
->dst
.box
.height
== dst_height
&& info
->dst
.box
.depth
== 1 && info
->src
.box
.x
== 0 &&
1029 info
->src
.box
.y
== 0 && info
->src
.box
.width
== dst_width
&&
1030 info
->src
.box
.height
== dst_height
&& info
->src
.box
.depth
== 1 && !dst
->surface
.is_linear
&&
1031 (!dst
->cmask_buffer
|| !dst
->dirty_level_mask
)) { /* dst cannot be fast-cleared */
1032 /* Check the last constraint. */
1033 if (src
->surface
.micro_tile_mode
!= dst
->surface
.micro_tile_mode
) {
1034 /* The next fast clear will switch to this mode to
1035 * get direct hw resolve next time if the mode is
1038 * TODO-GFX10: This does not work in GFX10 because MSAA
1039 * is restricted to 64KB_R_X and 64KB_Z_X swizzle modes.
1040 * In some cases we could change the swizzle of the
1041 * destination texture instead, but the more general
1042 * solution is to implement compute shader resolve.
1044 src
->last_msaa_resolve_target_micro_mode
= dst
->surface
.micro_tile_mode
;
1045 goto resolve_to_temp
;
1048 /* Resolving into a surface with DCC is unsupported. Since
1049 * it's being overwritten anyway, clear it to uncompressed.
1050 * This is still the fastest codepath even with this clear.
1052 if (vi_dcc_enabled(dst
, info
->dst
.level
)) {
1053 if (!vi_dcc_clear_level(sctx
, dst
, info
->dst
.level
, DCC_UNCOMPRESSED
))
1054 goto resolve_to_temp
;
1056 dst
->dirty_level_mask
&= ~(1 << info
->dst
.level
);
1059 /* Resolve directly from src to dst. */
1060 si_do_CB_resolve(sctx
, info
, info
->dst
.resource
, info
->dst
.level
, info
->dst
.box
.z
, format
);
1065 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1066 * a temporary texture and blit.
1068 memset(&templ
, 0, sizeof(templ
));
1069 templ
.target
= PIPE_TEXTURE_2D
;
1070 templ
.format
= info
->src
.resource
->format
;
1071 templ
.width0
= info
->src
.resource
->width0
;
1072 templ
.height0
= info
->src
.resource
->height0
;
1074 templ
.array_size
= 1;
1075 templ
.usage
= PIPE_USAGE_DEFAULT
;
1076 templ
.flags
= SI_RESOURCE_FLAG_FORCE_MSAA_TILING
| SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE
|
1077 SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(src
->surface
.micro_tile_mode
) |
1078 SI_RESOURCE_FLAG_DISABLE_DCC
;
1080 /* The src and dst microtile modes must be the same. */
1081 if (sctx
->chip_class
<= GFX8
&& src
->surface
.micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
)
1082 templ
.bind
= PIPE_BIND_SCANOUT
;
1086 tmp
= ctx
->screen
->resource_create(ctx
->screen
, &templ
);
1089 stmp
= (struct si_texture
*)tmp
;
1091 assert(!stmp
->surface
.is_linear
);
1092 assert(src
->surface
.micro_tile_mode
== stmp
->surface
.micro_tile_mode
);
1095 si_do_CB_resolve(sctx
, info
, tmp
, 0, 0, format
);
1099 blit
.src
.resource
= tmp
;
1102 si_blitter_begin(sctx
, SI_BLIT
| (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1103 util_blitter_blit(sctx
->blitter
, &blit
);
1104 si_blitter_end(sctx
);
1106 pipe_resource_reference(&tmp
, NULL
);
1110 static void si_blit(struct pipe_context
*ctx
, const struct pipe_blit_info
*info
)
1112 struct si_context
*sctx
= (struct si_context
*)ctx
;
1113 struct si_texture
*dst
= (struct si_texture
*)info
->dst
.resource
;
1115 if (do_hardware_msaa_resolve(ctx
, info
)) {
1119 /* Using SDMA for copying to a linear texture in GTT is much faster.
1120 * This improves DRI PRIME performance.
1122 * resource_copy_region can't do this yet, because dma_copy calls it
1123 * on failure (recursion).
1125 if (dst
->surface
.is_linear
&& util_can_blit_via_copy_region(info
, false)) {
1126 sctx
->dma_copy(ctx
, info
->dst
.resource
, info
->dst
.level
, info
->dst
.box
.x
, info
->dst
.box
.y
,
1127 info
->dst
.box
.z
, info
->src
.resource
, info
->src
.level
, &info
->src
.box
);
1131 assert(util_blitter_is_blit_supported(sctx
->blitter
, info
));
1133 /* The driver doesn't decompress resources automatically while
1134 * u_blitter is rendering. */
1135 vi_disable_dcc_if_incompatible_format(sctx
, info
->src
.resource
, info
->src
.level
,
1137 vi_disable_dcc_if_incompatible_format(sctx
, info
->dst
.resource
, info
->dst
.level
,
1139 si_decompress_subresource(ctx
, info
->src
.resource
, PIPE_MASK_RGBAZS
, info
->src
.level
,
1140 info
->src
.box
.z
, info
->src
.box
.z
+ info
->src
.box
.depth
- 1);
1142 if (sctx
->screen
->debug_flags
& DBG(FORCE_SDMA
) && util_try_blit_via_copy_region(ctx
, info
))
1145 si_blitter_begin(sctx
, SI_BLIT
| (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1146 util_blitter_blit(sctx
->blitter
, info
);
1147 si_blitter_end(sctx
);
1150 static bool si_generate_mipmap(struct pipe_context
*ctx
, struct pipe_resource
*tex
,
1151 enum pipe_format format
, unsigned base_level
, unsigned last_level
,
1152 unsigned first_layer
, unsigned last_layer
)
1154 struct si_context
*sctx
= (struct si_context
*)ctx
;
1155 struct si_texture
*stex
= (struct si_texture
*)tex
;
1157 if (!util_blitter_is_copy_supported(sctx
->blitter
, tex
, tex
))
1160 /* The driver doesn't decompress resources automatically while
1161 * u_blitter is rendering. */
1162 vi_disable_dcc_if_incompatible_format(sctx
, tex
, base_level
, format
);
1163 si_decompress_subresource(ctx
, tex
, PIPE_MASK_RGBAZS
, base_level
, first_layer
, last_layer
);
1165 /* Clear dirty_level_mask for the levels that will be overwritten. */
1166 assert(base_level
< last_level
);
1167 stex
->dirty_level_mask
&= ~u_bit_consecutive(base_level
+ 1, last_level
- base_level
);
1169 sctx
->generate_mipmap_for_depth
= stex
->is_depth
;
1171 si_blitter_begin(sctx
, SI_BLIT
| SI_DISABLE_RENDER_COND
);
1172 util_blitter_generate_mipmap(sctx
->blitter
, tex
, format
, base_level
, last_level
, first_layer
,
1174 si_blitter_end(sctx
);
1176 sctx
->generate_mipmap_for_depth
= false;
1180 static void si_flush_resource(struct pipe_context
*ctx
, struct pipe_resource
*res
)
1182 struct si_context
*sctx
= (struct si_context
*)ctx
;
1183 struct si_texture
*tex
= (struct si_texture
*)res
;
1185 assert(res
->target
!= PIPE_BUFFER
);
1186 assert(!tex
->dcc_separate_buffer
|| tex
->dcc_gather_statistics
);
1188 /* st/dri calls flush twice per frame (not a bug), this prevents double
1190 if (tex
->dcc_separate_buffer
&& !tex
->separate_dcc_dirty
)
1193 if (!tex
->is_depth
&& (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
)) {
1194 si_blit_decompress_color(sctx
, tex
, 0, res
->last_level
, 0, util_max_layer(res
, 0),
1195 tex
->dcc_separate_buffer
!= NULL
, false);
1197 if (tex
->surface
.display_dcc_offset
&& tex
->displayable_dcc_dirty
) {
1198 si_retile_dcc(sctx
, tex
);
1199 tex
->displayable_dcc_dirty
= false;
1203 /* Always do the analysis even if DCC is disabled at the moment. */
1204 if (tex
->dcc_gather_statistics
) {
1205 bool separate_dcc_dirty
= tex
->separate_dcc_dirty
;
1207 /* If the color buffer hasn't been unbound and fast clear hasn't
1208 * been used, separate_dcc_dirty is false, but there may have been
1209 * new rendering. Check if the color buffer is bound and assume
1212 * Note that DRI2 never unbinds window colorbuffers, which means
1213 * the DCC pipeline statistics query would never be re-set and would
1214 * keep adding new results until all free memory is exhausted if we
1217 if (!separate_dcc_dirty
) {
1218 for (unsigned i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
1219 if (sctx
->framebuffer
.state
.cbufs
[i
] &&
1220 sctx
->framebuffer
.state
.cbufs
[i
]->texture
== res
) {
1221 separate_dcc_dirty
= true;
1227 if (separate_dcc_dirty
) {
1228 tex
->separate_dcc_dirty
= false;
1229 vi_separate_dcc_process_and_reset_stats(ctx
, tex
);
1234 void si_decompress_dcc(struct si_context
*sctx
, struct si_texture
*tex
)
1236 /* If graphics is disabled, we can't decompress DCC, but it shouldn't
1237 * be compressed either. The caller should simply discard it.
1239 if (!tex
->surface
.dcc_offset
|| !sctx
->has_graphics
)
1242 if (sctx
->chip_class
== GFX8
) {
1243 si_blit_decompress_color(sctx
, tex
, 0, tex
->buffer
.b
.b
.last_level
, 0,
1244 util_max_layer(&tex
->buffer
.b
.b
, 0), true, false);
1246 struct pipe_resource
*ptex
= &tex
->buffer
.b
.b
;
1248 /* DCC decompression using a compute shader. */
1249 for (unsigned level
= 0; level
< tex
->surface
.num_dcc_levels
; level
++) {
1250 struct pipe_box box
;
1252 u_box_3d(0, 0, 0, u_minify(ptex
->width0
, level
),
1253 u_minify(ptex
->height0
, level
),
1254 util_num_layers(ptex
, level
), &box
);
1255 si_compute_copy_image(sctx
, ptex
, level
, ptex
, level
, 0, 0, 0, &box
,
1259 /* Now clear DCC metadata to uncompressed. */
1260 uint32_t clear_value
= DCC_UNCOMPRESSED
;
1261 si_clear_buffer(sctx
, ptex
, tex
->surface
.dcc_offset
,
1262 tex
->surface
.dcc_size
, &clear_value
, 4,
1263 SI_COHERENCY_CB_META
, false);
1267 void si_init_blit_functions(struct si_context
*sctx
)
1269 sctx
->b
.resource_copy_region
= si_resource_copy_region
;
1271 if (sctx
->has_graphics
) {
1272 sctx
->b
.blit
= si_blit
;
1273 sctx
->b
.flush_resource
= si_flush_resource
;
1274 sctx
->b
.generate_mipmap
= si_generate_mipmap
;