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radeonsi/gfx10: implement hardware MSAA resolve
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_compute.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
34 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
35
36 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
37 SI_SAVE_FRAGMENT_STATE,
38
39 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
40 SI_DISABLE_RENDER_COND,
41
42 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
43 };
44
45 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op)
46 {
47 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
48 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
49 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
50 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
51 util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets,
52 (struct pipe_stream_output_target**)sctx->streamout.targets);
53 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
54
55 if (op & SI_SAVE_FRAGMENT_STATE) {
56 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
57 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
58 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
59 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
60 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask);
61 util_blitter_save_scissor(sctx->blitter, &sctx->scissors[0]);
62 util_blitter_save_window_rectangles(sctx->blitter,
63 sctx->window_rectangles_include,
64 sctx->num_window_rectangles,
65 sctx->window_rectangles);
66 }
67
68 if (op & SI_SAVE_FRAMEBUFFER)
69 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
70
71 if (op & SI_SAVE_TEXTURES) {
72 util_blitter_save_fragment_sampler_states(
73 sctx->blitter, 2,
74 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
75
76 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
77 sctx->samplers[PIPE_SHADER_FRAGMENT].views);
78 }
79
80 if (op & SI_DISABLE_RENDER_COND)
81 sctx->render_cond_force_off = true;
82
83 if (sctx->screen->dpbb_allowed) {
84 sctx->dpbb_force_off = true;
85 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
86 }
87 }
88
89 void si_blitter_end(struct si_context *sctx)
90 {
91 if (sctx->screen->dpbb_allowed) {
92 sctx->dpbb_force_off = false;
93 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
94 }
95
96 sctx->render_cond_force_off = false;
97
98 /* Restore shader pointers because the VS blit shader changed all
99 * non-global VS user SGPRs. */
100 sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX);
101 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
102 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
103 }
104
105 static unsigned u_max_sample(struct pipe_resource *r)
106 {
107 return r->nr_samples ? r->nr_samples - 1 : 0;
108 }
109
110 static unsigned
111 si_blit_dbcb_copy(struct si_context *sctx,
112 struct si_texture *src,
113 struct si_texture *dst,
114 unsigned planes, unsigned level_mask,
115 unsigned first_layer, unsigned last_layer,
116 unsigned first_sample, unsigned last_sample)
117 {
118 struct pipe_surface surf_tmpl = {{0}};
119 unsigned layer, sample, checked_last_layer, max_layer;
120 unsigned fully_copied_levels = 0;
121
122 if (planes & PIPE_MASK_Z)
123 sctx->dbcb_depth_copy_enabled = true;
124 if (planes & PIPE_MASK_S)
125 sctx->dbcb_stencil_copy_enabled = true;
126 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
127
128 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
129
130 sctx->decompression_enabled = true;
131
132 while (level_mask) {
133 unsigned level = u_bit_scan(&level_mask);
134
135 /* The smaller the mipmap level, the less layers there are
136 * as far as 3D textures are concerned. */
137 max_layer = util_max_layer(&src->buffer.b.b, level);
138 checked_last_layer = MIN2(last_layer, max_layer);
139
140 surf_tmpl.u.tex.level = level;
141
142 for (layer = first_layer; layer <= checked_last_layer; layer++) {
143 struct pipe_surface *zsurf, *cbsurf;
144
145 surf_tmpl.format = src->buffer.b.b.format;
146 surf_tmpl.u.tex.first_layer = layer;
147 surf_tmpl.u.tex.last_layer = layer;
148
149 zsurf = sctx->b.create_surface(&sctx->b, &src->buffer.b.b, &surf_tmpl);
150
151 surf_tmpl.format = dst->buffer.b.b.format;
152 cbsurf = sctx->b.create_surface(&sctx->b, &dst->buffer.b.b, &surf_tmpl);
153
154 for (sample = first_sample; sample <= last_sample; sample++) {
155 if (sample != sctx->dbcb_copy_sample) {
156 sctx->dbcb_copy_sample = sample;
157 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
158 }
159
160 si_blitter_begin(sctx, SI_DECOMPRESS);
161 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
162 sctx->custom_dsa_flush, 1.0f);
163 si_blitter_end(sctx);
164 }
165
166 pipe_surface_reference(&zsurf, NULL);
167 pipe_surface_reference(&cbsurf, NULL);
168 }
169
170 if (first_layer == 0 && last_layer >= max_layer &&
171 first_sample == 0 && last_sample >= u_max_sample(&src->buffer.b.b))
172 fully_copied_levels |= 1u << level;
173 }
174
175 sctx->decompression_enabled = false;
176 sctx->dbcb_depth_copy_enabled = false;
177 sctx->dbcb_stencil_copy_enabled = false;
178 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
179
180 return fully_copied_levels;
181 }
182
183 /* Helper function for si_blit_decompress_zs_in_place.
184 */
185 static void
186 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
187 struct si_texture *texture,
188 unsigned planes, unsigned level_mask,
189 unsigned first_layer, unsigned last_layer)
190 {
191 struct pipe_surface *zsurf, surf_tmpl = {{0}};
192 unsigned layer, max_layer, checked_last_layer;
193 unsigned fully_decompressed_mask = 0;
194
195 if (!level_mask)
196 return;
197
198 if (planes & PIPE_MASK_S)
199 sctx->db_flush_stencil_inplace = true;
200 if (planes & PIPE_MASK_Z)
201 sctx->db_flush_depth_inplace = true;
202 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
203
204 surf_tmpl.format = texture->buffer.b.b.format;
205
206 sctx->decompression_enabled = true;
207
208 while (level_mask) {
209 unsigned level = u_bit_scan(&level_mask);
210
211 surf_tmpl.u.tex.level = level;
212
213 /* The smaller the mipmap level, the less layers there are
214 * as far as 3D textures are concerned. */
215 max_layer = util_max_layer(&texture->buffer.b.b, level);
216 checked_last_layer = MIN2(last_layer, max_layer);
217
218 for (layer = first_layer; layer <= checked_last_layer; layer++) {
219 surf_tmpl.u.tex.first_layer = layer;
220 surf_tmpl.u.tex.last_layer = layer;
221
222 zsurf = sctx->b.create_surface(&sctx->b, &texture->buffer.b.b, &surf_tmpl);
223
224 si_blitter_begin(sctx, SI_DECOMPRESS);
225 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
226 sctx->custom_dsa_flush,
227 1.0f);
228 si_blitter_end(sctx);
229
230 pipe_surface_reference(&zsurf, NULL);
231 }
232
233 /* The texture will always be dirty if some layers aren't flushed.
234 * I don't think this case occurs often though. */
235 if (first_layer == 0 && last_layer >= max_layer) {
236 fully_decompressed_mask |= 1u << level;
237 }
238 }
239
240 if (planes & PIPE_MASK_Z)
241 texture->dirty_level_mask &= ~fully_decompressed_mask;
242 if (planes & PIPE_MASK_S)
243 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
244
245 sctx->decompression_enabled = false;
246 sctx->db_flush_depth_inplace = false;
247 sctx->db_flush_stencil_inplace = false;
248 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
249 }
250
251 /* Helper function of si_flush_depth_texture: decompress the given levels
252 * of Z and/or S planes in place.
253 */
254 static void
255 si_blit_decompress_zs_in_place(struct si_context *sctx,
256 struct si_texture *texture,
257 unsigned levels_z, unsigned levels_s,
258 unsigned first_layer, unsigned last_layer)
259 {
260 unsigned both = levels_z & levels_s;
261
262 /* First, do combined Z & S decompresses for levels that need it. */
263 if (both) {
264 si_blit_decompress_zs_planes_in_place(
265 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
266 both,
267 first_layer, last_layer);
268 levels_z &= ~both;
269 levels_s &= ~both;
270 }
271
272 /* Now do separate Z and S decompresses. */
273 if (levels_z) {
274 si_blit_decompress_zs_planes_in_place(
275 sctx, texture, PIPE_MASK_Z,
276 levels_z,
277 first_layer, last_layer);
278 }
279
280 if (levels_s) {
281 si_blit_decompress_zs_planes_in_place(
282 sctx, texture, PIPE_MASK_S,
283 levels_s,
284 first_layer, last_layer);
285 }
286 }
287
288 static void
289 si_decompress_depth(struct si_context *sctx,
290 struct si_texture *tex,
291 unsigned required_planes,
292 unsigned first_level, unsigned last_level,
293 unsigned first_layer, unsigned last_layer)
294 {
295 unsigned inplace_planes = 0;
296 unsigned copy_planes = 0;
297 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
298 unsigned levels_z = 0;
299 unsigned levels_s = 0;
300
301 if (required_planes & PIPE_MASK_Z) {
302 levels_z = level_mask & tex->dirty_level_mask;
303
304 if (levels_z) {
305 if (si_can_sample_zs(tex, false))
306 inplace_planes |= PIPE_MASK_Z;
307 else
308 copy_planes |= PIPE_MASK_Z;
309 }
310 }
311 if (required_planes & PIPE_MASK_S) {
312 levels_s = level_mask & tex->stencil_dirty_level_mask;
313
314 if (levels_s) {
315 if (si_can_sample_zs(tex, true))
316 inplace_planes |= PIPE_MASK_S;
317 else
318 copy_planes |= PIPE_MASK_S;
319 }
320 }
321
322 if (unlikely(sctx->log))
323 u_log_printf(sctx->log,
324 "\n------------------------------------------------\n"
325 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
326 first_level, last_level, levels_z, levels_s);
327
328 /* We may have to allocate the flushed texture here when called from
329 * si_decompress_subresource.
330 */
331 if (copy_planes &&
332 (tex->flushed_depth_texture ||
333 si_init_flushed_depth_texture(&sctx->b, &tex->buffer.b.b))) {
334 struct si_texture *dst = tex->flushed_depth_texture;
335 unsigned fully_copied_levels;
336 unsigned levels = 0;
337
338 assert(tex->flushed_depth_texture);
339
340 if (util_format_is_depth_and_stencil(dst->buffer.b.b.format))
341 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
342
343 if (copy_planes & PIPE_MASK_Z) {
344 levels |= levels_z;
345 levels_z = 0;
346 }
347 if (copy_planes & PIPE_MASK_S) {
348 levels |= levels_s;
349 levels_s = 0;
350 }
351
352 fully_copied_levels = si_blit_dbcb_copy(
353 sctx, tex, dst, copy_planes, levels,
354 first_layer, last_layer,
355 0, u_max_sample(&tex->buffer.b.b));
356
357 if (copy_planes & PIPE_MASK_Z)
358 tex->dirty_level_mask &= ~fully_copied_levels;
359 if (copy_planes & PIPE_MASK_S)
360 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
361 }
362
363 if (inplace_planes) {
364 bool has_htile = si_htile_enabled(tex, first_level);
365 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
366
367 /* Don't decompress if there is no HTILE or when HTILE is
368 * TC-compatible. */
369 if (has_htile && !tc_compat_htile) {
370 si_blit_decompress_zs_in_place(
371 sctx, tex,
372 levels_z, levels_s,
373 first_layer, last_layer);
374 } else {
375 /* This is only a cache flush.
376 *
377 * Only clear the mask that we are flushing, because
378 * si_make_DB_shader_coherent() treats different levels
379 * and depth and stencil differently.
380 */
381 if (inplace_planes & PIPE_MASK_Z)
382 tex->dirty_level_mask &= ~levels_z;
383 if (inplace_planes & PIPE_MASK_S)
384 tex->stencil_dirty_level_mask &= ~levels_s;
385 }
386
387 /* Only in-place decompression needs to flush DB caches, or
388 * when we don't decompress but TC-compatible planes are dirty.
389 */
390 si_make_DB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
391 inplace_planes & PIPE_MASK_S,
392 tc_compat_htile);
393 }
394 /* set_framebuffer_state takes care of coherency for single-sample.
395 * The DB->CB copy uses CB for the final writes.
396 */
397 if (copy_planes && tex->buffer.b.b.nr_samples > 1)
398 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
399 false, true /* no DCC */);
400 }
401
402 static void
403 si_decompress_sampler_depth_textures(struct si_context *sctx,
404 struct si_samplers *textures)
405 {
406 unsigned i;
407 unsigned mask = textures->needs_depth_decompress_mask;
408
409 while (mask) {
410 struct pipe_sampler_view *view;
411 struct si_sampler_view *sview;
412 struct si_texture *tex;
413
414 i = u_bit_scan(&mask);
415
416 view = textures->views[i];
417 assert(view);
418 sview = (struct si_sampler_view*)view;
419
420 tex = (struct si_texture *)view->texture;
421 assert(tex->db_compatible);
422
423 si_decompress_depth(sctx, tex,
424 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
425 view->u.tex.first_level, view->u.tex.last_level,
426 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
427 }
428 }
429
430 static void si_blit_decompress_color(struct si_context *sctx,
431 struct si_texture *tex,
432 unsigned first_level, unsigned last_level,
433 unsigned first_layer, unsigned last_layer,
434 bool need_dcc_decompress)
435 {
436 void* custom_blend;
437 unsigned layer, checked_last_layer, max_layer;
438 unsigned level_mask =
439 u_bit_consecutive(first_level, last_level - first_level + 1);
440
441 if (!need_dcc_decompress)
442 level_mask &= tex->dirty_level_mask;
443 if (!level_mask)
444 return;
445
446 if (unlikely(sctx->log))
447 u_log_printf(sctx->log,
448 "\n------------------------------------------------\n"
449 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
450 first_level, last_level, level_mask);
451
452 if (need_dcc_decompress) {
453 custom_blend = sctx->custom_blend_dcc_decompress;
454
455 assert(tex->dcc_offset);
456
457 /* disable levels without DCC */
458 for (int i = first_level; i <= last_level; i++) {
459 if (!vi_dcc_enabled(tex, i))
460 level_mask &= ~(1 << i);
461 }
462 } else if (tex->surface.fmask_size) {
463 custom_blend = sctx->custom_blend_fmask_decompress;
464 } else {
465 custom_blend = sctx->custom_blend_eliminate_fastclear;
466 }
467
468 sctx->decompression_enabled = true;
469
470 while (level_mask) {
471 unsigned level = u_bit_scan(&level_mask);
472
473 /* The smaller the mipmap level, the less layers there are
474 * as far as 3D textures are concerned. */
475 max_layer = util_max_layer(&tex->buffer.b.b, level);
476 checked_last_layer = MIN2(last_layer, max_layer);
477
478 for (layer = first_layer; layer <= checked_last_layer; layer++) {
479 struct pipe_surface *cbsurf, surf_tmpl;
480
481 surf_tmpl.format = tex->buffer.b.b.format;
482 surf_tmpl.u.tex.level = level;
483 surf_tmpl.u.tex.first_layer = layer;
484 surf_tmpl.u.tex.last_layer = layer;
485 cbsurf = sctx->b.create_surface(&sctx->b, &tex->buffer.b.b, &surf_tmpl);
486
487 /* Required before and after FMASK and DCC_DECOMPRESS. */
488 if (custom_blend == sctx->custom_blend_fmask_decompress ||
489 custom_blend == sctx->custom_blend_dcc_decompress)
490 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
491
492 si_blitter_begin(sctx, SI_DECOMPRESS);
493 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
494 si_blitter_end(sctx);
495
496 if (custom_blend == sctx->custom_blend_fmask_decompress ||
497 custom_blend == sctx->custom_blend_dcc_decompress)
498 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
499
500 pipe_surface_reference(&cbsurf, NULL);
501 }
502
503 /* The texture will always be dirty if some layers aren't flushed.
504 * I don't think this case occurs often though. */
505 if (first_layer == 0 && last_layer >= max_layer) {
506 tex->dirty_level_mask &= ~(1 << level);
507 }
508 }
509
510 sctx->decompression_enabled = false;
511 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
512 vi_dcc_enabled(tex, first_level),
513 tex->surface.u.gfx9.dcc.pipe_aligned);
514 }
515
516 static void
517 si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex,
518 unsigned first_level, unsigned last_level)
519 {
520 /* CMASK or DCC can be discarded and we can still end up here. */
521 if (!tex->cmask_buffer && !tex->surface.fmask_size && !tex->dcc_offset)
522 return;
523
524 si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
525 util_max_layer(&tex->buffer.b.b, first_level),
526 false);
527 }
528
529 static void
530 si_decompress_sampler_color_textures(struct si_context *sctx,
531 struct si_samplers *textures)
532 {
533 unsigned i;
534 unsigned mask = textures->needs_color_decompress_mask;
535
536 while (mask) {
537 struct pipe_sampler_view *view;
538 struct si_texture *tex;
539
540 i = u_bit_scan(&mask);
541
542 view = textures->views[i];
543 assert(view);
544
545 tex = (struct si_texture *)view->texture;
546
547 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
548 view->u.tex.last_level);
549 }
550 }
551
552 static void
553 si_decompress_image_color_textures(struct si_context *sctx,
554 struct si_images *images)
555 {
556 unsigned i;
557 unsigned mask = images->needs_color_decompress_mask;
558
559 while (mask) {
560 const struct pipe_image_view *view;
561 struct si_texture *tex;
562
563 i = u_bit_scan(&mask);
564
565 view = &images->views[i];
566 assert(view->resource->target != PIPE_BUFFER);
567
568 tex = (struct si_texture *)view->resource;
569
570 si_decompress_color_texture(sctx, tex, view->u.tex.level,
571 view->u.tex.level);
572 }
573 }
574
575 static void si_check_render_feedback_texture(struct si_context *sctx,
576 struct si_texture *tex,
577 unsigned first_level,
578 unsigned last_level,
579 unsigned first_layer,
580 unsigned last_layer)
581 {
582 bool render_feedback = false;
583
584 if (!tex->dcc_offset)
585 return;
586
587 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
588 struct si_surface * surf;
589
590 if (!sctx->framebuffer.state.cbufs[j])
591 continue;
592
593 surf = (struct si_surface*)sctx->framebuffer.state.cbufs[j];
594
595 if (tex == (struct si_texture *)surf->base.texture &&
596 surf->base.u.tex.level >= first_level &&
597 surf->base.u.tex.level <= last_level &&
598 surf->base.u.tex.first_layer <= last_layer &&
599 surf->base.u.tex.last_layer >= first_layer) {
600 render_feedback = true;
601 break;
602 }
603 }
604
605 if (render_feedback)
606 si_texture_disable_dcc(sctx, tex);
607 }
608
609 static void si_check_render_feedback_textures(struct si_context *sctx,
610 struct si_samplers *textures)
611 {
612 uint32_t mask = textures->enabled_mask;
613
614 while (mask) {
615 const struct pipe_sampler_view *view;
616 struct si_texture *tex;
617
618 unsigned i = u_bit_scan(&mask);
619
620 view = textures->views[i];
621 if(view->texture->target == PIPE_BUFFER)
622 continue;
623
624 tex = (struct si_texture *)view->texture;
625
626 si_check_render_feedback_texture(sctx, tex,
627 view->u.tex.first_level,
628 view->u.tex.last_level,
629 view->u.tex.first_layer,
630 view->u.tex.last_layer);
631 }
632 }
633
634 static void si_check_render_feedback_images(struct si_context *sctx,
635 struct si_images *images)
636 {
637 uint32_t mask = images->enabled_mask;
638
639 while (mask) {
640 const struct pipe_image_view *view;
641 struct si_texture *tex;
642
643 unsigned i = u_bit_scan(&mask);
644
645 view = &images->views[i];
646 if (view->resource->target == PIPE_BUFFER)
647 continue;
648
649 tex = (struct si_texture *)view->resource;
650
651 si_check_render_feedback_texture(sctx, tex,
652 view->u.tex.level,
653 view->u.tex.level,
654 view->u.tex.first_layer,
655 view->u.tex.last_layer);
656 }
657 }
658
659 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
660 {
661 util_dynarray_foreach(&sctx->resident_tex_handles,
662 struct si_texture_handle *, tex_handle) {
663 struct pipe_sampler_view *view;
664 struct si_texture *tex;
665
666 view = (*tex_handle)->view;
667 if (view->texture->target == PIPE_BUFFER)
668 continue;
669
670 tex = (struct si_texture *)view->texture;
671
672 si_check_render_feedback_texture(sctx, tex,
673 view->u.tex.first_level,
674 view->u.tex.last_level,
675 view->u.tex.first_layer,
676 view->u.tex.last_layer);
677 }
678 }
679
680 static void si_check_render_feedback_resident_images(struct si_context *sctx)
681 {
682 util_dynarray_foreach(&sctx->resident_img_handles,
683 struct si_image_handle *, img_handle) {
684 struct pipe_image_view *view;
685 struct si_texture *tex;
686
687 view = &(*img_handle)->view;
688 if (view->resource->target == PIPE_BUFFER)
689 continue;
690
691 tex = (struct si_texture *)view->resource;
692
693 si_check_render_feedback_texture(sctx, tex,
694 view->u.tex.level,
695 view->u.tex.level,
696 view->u.tex.first_layer,
697 view->u.tex.last_layer);
698 }
699 }
700
701 static void si_check_render_feedback(struct si_context *sctx)
702 {
703 if (!sctx->need_check_render_feedback)
704 return;
705
706 /* There is no render feedback if color writes are disabled.
707 * (e.g. a pixel shader with image stores)
708 */
709 if (!si_get_total_colormask(sctx))
710 return;
711
712 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
713 si_check_render_feedback_images(sctx, &sctx->images[i]);
714 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
715 }
716
717 si_check_render_feedback_resident_images(sctx);
718 si_check_render_feedback_resident_textures(sctx);
719
720 sctx->need_check_render_feedback = false;
721 }
722
723 static void si_decompress_resident_textures(struct si_context *sctx)
724 {
725 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
726 struct si_texture_handle *, tex_handle) {
727 struct pipe_sampler_view *view = (*tex_handle)->view;
728 struct si_texture *tex = (struct si_texture *)view->texture;
729
730 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
731 view->u.tex.last_level);
732 }
733
734 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
735 struct si_texture_handle *, tex_handle) {
736 struct pipe_sampler_view *view = (*tex_handle)->view;
737 struct si_sampler_view *sview = (struct si_sampler_view *)view;
738 struct si_texture *tex = (struct si_texture *)view->texture;
739
740 si_decompress_depth(sctx, tex,
741 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
742 view->u.tex.first_level, view->u.tex.last_level,
743 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
744 }
745 }
746
747 static void si_decompress_resident_images(struct si_context *sctx)
748 {
749 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
750 struct si_image_handle *, img_handle) {
751 struct pipe_image_view *view = &(*img_handle)->view;
752 struct si_texture *tex = (struct si_texture *)view->resource;
753
754 si_decompress_color_texture(sctx, tex, view->u.tex.level,
755 view->u.tex.level);
756 }
757 }
758
759 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
760 {
761 unsigned compressed_colortex_counter, mask;
762
763 if (sctx->blitter->running)
764 return;
765
766 /* Update the compressed_colortex_mask if necessary. */
767 compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter);
768 if (compressed_colortex_counter != sctx->last_compressed_colortex_counter) {
769 sctx->last_compressed_colortex_counter = compressed_colortex_counter;
770 si_update_needs_color_decompress_masks(sctx);
771 }
772
773 /* Decompress color & depth textures if needed. */
774 mask = sctx->shader_needs_decompress_mask & shader_mask;
775 while (mask) {
776 unsigned i = u_bit_scan(&mask);
777
778 if (sctx->samplers[i].needs_depth_decompress_mask) {
779 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
780 }
781 if (sctx->samplers[i].needs_color_decompress_mask) {
782 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
783 }
784 if (sctx->images[i].needs_color_decompress_mask) {
785 si_decompress_image_color_textures(sctx, &sctx->images[i]);
786 }
787 }
788
789 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
790 if (sctx->uses_bindless_samplers)
791 si_decompress_resident_textures(sctx);
792 if (sctx->uses_bindless_images)
793 si_decompress_resident_images(sctx);
794
795 if (sctx->ps_uses_fbfetch) {
796 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
797 si_decompress_color_texture(sctx,
798 (struct si_texture*)cb0->texture,
799 cb0->u.tex.first_layer,
800 cb0->u.tex.last_layer);
801 }
802
803 si_check_render_feedback(sctx);
804 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
805 if (sctx->cs_shader_state.program->uses_bindless_samplers)
806 si_decompress_resident_textures(sctx);
807 if (sctx->cs_shader_state.program->uses_bindless_images)
808 si_decompress_resident_images(sctx);
809 }
810 }
811
812 /* Helper for decompressing a portion of a color or depth resource before
813 * blitting if any decompression is needed.
814 * The driver doesn't decompress resources automatically while u_blitter is
815 * rendering. */
816 static void si_decompress_subresource(struct pipe_context *ctx,
817 struct pipe_resource *tex,
818 unsigned planes, unsigned level,
819 unsigned first_layer, unsigned last_layer)
820 {
821 struct si_context *sctx = (struct si_context *)ctx;
822 struct si_texture *stex = (struct si_texture*)tex;
823
824 if (stex->db_compatible) {
825 planes &= PIPE_MASK_Z | PIPE_MASK_S;
826
827 if (!stex->surface.has_stencil)
828 planes &= ~PIPE_MASK_S;
829
830 /* If we've rendered into the framebuffer and it's a blitting
831 * source, make sure the decompression pass is invoked
832 * by dirtying the framebuffer.
833 */
834 if (sctx->framebuffer.state.zsbuf &&
835 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
836 sctx->framebuffer.state.zsbuf->texture == tex)
837 si_update_fb_dirtiness_after_rendering(sctx);
838
839 si_decompress_depth(sctx, stex, planes,
840 level, level,
841 first_layer, last_layer);
842 } else if (stex->surface.fmask_size || stex->cmask_buffer || stex->dcc_offset) {
843 /* If we've rendered into the framebuffer and it's a blitting
844 * source, make sure the decompression pass is invoked
845 * by dirtying the framebuffer.
846 */
847 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
848 if (sctx->framebuffer.state.cbufs[i] &&
849 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
850 sctx->framebuffer.state.cbufs[i]->texture == tex) {
851 si_update_fb_dirtiness_after_rendering(sctx);
852 break;
853 }
854 }
855
856 si_blit_decompress_color(sctx, stex, level, level,
857 first_layer, last_layer, false);
858 }
859 }
860
861 struct texture_orig_info {
862 unsigned format;
863 unsigned width0;
864 unsigned height0;
865 unsigned npix_x;
866 unsigned npix_y;
867 unsigned npix0_x;
868 unsigned npix0_y;
869 };
870
871 void si_resource_copy_region(struct pipe_context *ctx,
872 struct pipe_resource *dst,
873 unsigned dst_level,
874 unsigned dstx, unsigned dsty, unsigned dstz,
875 struct pipe_resource *src,
876 unsigned src_level,
877 const struct pipe_box *src_box)
878 {
879 struct si_context *sctx = (struct si_context *)ctx;
880 struct si_texture *ssrc = (struct si_texture*)src;
881 struct si_texture *sdst = (struct si_texture*)dst;
882 struct pipe_surface *dst_view, dst_templ;
883 struct pipe_sampler_view src_templ, *src_view;
884 unsigned dst_width, dst_height, src_width0, src_height0;
885 unsigned dst_width0, dst_height0, src_force_level = 0;
886 struct pipe_box sbox, dstbox;
887
888 /* Handle buffers first. */
889 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
890 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
891 return;
892 }
893
894 if (!util_format_is_compressed(src->format) &&
895 !util_format_is_compressed(dst->format) &&
896 !util_format_is_depth_or_stencil(src->format) &&
897 src->nr_samples <= 1 &&
898 !sdst->dcc_offset &&
899 !(dst->target != src->target &&
900 (src->target == PIPE_TEXTURE_1D_ARRAY || dst->target == PIPE_TEXTURE_1D_ARRAY))) {
901 si_compute_copy_image(sctx, dst, dst_level, src, src_level, dstx, dsty, dstz, src_box);
902 return;
903 }
904
905 assert(u_max_sample(dst) == u_max_sample(src));
906
907 /* The driver doesn't decompress resources automatically while
908 * u_blitter is rendering. */
909 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
910 src_box->z, src_box->z + src_box->depth - 1);
911
912 dst_width = u_minify(dst->width0, dst_level);
913 dst_height = u_minify(dst->height0, dst_level);
914 dst_width0 = dst->width0;
915 dst_height0 = dst->height0;
916 src_width0 = src->width0;
917 src_height0 = src->height0;
918
919 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
920 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
921
922 if (util_format_is_compressed(src->format) ||
923 util_format_is_compressed(dst->format)) {
924 unsigned blocksize = ssrc->surface.bpe;
925
926 if (blocksize == 8)
927 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
928 else
929 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
930 dst_templ.format = src_templ.format;
931
932 dst_width = util_format_get_nblocksx(dst->format, dst_width);
933 dst_height = util_format_get_nblocksy(dst->format, dst_height);
934 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
935 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
936 src_width0 = util_format_get_nblocksx(src->format, src_width0);
937 src_height0 = util_format_get_nblocksy(src->format, src_height0);
938
939 dstx = util_format_get_nblocksx(dst->format, dstx);
940 dsty = util_format_get_nblocksy(dst->format, dsty);
941
942 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
943 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
944 sbox.z = src_box->z;
945 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
946 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
947 sbox.depth = src_box->depth;
948 src_box = &sbox;
949
950 src_force_level = src_level;
951 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
952 if (util_format_is_subsampled_422(src->format)) {
953 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
954 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
955
956 dst_width = util_format_get_nblocksx(dst->format, dst_width);
957 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
958 src_width0 = util_format_get_nblocksx(src->format, src_width0);
959
960 dstx = util_format_get_nblocksx(dst->format, dstx);
961
962 sbox = *src_box;
963 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
964 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
965 src_box = &sbox;
966 } else {
967 unsigned blocksize = ssrc->surface.bpe;
968
969 switch (blocksize) {
970 case 1:
971 dst_templ.format = PIPE_FORMAT_R8_UNORM;
972 src_templ.format = PIPE_FORMAT_R8_UNORM;
973 break;
974 case 2:
975 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
976 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
977 break;
978 case 4:
979 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
980 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
981 break;
982 case 8:
983 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
984 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
985 break;
986 case 16:
987 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
988 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
989 break;
990 default:
991 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
992 util_format_short_name(src->format), blocksize);
993 assert(0);
994 }
995 }
996 }
997
998 /* SNORM8 blitting has precision issues on some chips. Use the SINT
999 * equivalent instead, which doesn't force DCC decompression.
1000 * Note that some chips avoid this issue by using SDMA.
1001 */
1002 if (util_format_is_snorm8(dst_templ.format)) {
1003 dst_templ.format = src_templ.format =
1004 util_format_snorm8_to_sint8(dst_templ.format);
1005 }
1006
1007 vi_disable_dcc_if_incompatible_format(sctx, dst, dst_level,
1008 dst_templ.format);
1009 vi_disable_dcc_if_incompatible_format(sctx, src, src_level,
1010 src_templ.format);
1011
1012 /* Initialize the surface. */
1013 dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
1014 dst_width0, dst_height0,
1015 dst_width, dst_height);
1016
1017 /* Initialize the sampler view. */
1018 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1019 src_width0, src_height0,
1020 src_force_level);
1021
1022 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1023 abs(src_box->depth), &dstbox);
1024
1025 /* Copy. */
1026 si_blitter_begin(sctx, SI_COPY);
1027 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1028 src_view, src_box, src_width0, src_height0,
1029 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1030 false);
1031 si_blitter_end(sctx);
1032
1033 pipe_surface_reference(&dst_view, NULL);
1034 pipe_sampler_view_reference(&src_view, NULL);
1035 }
1036
1037 static void si_do_CB_resolve(struct si_context *sctx,
1038 const struct pipe_blit_info *info,
1039 struct pipe_resource *dst,
1040 unsigned dst_level, unsigned dst_z,
1041 enum pipe_format format)
1042 {
1043 /* Required before and after CB_RESOLVE. */
1044 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1045
1046 si_blitter_begin(sctx, SI_COLOR_RESOLVE |
1047 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1048 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1049 info->src.resource, info->src.box.z,
1050 ~0, sctx->custom_blend_resolve,
1051 format);
1052 si_blitter_end(sctx);
1053
1054 /* Flush caches for possible texturing. */
1055 si_make_CB_shader_coherent(sctx, 1, false, true /* no DCC */);
1056 }
1057
1058 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1059 const struct pipe_blit_info *info)
1060 {
1061 struct si_context *sctx = (struct si_context*)ctx;
1062 struct si_texture *src = (struct si_texture*)info->src.resource;
1063 struct si_texture *dst = (struct si_texture*)info->dst.resource;
1064 MAYBE_UNUSED struct si_texture *stmp;
1065 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1066 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1067 enum pipe_format format = info->src.format;
1068 struct pipe_resource *tmp, templ;
1069 struct pipe_blit_info blit;
1070
1071 /* Check basic requirements for hw resolve. */
1072 if (!(info->src.resource->nr_samples > 1 &&
1073 info->dst.resource->nr_samples <= 1 &&
1074 !util_format_is_pure_integer(format) &&
1075 !util_format_is_depth_or_stencil(format) &&
1076 util_max_layer(info->src.resource, 0) == 0))
1077 return false;
1078
1079 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1080 * the format is R16G16. Use R16A16, which does work.
1081 */
1082 if (format == PIPE_FORMAT_R16G16_UNORM)
1083 format = PIPE_FORMAT_R16A16_UNORM;
1084 if (format == PIPE_FORMAT_R16G16_SNORM)
1085 format = PIPE_FORMAT_R16A16_SNORM;
1086
1087 /* Check the remaining requirements for hw resolve. */
1088 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1089 !info->scissor_enable &&
1090 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1091 util_is_format_compatible(util_format_description(info->src.format),
1092 util_format_description(info->dst.format)) &&
1093 dst_width == info->src.resource->width0 &&
1094 dst_height == info->src.resource->height0 &&
1095 info->dst.box.x == 0 &&
1096 info->dst.box.y == 0 &&
1097 info->dst.box.width == dst_width &&
1098 info->dst.box.height == dst_height &&
1099 info->dst.box.depth == 1 &&
1100 info->src.box.x == 0 &&
1101 info->src.box.y == 0 &&
1102 info->src.box.width == dst_width &&
1103 info->src.box.height == dst_height &&
1104 info->src.box.depth == 1 &&
1105 !dst->surface.is_linear &&
1106 (!dst->cmask_buffer || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1107 /* Check the last constraint. */
1108 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1109 /* The next fast clear will switch to this mode to
1110 * get direct hw resolve next time if the mode is
1111 * different now.
1112 *
1113 * TODO-GFX10: This does not work in GFX10 because MSAA
1114 * is restricted to 64KB_R_X and 64KB_Z_X swizzle modes.
1115 * In some cases we could change the swizzle of the
1116 * destination texture instead, but the more general
1117 * solution is to implement compute shader resolve.
1118 */
1119 src->last_msaa_resolve_target_micro_mode =
1120 dst->surface.micro_tile_mode;
1121 goto resolve_to_temp;
1122 }
1123
1124 /* Resolving into a surface with DCC is unsupported. Since
1125 * it's being overwritten anyway, clear it to uncompressed.
1126 * This is still the fastest codepath even with this clear.
1127 */
1128 if (vi_dcc_enabled(dst, info->dst.level)) {
1129 /* TODO: Implement per-level DCC clears for GFX9. */
1130 if (sctx->chip_class >= GFX9 &&
1131 info->dst.resource->last_level != 0)
1132 goto resolve_to_temp;
1133
1134 /* This can happen with mipmapping. */
1135 if (sctx->chip_class == GFX8 &&
1136 !dst->surface.u.legacy.level[info->dst.level].dcc_fast_clear_size)
1137 goto resolve_to_temp;
1138
1139 vi_dcc_clear_level(sctx, dst, info->dst.level,
1140 0xFFFFFFFF);
1141 dst->dirty_level_mask &= ~(1 << info->dst.level);
1142 }
1143
1144 /* Resolve directly from src to dst. */
1145 si_do_CB_resolve(sctx, info, info->dst.resource,
1146 info->dst.level, info->dst.box.z, format);
1147 return true;
1148 }
1149
1150 resolve_to_temp:
1151 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1152 * a temporary texture and blit.
1153 */
1154 memset(&templ, 0, sizeof(templ));
1155 templ.target = PIPE_TEXTURE_2D;
1156 templ.format = info->src.resource->format;
1157 templ.width0 = info->src.resource->width0;
1158 templ.height0 = info->src.resource->height0;
1159 templ.depth0 = 1;
1160 templ.array_size = 1;
1161 templ.usage = PIPE_USAGE_DEFAULT;
1162 templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING |
1163 SI_RESOURCE_FLAG_DISABLE_DCC;
1164
1165 /* The src and dst microtile modes must be the same. */
1166 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1167 templ.bind = PIPE_BIND_SCANOUT;
1168 else
1169 templ.bind = 0;
1170
1171 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1172 if (!tmp)
1173 return false;
1174 stmp = (struct si_texture*)tmp;
1175
1176 assert(!stmp->surface.is_linear);
1177 assert(src->surface.micro_tile_mode == stmp->surface.micro_tile_mode);
1178
1179 /* resolve */
1180 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1181
1182 /* blit */
1183 blit = *info;
1184 blit.src.resource = tmp;
1185 blit.src.box.z = 0;
1186
1187 si_blitter_begin(sctx, SI_BLIT |
1188 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1189 util_blitter_blit(sctx->blitter, &blit);
1190 si_blitter_end(sctx);
1191
1192 pipe_resource_reference(&tmp, NULL);
1193 return true;
1194 }
1195
1196 static void si_blit(struct pipe_context *ctx,
1197 const struct pipe_blit_info *info)
1198 {
1199 struct si_context *sctx = (struct si_context*)ctx;
1200 struct si_texture *dst = (struct si_texture *)info->dst.resource;
1201
1202 if (do_hardware_msaa_resolve(ctx, info)) {
1203 return;
1204 }
1205
1206 /* Using SDMA for copying to a linear texture in GTT is much faster.
1207 * This improves DRI PRIME performance.
1208 *
1209 * resource_copy_region can't do this yet, because dma_copy calls it
1210 * on failure (recursion).
1211 */
1212 if (dst->surface.is_linear &&
1213 sctx->dma_copy &&
1214 util_can_blit_via_copy_region(info, false)) {
1215 sctx->dma_copy(ctx, info->dst.resource, info->dst.level,
1216 info->dst.box.x, info->dst.box.y,
1217 info->dst.box.z,
1218 info->src.resource, info->src.level,
1219 &info->src.box);
1220 return;
1221 }
1222
1223 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1224
1225 /* The driver doesn't decompress resources automatically while
1226 * u_blitter is rendering. */
1227 vi_disable_dcc_if_incompatible_format(sctx, info->src.resource,
1228 info->src.level,
1229 info->src.format);
1230 vi_disable_dcc_if_incompatible_format(sctx, info->dst.resource,
1231 info->dst.level,
1232 info->dst.format);
1233 si_decompress_subresource(ctx, info->src.resource, PIPE_MASK_RGBAZS,
1234 info->src.level,
1235 info->src.box.z,
1236 info->src.box.z + info->src.box.depth - 1);
1237
1238 if (sctx->screen->debug_flags & DBG(FORCE_DMA) &&
1239 util_try_blit_via_copy_region(ctx, info))
1240 return;
1241
1242 si_blitter_begin(sctx, SI_BLIT |
1243 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1244 util_blitter_blit(sctx->blitter, info);
1245 si_blitter_end(sctx);
1246 }
1247
1248 static boolean si_generate_mipmap(struct pipe_context *ctx,
1249 struct pipe_resource *tex,
1250 enum pipe_format format,
1251 unsigned base_level, unsigned last_level,
1252 unsigned first_layer, unsigned last_layer)
1253 {
1254 struct si_context *sctx = (struct si_context*)ctx;
1255 struct si_texture *stex = (struct si_texture *)tex;
1256
1257 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1258 return false;
1259
1260 /* The driver doesn't decompress resources automatically while
1261 * u_blitter is rendering. */
1262 vi_disable_dcc_if_incompatible_format(sctx, tex, base_level,
1263 format);
1264 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1265 base_level, first_layer, last_layer);
1266
1267 /* Clear dirty_level_mask for the levels that will be overwritten. */
1268 assert(base_level < last_level);
1269 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1270 last_level - base_level);
1271
1272 sctx->generate_mipmap_for_depth = stex->is_depth;
1273
1274 si_blitter_begin(sctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1275 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1276 base_level, last_level,
1277 first_layer, last_layer);
1278 si_blitter_end(sctx);
1279
1280 sctx->generate_mipmap_for_depth = false;
1281 return true;
1282 }
1283
1284 static void si_flush_resource(struct pipe_context *ctx,
1285 struct pipe_resource *res)
1286 {
1287 struct si_context *sctx = (struct si_context*)ctx;
1288 struct si_texture *tex = (struct si_texture*)res;
1289
1290 assert(res->target != PIPE_BUFFER);
1291 assert(!tex->dcc_separate_buffer || tex->dcc_gather_statistics);
1292
1293 /* st/dri calls flush twice per frame (not a bug), this prevents double
1294 * decompression. */
1295 if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
1296 return;
1297
1298 if (!tex->is_depth && (tex->cmask_buffer || tex->dcc_offset)) {
1299 si_blit_decompress_color(sctx, tex, 0, res->last_level,
1300 0, util_max_layer(res, 0),
1301 tex->dcc_separate_buffer != NULL);
1302
1303 if (tex->display_dcc_offset)
1304 si_retile_dcc(sctx, tex);
1305 }
1306
1307 /* Always do the analysis even if DCC is disabled at the moment. */
1308 if (tex->dcc_gather_statistics) {
1309 bool separate_dcc_dirty = tex->separate_dcc_dirty;
1310
1311 /* If the color buffer hasn't been unbound and fast clear hasn't
1312 * been used, separate_dcc_dirty is false, but there may have been
1313 * new rendering. Check if the color buffer is bound and assume
1314 * it's dirty.
1315 *
1316 * Note that DRI2 never unbinds window colorbuffers, which means
1317 * the DCC pipeline statistics query would never be re-set and would
1318 * keep adding new results until all free memory is exhausted if we
1319 * didn't do this.
1320 */
1321 if (!separate_dcc_dirty) {
1322 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
1323 if (sctx->framebuffer.state.cbufs[i] &&
1324 sctx->framebuffer.state.cbufs[i]->texture == res) {
1325 separate_dcc_dirty = true;
1326 break;
1327 }
1328 }
1329 }
1330
1331 if (separate_dcc_dirty) {
1332 tex->separate_dcc_dirty = false;
1333 vi_separate_dcc_process_and_reset_stats(ctx, tex);
1334 }
1335 }
1336 }
1337
1338 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
1339 {
1340 /* If graphics is disabled, we can't decompress DCC, but it shouldn't
1341 * be compressed either. The caller should simply discard it.
1342 */
1343 if (!tex->dcc_offset || !sctx->has_graphics)
1344 return;
1345
1346 si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level,
1347 0, util_max_layer(&tex->buffer.b.b, 0),
1348 true);
1349 }
1350
1351 void si_init_blit_functions(struct si_context *sctx)
1352 {
1353 sctx->b.resource_copy_region = si_resource_copy_region;
1354
1355 if (sctx->has_graphics) {
1356 sctx->b.blit = si_blit;
1357 sctx->b.flush_resource = si_flush_resource;
1358 sctx->b.generate_mipmap = si_generate_mipmap;
1359 }
1360 }