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radeonsi: rename r600_texture -> si_texture, rxxx -> xxx or sxxx
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_compute.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
34 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
35
36 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
37 SI_SAVE_FRAGMENT_STATE,
38
39 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
40 SI_DISABLE_RENDER_COND,
41
42 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
43 };
44
45 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op)
46 {
47 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
48 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
49 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
50 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
51 util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets,
52 (struct pipe_stream_output_target**)sctx->streamout.targets);
53 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
54
55 if (op & SI_SAVE_FRAGMENT_STATE) {
56 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
57 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
58 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
59 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
60 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask);
61 util_blitter_save_scissor(sctx->blitter, &sctx->scissors.states[0]);
62 }
63
64 if (op & SI_SAVE_FRAMEBUFFER)
65 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
66
67 if (op & SI_SAVE_TEXTURES) {
68 util_blitter_save_fragment_sampler_states(
69 sctx->blitter, 2,
70 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
71
72 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
73 sctx->samplers[PIPE_SHADER_FRAGMENT].views);
74 }
75
76 if (op & SI_DISABLE_RENDER_COND)
77 sctx->render_cond_force_off = true;
78
79 if (sctx->screen->dpbb_allowed) {
80 sctx->dpbb_force_off = true;
81 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
82 }
83 }
84
85 void si_blitter_end(struct si_context *sctx)
86 {
87 if (sctx->screen->dpbb_allowed) {
88 sctx->dpbb_force_off = false;
89 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
90 }
91
92 sctx->render_cond_force_off = false;
93
94 /* Restore shader pointers because the VS blit shader changed all
95 * non-global VS user SGPRs. */
96 sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX);
97 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
98 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
99 }
100
101 static unsigned u_max_sample(struct pipe_resource *r)
102 {
103 return r->nr_samples ? r->nr_samples - 1 : 0;
104 }
105
106 static unsigned
107 si_blit_dbcb_copy(struct si_context *sctx,
108 struct si_texture *src,
109 struct si_texture *dst,
110 unsigned planes, unsigned level_mask,
111 unsigned first_layer, unsigned last_layer,
112 unsigned first_sample, unsigned last_sample)
113 {
114 struct pipe_surface surf_tmpl = {{0}};
115 unsigned layer, sample, checked_last_layer, max_layer;
116 unsigned fully_copied_levels = 0;
117
118 if (planes & PIPE_MASK_Z)
119 sctx->dbcb_depth_copy_enabled = true;
120 if (planes & PIPE_MASK_S)
121 sctx->dbcb_stencil_copy_enabled = true;
122 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
123
124 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
125
126 sctx->decompression_enabled = true;
127
128 while (level_mask) {
129 unsigned level = u_bit_scan(&level_mask);
130
131 /* The smaller the mipmap level, the less layers there are
132 * as far as 3D textures are concerned. */
133 max_layer = util_max_layer(&src->buffer.b.b, level);
134 checked_last_layer = MIN2(last_layer, max_layer);
135
136 surf_tmpl.u.tex.level = level;
137
138 for (layer = first_layer; layer <= checked_last_layer; layer++) {
139 struct pipe_surface *zsurf, *cbsurf;
140
141 surf_tmpl.format = src->buffer.b.b.format;
142 surf_tmpl.u.tex.first_layer = layer;
143 surf_tmpl.u.tex.last_layer = layer;
144
145 zsurf = sctx->b.create_surface(&sctx->b, &src->buffer.b.b, &surf_tmpl);
146
147 surf_tmpl.format = dst->buffer.b.b.format;
148 cbsurf = sctx->b.create_surface(&sctx->b, &dst->buffer.b.b, &surf_tmpl);
149
150 for (sample = first_sample; sample <= last_sample; sample++) {
151 if (sample != sctx->dbcb_copy_sample) {
152 sctx->dbcb_copy_sample = sample;
153 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
154 }
155
156 si_blitter_begin(sctx, SI_DECOMPRESS);
157 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
158 sctx->custom_dsa_flush, 1.0f);
159 si_blitter_end(sctx);
160 }
161
162 pipe_surface_reference(&zsurf, NULL);
163 pipe_surface_reference(&cbsurf, NULL);
164 }
165
166 if (first_layer == 0 && last_layer >= max_layer &&
167 first_sample == 0 && last_sample >= u_max_sample(&src->buffer.b.b))
168 fully_copied_levels |= 1u << level;
169 }
170
171 sctx->decompression_enabled = false;
172 sctx->dbcb_depth_copy_enabled = false;
173 sctx->dbcb_stencil_copy_enabled = false;
174 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
175
176 return fully_copied_levels;
177 }
178
179 void si_blit_decompress_depth(struct pipe_context *ctx,
180 struct si_texture *texture,
181 struct si_texture *staging,
182 unsigned first_level, unsigned last_level,
183 unsigned first_layer, unsigned last_layer,
184 unsigned first_sample, unsigned last_sample)
185 {
186 const struct util_format_description *desc;
187 unsigned planes = 0;
188
189 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
190
191 desc = util_format_description(staging->buffer.b.b.format);
192
193 if (util_format_has_depth(desc))
194 planes |= PIPE_MASK_Z;
195 if (util_format_has_stencil(desc))
196 planes |= PIPE_MASK_S;
197
198 si_blit_dbcb_copy(
199 (struct si_context *)ctx, texture, staging, planes,
200 u_bit_consecutive(first_level, last_level - first_level + 1),
201 first_layer, last_layer, first_sample, last_sample);
202 }
203
204 /* Helper function for si_blit_decompress_zs_in_place.
205 */
206 static void
207 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
208 struct si_texture *texture,
209 unsigned planes, unsigned level_mask,
210 unsigned first_layer, unsigned last_layer)
211 {
212 struct pipe_surface *zsurf, surf_tmpl = {{0}};
213 unsigned layer, max_layer, checked_last_layer;
214 unsigned fully_decompressed_mask = 0;
215
216 if (!level_mask)
217 return;
218
219 if (planes & PIPE_MASK_S)
220 sctx->db_flush_stencil_inplace = true;
221 if (planes & PIPE_MASK_Z)
222 sctx->db_flush_depth_inplace = true;
223 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
224
225 surf_tmpl.format = texture->buffer.b.b.format;
226
227 sctx->decompression_enabled = true;
228
229 while (level_mask) {
230 unsigned level = u_bit_scan(&level_mask);
231
232 surf_tmpl.u.tex.level = level;
233
234 /* The smaller the mipmap level, the less layers there are
235 * as far as 3D textures are concerned. */
236 max_layer = util_max_layer(&texture->buffer.b.b, level);
237 checked_last_layer = MIN2(last_layer, max_layer);
238
239 for (layer = first_layer; layer <= checked_last_layer; layer++) {
240 surf_tmpl.u.tex.first_layer = layer;
241 surf_tmpl.u.tex.last_layer = layer;
242
243 zsurf = sctx->b.create_surface(&sctx->b, &texture->buffer.b.b, &surf_tmpl);
244
245 si_blitter_begin(sctx, SI_DECOMPRESS);
246 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
247 sctx->custom_dsa_flush,
248 1.0f);
249 si_blitter_end(sctx);
250
251 pipe_surface_reference(&zsurf, NULL);
252 }
253
254 /* The texture will always be dirty if some layers aren't flushed.
255 * I don't think this case occurs often though. */
256 if (first_layer == 0 && last_layer >= max_layer) {
257 fully_decompressed_mask |= 1u << level;
258 }
259 }
260
261 if (planes & PIPE_MASK_Z)
262 texture->dirty_level_mask &= ~fully_decompressed_mask;
263 if (planes & PIPE_MASK_S)
264 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
265
266 sctx->decompression_enabled = false;
267 sctx->db_flush_depth_inplace = false;
268 sctx->db_flush_stencil_inplace = false;
269 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
270 }
271
272 /* Helper function of si_flush_depth_texture: decompress the given levels
273 * of Z and/or S planes in place.
274 */
275 static void
276 si_blit_decompress_zs_in_place(struct si_context *sctx,
277 struct si_texture *texture,
278 unsigned levels_z, unsigned levels_s,
279 unsigned first_layer, unsigned last_layer)
280 {
281 unsigned both = levels_z & levels_s;
282
283 /* First, do combined Z & S decompresses for levels that need it. */
284 if (both) {
285 si_blit_decompress_zs_planes_in_place(
286 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
287 both,
288 first_layer, last_layer);
289 levels_z &= ~both;
290 levels_s &= ~both;
291 }
292
293 /* Now do separate Z and S decompresses. */
294 if (levels_z) {
295 si_blit_decompress_zs_planes_in_place(
296 sctx, texture, PIPE_MASK_Z,
297 levels_z,
298 first_layer, last_layer);
299 }
300
301 if (levels_s) {
302 si_blit_decompress_zs_planes_in_place(
303 sctx, texture, PIPE_MASK_S,
304 levels_s,
305 first_layer, last_layer);
306 }
307 }
308
309 static void
310 si_decompress_depth(struct si_context *sctx,
311 struct si_texture *tex,
312 unsigned required_planes,
313 unsigned first_level, unsigned last_level,
314 unsigned first_layer, unsigned last_layer)
315 {
316 unsigned inplace_planes = 0;
317 unsigned copy_planes = 0;
318 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
319 unsigned levels_z = 0;
320 unsigned levels_s = 0;
321
322 if (required_planes & PIPE_MASK_Z) {
323 levels_z = level_mask & tex->dirty_level_mask;
324
325 if (levels_z) {
326 if (si_can_sample_zs(tex, false))
327 inplace_planes |= PIPE_MASK_Z;
328 else
329 copy_planes |= PIPE_MASK_Z;
330 }
331 }
332 if (required_planes & PIPE_MASK_S) {
333 levels_s = level_mask & tex->stencil_dirty_level_mask;
334
335 if (levels_s) {
336 if (si_can_sample_zs(tex, true))
337 inplace_planes |= PIPE_MASK_S;
338 else
339 copy_planes |= PIPE_MASK_S;
340 }
341 }
342
343 if (unlikely(sctx->log))
344 u_log_printf(sctx->log,
345 "\n------------------------------------------------\n"
346 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
347 first_level, last_level, levels_z, levels_s);
348
349 /* We may have to allocate the flushed texture here when called from
350 * si_decompress_subresource.
351 */
352 if (copy_planes &&
353 (tex->flushed_depth_texture ||
354 si_init_flushed_depth_texture(&sctx->b, &tex->buffer.b.b, NULL))) {
355 struct si_texture *dst = tex->flushed_depth_texture;
356 unsigned fully_copied_levels;
357 unsigned levels = 0;
358
359 assert(tex->flushed_depth_texture);
360
361 if (util_format_is_depth_and_stencil(dst->buffer.b.b.format))
362 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
363
364 if (copy_planes & PIPE_MASK_Z) {
365 levels |= levels_z;
366 levels_z = 0;
367 }
368 if (copy_planes & PIPE_MASK_S) {
369 levels |= levels_s;
370 levels_s = 0;
371 }
372
373 fully_copied_levels = si_blit_dbcb_copy(
374 sctx, tex, dst, copy_planes, levels,
375 first_layer, last_layer,
376 0, u_max_sample(&tex->buffer.b.b));
377
378 if (copy_planes & PIPE_MASK_Z)
379 tex->dirty_level_mask &= ~fully_copied_levels;
380 if (copy_planes & PIPE_MASK_S)
381 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
382 }
383
384 if (inplace_planes) {
385 bool has_htile = si_htile_enabled(tex, first_level);
386 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
387
388 /* Don't decompress if there is no HTILE or when HTILE is
389 * TC-compatible. */
390 if (has_htile && !tc_compat_htile) {
391 si_blit_decompress_zs_in_place(
392 sctx, tex,
393 levels_z, levels_s,
394 first_layer, last_layer);
395 } else {
396 /* This is only a cache flush.
397 *
398 * Only clear the mask that we are flushing, because
399 * si_make_DB_shader_coherent() treats different levels
400 * and depth and stencil differently.
401 */
402 if (inplace_planes & PIPE_MASK_Z)
403 tex->dirty_level_mask &= ~levels_z;
404 if (inplace_planes & PIPE_MASK_S)
405 tex->stencil_dirty_level_mask &= ~levels_s;
406 }
407
408 /* Only in-place decompression needs to flush DB caches, or
409 * when we don't decompress but TC-compatible planes are dirty.
410 */
411 si_make_DB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
412 inplace_planes & PIPE_MASK_S,
413 tc_compat_htile);
414 }
415 /* set_framebuffer_state takes care of coherency for single-sample.
416 * The DB->CB copy uses CB for the final writes.
417 */
418 if (copy_planes && tex->buffer.b.b.nr_samples > 1)
419 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
420 false);
421 }
422
423 static void
424 si_decompress_sampler_depth_textures(struct si_context *sctx,
425 struct si_samplers *textures)
426 {
427 unsigned i;
428 unsigned mask = textures->needs_depth_decompress_mask;
429
430 while (mask) {
431 struct pipe_sampler_view *view;
432 struct si_sampler_view *sview;
433 struct si_texture *tex;
434
435 i = u_bit_scan(&mask);
436
437 view = textures->views[i];
438 assert(view);
439 sview = (struct si_sampler_view*)view;
440
441 tex = (struct si_texture *)view->texture;
442 assert(tex->db_compatible);
443
444 si_decompress_depth(sctx, tex,
445 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
446 view->u.tex.first_level, view->u.tex.last_level,
447 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
448 }
449 }
450
451 static void si_blit_decompress_color(struct si_context *sctx,
452 struct si_texture *tex,
453 unsigned first_level, unsigned last_level,
454 unsigned first_layer, unsigned last_layer,
455 bool need_dcc_decompress)
456 {
457 void* custom_blend;
458 unsigned layer, checked_last_layer, max_layer;
459 unsigned level_mask =
460 u_bit_consecutive(first_level, last_level - first_level + 1);
461
462 if (!need_dcc_decompress)
463 level_mask &= tex->dirty_level_mask;
464 if (!level_mask)
465 return;
466
467 if (unlikely(sctx->log))
468 u_log_printf(sctx->log,
469 "\n------------------------------------------------\n"
470 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
471 first_level, last_level, level_mask);
472
473 if (need_dcc_decompress) {
474 custom_blend = sctx->custom_blend_dcc_decompress;
475
476 assert(tex->dcc_offset);
477
478 /* disable levels without DCC */
479 for (int i = first_level; i <= last_level; i++) {
480 if (!vi_dcc_enabled(tex, i))
481 level_mask &= ~(1 << i);
482 }
483 } else if (tex->surface.fmask_size) {
484 custom_blend = sctx->custom_blend_fmask_decompress;
485 } else {
486 custom_blend = sctx->custom_blend_eliminate_fastclear;
487 }
488
489 sctx->decompression_enabled = true;
490
491 while (level_mask) {
492 unsigned level = u_bit_scan(&level_mask);
493
494 /* The smaller the mipmap level, the less layers there are
495 * as far as 3D textures are concerned. */
496 max_layer = util_max_layer(&tex->buffer.b.b, level);
497 checked_last_layer = MIN2(last_layer, max_layer);
498
499 for (layer = first_layer; layer <= checked_last_layer; layer++) {
500 struct pipe_surface *cbsurf, surf_tmpl;
501
502 surf_tmpl.format = tex->buffer.b.b.format;
503 surf_tmpl.u.tex.level = level;
504 surf_tmpl.u.tex.first_layer = layer;
505 surf_tmpl.u.tex.last_layer = layer;
506 cbsurf = sctx->b.create_surface(&sctx->b, &tex->buffer.b.b, &surf_tmpl);
507
508 /* Required before and after FMASK and DCC_DECOMPRESS. */
509 if (custom_blend == sctx->custom_blend_fmask_decompress ||
510 custom_blend == sctx->custom_blend_dcc_decompress)
511 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
512
513 si_blitter_begin(sctx, SI_DECOMPRESS);
514 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
515 si_blitter_end(sctx);
516
517 if (custom_blend == sctx->custom_blend_fmask_decompress ||
518 custom_blend == sctx->custom_blend_dcc_decompress)
519 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
520
521 pipe_surface_reference(&cbsurf, NULL);
522 }
523
524 /* The texture will always be dirty if some layers aren't flushed.
525 * I don't think this case occurs often though. */
526 if (first_layer == 0 && last_layer >= max_layer) {
527 tex->dirty_level_mask &= ~(1 << level);
528 }
529 }
530
531 sctx->decompression_enabled = false;
532 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
533 vi_dcc_enabled(tex, first_level));
534 }
535
536 static void
537 si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex,
538 unsigned first_level, unsigned last_level)
539 {
540 /* CMASK or DCC can be discarded and we can still end up here. */
541 if (!tex->cmask.size && !tex->surface.fmask_size && !tex->dcc_offset)
542 return;
543
544 si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
545 util_max_layer(&tex->buffer.b.b, first_level),
546 false);
547 }
548
549 static void
550 si_decompress_sampler_color_textures(struct si_context *sctx,
551 struct si_samplers *textures)
552 {
553 unsigned i;
554 unsigned mask = textures->needs_color_decompress_mask;
555
556 while (mask) {
557 struct pipe_sampler_view *view;
558 struct si_texture *tex;
559
560 i = u_bit_scan(&mask);
561
562 view = textures->views[i];
563 assert(view);
564
565 tex = (struct si_texture *)view->texture;
566
567 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
568 view->u.tex.last_level);
569 }
570 }
571
572 static void
573 si_decompress_image_color_textures(struct si_context *sctx,
574 struct si_images *images)
575 {
576 unsigned i;
577 unsigned mask = images->needs_color_decompress_mask;
578
579 while (mask) {
580 const struct pipe_image_view *view;
581 struct si_texture *tex;
582
583 i = u_bit_scan(&mask);
584
585 view = &images->views[i];
586 assert(view->resource->target != PIPE_BUFFER);
587
588 tex = (struct si_texture *)view->resource;
589
590 si_decompress_color_texture(sctx, tex, view->u.tex.level,
591 view->u.tex.level);
592 }
593 }
594
595 static void si_check_render_feedback_texture(struct si_context *sctx,
596 struct si_texture *tex,
597 unsigned first_level,
598 unsigned last_level,
599 unsigned first_layer,
600 unsigned last_layer)
601 {
602 bool render_feedback = false;
603
604 if (!tex->dcc_offset)
605 return;
606
607 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
608 struct r600_surface * surf;
609
610 if (!sctx->framebuffer.state.cbufs[j])
611 continue;
612
613 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
614
615 if (tex == (struct si_texture *)surf->base.texture &&
616 surf->base.u.tex.level >= first_level &&
617 surf->base.u.tex.level <= last_level &&
618 surf->base.u.tex.first_layer <= last_layer &&
619 surf->base.u.tex.last_layer >= first_layer) {
620 render_feedback = true;
621 break;
622 }
623 }
624
625 if (render_feedback)
626 si_texture_disable_dcc(sctx, tex);
627 }
628
629 static void si_check_render_feedback_textures(struct si_context *sctx,
630 struct si_samplers *textures)
631 {
632 uint32_t mask = textures->enabled_mask;
633
634 while (mask) {
635 const struct pipe_sampler_view *view;
636 struct si_texture *tex;
637
638 unsigned i = u_bit_scan(&mask);
639
640 view = textures->views[i];
641 if(view->texture->target == PIPE_BUFFER)
642 continue;
643
644 tex = (struct si_texture *)view->texture;
645
646 si_check_render_feedback_texture(sctx, tex,
647 view->u.tex.first_level,
648 view->u.tex.last_level,
649 view->u.tex.first_layer,
650 view->u.tex.last_layer);
651 }
652 }
653
654 static void si_check_render_feedback_images(struct si_context *sctx,
655 struct si_images *images)
656 {
657 uint32_t mask = images->enabled_mask;
658
659 while (mask) {
660 const struct pipe_image_view *view;
661 struct si_texture *tex;
662
663 unsigned i = u_bit_scan(&mask);
664
665 view = &images->views[i];
666 if (view->resource->target == PIPE_BUFFER)
667 continue;
668
669 tex = (struct si_texture *)view->resource;
670
671 si_check_render_feedback_texture(sctx, tex,
672 view->u.tex.level,
673 view->u.tex.level,
674 view->u.tex.first_layer,
675 view->u.tex.last_layer);
676 }
677 }
678
679 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
680 {
681 util_dynarray_foreach(&sctx->resident_tex_handles,
682 struct si_texture_handle *, tex_handle) {
683 struct pipe_sampler_view *view;
684 struct si_texture *tex;
685
686 view = (*tex_handle)->view;
687 if (view->texture->target == PIPE_BUFFER)
688 continue;
689
690 tex = (struct si_texture *)view->texture;
691
692 si_check_render_feedback_texture(sctx, tex,
693 view->u.tex.first_level,
694 view->u.tex.last_level,
695 view->u.tex.first_layer,
696 view->u.tex.last_layer);
697 }
698 }
699
700 static void si_check_render_feedback_resident_images(struct si_context *sctx)
701 {
702 util_dynarray_foreach(&sctx->resident_img_handles,
703 struct si_image_handle *, img_handle) {
704 struct pipe_image_view *view;
705 struct si_texture *tex;
706
707 view = &(*img_handle)->view;
708 if (view->resource->target == PIPE_BUFFER)
709 continue;
710
711 tex = (struct si_texture *)view->resource;
712
713 si_check_render_feedback_texture(sctx, tex,
714 view->u.tex.level,
715 view->u.tex.level,
716 view->u.tex.first_layer,
717 view->u.tex.last_layer);
718 }
719 }
720
721 static void si_check_render_feedback(struct si_context *sctx)
722 {
723 if (!sctx->need_check_render_feedback)
724 return;
725
726 /* There is no render feedback if color writes are disabled.
727 * (e.g. a pixel shader with image stores)
728 */
729 if (!si_get_total_colormask(sctx))
730 return;
731
732 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
733 si_check_render_feedback_images(sctx, &sctx->images[i]);
734 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
735 }
736
737 si_check_render_feedback_resident_images(sctx);
738 si_check_render_feedback_resident_textures(sctx);
739
740 sctx->need_check_render_feedback = false;
741 }
742
743 static void si_decompress_resident_textures(struct si_context *sctx)
744 {
745 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
746 struct si_texture_handle *, tex_handle) {
747 struct pipe_sampler_view *view = (*tex_handle)->view;
748 struct si_texture *tex = (struct si_texture *)view->texture;
749
750 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
751 view->u.tex.last_level);
752 }
753
754 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
755 struct si_texture_handle *, tex_handle) {
756 struct pipe_sampler_view *view = (*tex_handle)->view;
757 struct si_sampler_view *sview = (struct si_sampler_view *)view;
758 struct si_texture *tex = (struct si_texture *)view->texture;
759
760 si_decompress_depth(sctx, tex,
761 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
762 view->u.tex.first_level, view->u.tex.last_level,
763 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
764 }
765 }
766
767 static void si_decompress_resident_images(struct si_context *sctx)
768 {
769 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
770 struct si_image_handle *, img_handle) {
771 struct pipe_image_view *view = &(*img_handle)->view;
772 struct si_texture *tex = (struct si_texture *)view->resource;
773
774 si_decompress_color_texture(sctx, tex, view->u.tex.level,
775 view->u.tex.level);
776 }
777 }
778
779 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
780 {
781 unsigned compressed_colortex_counter, mask;
782
783 if (sctx->blitter->running)
784 return;
785
786 /* Update the compressed_colortex_mask if necessary. */
787 compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter);
788 if (compressed_colortex_counter != sctx->last_compressed_colortex_counter) {
789 sctx->last_compressed_colortex_counter = compressed_colortex_counter;
790 si_update_needs_color_decompress_masks(sctx);
791 }
792
793 /* Decompress color & depth textures if needed. */
794 mask = sctx->shader_needs_decompress_mask & shader_mask;
795 while (mask) {
796 unsigned i = u_bit_scan(&mask);
797
798 if (sctx->samplers[i].needs_depth_decompress_mask) {
799 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
800 }
801 if (sctx->samplers[i].needs_color_decompress_mask) {
802 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
803 }
804 if (sctx->images[i].needs_color_decompress_mask) {
805 si_decompress_image_color_textures(sctx, &sctx->images[i]);
806 }
807 }
808
809 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
810 if (sctx->uses_bindless_samplers)
811 si_decompress_resident_textures(sctx);
812 if (sctx->uses_bindless_images)
813 si_decompress_resident_images(sctx);
814
815 if (sctx->ps_uses_fbfetch) {
816 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
817 si_decompress_color_texture(sctx,
818 (struct si_texture*)cb0->texture,
819 cb0->u.tex.first_layer,
820 cb0->u.tex.last_layer);
821 }
822
823 si_check_render_feedback(sctx);
824 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
825 if (sctx->cs_shader_state.program->uses_bindless_samplers)
826 si_decompress_resident_textures(sctx);
827 if (sctx->cs_shader_state.program->uses_bindless_images)
828 si_decompress_resident_images(sctx);
829 }
830 }
831
832 /* Helper for decompressing a portion of a color or depth resource before
833 * blitting if any decompression is needed.
834 * The driver doesn't decompress resources automatically while u_blitter is
835 * rendering. */
836 static void si_decompress_subresource(struct pipe_context *ctx,
837 struct pipe_resource *tex,
838 unsigned planes, unsigned level,
839 unsigned first_layer, unsigned last_layer)
840 {
841 struct si_context *sctx = (struct si_context *)ctx;
842 struct si_texture *stex = (struct si_texture*)tex;
843
844 if (stex->db_compatible) {
845 planes &= PIPE_MASK_Z | PIPE_MASK_S;
846
847 if (!stex->surface.has_stencil)
848 planes &= ~PIPE_MASK_S;
849
850 /* If we've rendered into the framebuffer and it's a blitting
851 * source, make sure the decompression pass is invoked
852 * by dirtying the framebuffer.
853 */
854 if (sctx->framebuffer.state.zsbuf &&
855 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
856 sctx->framebuffer.state.zsbuf->texture == tex)
857 si_update_fb_dirtiness_after_rendering(sctx);
858
859 si_decompress_depth(sctx, stex, planes,
860 level, level,
861 first_layer, last_layer);
862 } else if (stex->surface.fmask_size || stex->cmask.size || stex->dcc_offset) {
863 /* If we've rendered into the framebuffer and it's a blitting
864 * source, make sure the decompression pass is invoked
865 * by dirtying the framebuffer.
866 */
867 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
868 if (sctx->framebuffer.state.cbufs[i] &&
869 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
870 sctx->framebuffer.state.cbufs[i]->texture == tex) {
871 si_update_fb_dirtiness_after_rendering(sctx);
872 break;
873 }
874 }
875
876 si_blit_decompress_color(sctx, stex, level, level,
877 first_layer, last_layer, false);
878 }
879 }
880
881 struct texture_orig_info {
882 unsigned format;
883 unsigned width0;
884 unsigned height0;
885 unsigned npix_x;
886 unsigned npix_y;
887 unsigned npix0_x;
888 unsigned npix0_y;
889 };
890
891 void si_resource_copy_region(struct pipe_context *ctx,
892 struct pipe_resource *dst,
893 unsigned dst_level,
894 unsigned dstx, unsigned dsty, unsigned dstz,
895 struct pipe_resource *src,
896 unsigned src_level,
897 const struct pipe_box *src_box)
898 {
899 struct si_context *sctx = (struct si_context *)ctx;
900 struct si_texture *ssrc = (struct si_texture*)src;
901 struct pipe_surface *dst_view, dst_templ;
902 struct pipe_sampler_view src_templ, *src_view;
903 unsigned dst_width, dst_height, src_width0, src_height0;
904 unsigned dst_width0, dst_height0, src_force_level = 0;
905 struct pipe_box sbox, dstbox;
906
907 /* Handle buffers first. */
908 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
909 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
910 return;
911 }
912
913 assert(u_max_sample(dst) == u_max_sample(src));
914
915 /* The driver doesn't decompress resources automatically while
916 * u_blitter is rendering. */
917 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
918 src_box->z, src_box->z + src_box->depth - 1);
919
920 dst_width = u_minify(dst->width0, dst_level);
921 dst_height = u_minify(dst->height0, dst_level);
922 dst_width0 = dst->width0;
923 dst_height0 = dst->height0;
924 src_width0 = src->width0;
925 src_height0 = src->height0;
926
927 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
928 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
929
930 if (util_format_is_compressed(src->format) ||
931 util_format_is_compressed(dst->format)) {
932 unsigned blocksize = ssrc->surface.bpe;
933
934 if (blocksize == 8)
935 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
936 else
937 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
938 dst_templ.format = src_templ.format;
939
940 dst_width = util_format_get_nblocksx(dst->format, dst_width);
941 dst_height = util_format_get_nblocksy(dst->format, dst_height);
942 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
943 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
944 src_width0 = util_format_get_nblocksx(src->format, src_width0);
945 src_height0 = util_format_get_nblocksy(src->format, src_height0);
946
947 dstx = util_format_get_nblocksx(dst->format, dstx);
948 dsty = util_format_get_nblocksy(dst->format, dsty);
949
950 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
951 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
952 sbox.z = src_box->z;
953 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
954 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
955 sbox.depth = src_box->depth;
956 src_box = &sbox;
957
958 src_force_level = src_level;
959 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
960 if (util_format_is_subsampled_422(src->format)) {
961 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
962 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
963
964 dst_width = util_format_get_nblocksx(dst->format, dst_width);
965 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
966 src_width0 = util_format_get_nblocksx(src->format, src_width0);
967
968 dstx = util_format_get_nblocksx(dst->format, dstx);
969
970 sbox = *src_box;
971 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
972 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
973 src_box = &sbox;
974 } else {
975 unsigned blocksize = ssrc->surface.bpe;
976
977 switch (blocksize) {
978 case 1:
979 dst_templ.format = PIPE_FORMAT_R8_UNORM;
980 src_templ.format = PIPE_FORMAT_R8_UNORM;
981 break;
982 case 2:
983 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
984 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
985 break;
986 case 4:
987 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
988 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
989 break;
990 case 8:
991 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
992 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
993 break;
994 case 16:
995 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
996 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
997 break;
998 default:
999 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1000 util_format_short_name(src->format), blocksize);
1001 assert(0);
1002 }
1003 }
1004 }
1005
1006 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1007 * equivalent instead, which doesn't force DCC decompression.
1008 * Note that some chips avoid this issue by using SDMA.
1009 */
1010 if (util_format_is_snorm8(dst_templ.format)) {
1011 switch (dst_templ.format) {
1012 case PIPE_FORMAT_R8_SNORM:
1013 dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
1014 break;
1015 case PIPE_FORMAT_R8G8_SNORM:
1016 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
1017 break;
1018 case PIPE_FORMAT_R8G8B8X8_SNORM:
1019 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
1020 break;
1021 case PIPE_FORMAT_R8G8B8A8_SNORM:
1022 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1023 case PIPE_FORMAT_A8B8G8R8_SNORM:
1024 case PIPE_FORMAT_X8B8G8R8_SNORM:
1025 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
1026 break;
1027 case PIPE_FORMAT_A8_SNORM:
1028 dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
1029 break;
1030 case PIPE_FORMAT_L8_SNORM:
1031 dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
1032 break;
1033 case PIPE_FORMAT_L8A8_SNORM:
1034 dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
1035 break;
1036 case PIPE_FORMAT_I8_SNORM:
1037 dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
1038 break;
1039 default:; /* fall through */
1040 }
1041 }
1042
1043 vi_disable_dcc_if_incompatible_format(sctx, dst, dst_level,
1044 dst_templ.format);
1045 vi_disable_dcc_if_incompatible_format(sctx, src, src_level,
1046 src_templ.format);
1047
1048 /* Initialize the surface. */
1049 dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
1050 dst_width0, dst_height0,
1051 dst_width, dst_height);
1052
1053 /* Initialize the sampler view. */
1054 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1055 src_width0, src_height0,
1056 src_force_level);
1057
1058 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1059 abs(src_box->depth), &dstbox);
1060
1061 /* Copy. */
1062 si_blitter_begin(sctx, SI_COPY);
1063 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1064 src_view, src_box, src_width0, src_height0,
1065 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1066 false);
1067 si_blitter_end(sctx);
1068
1069 pipe_surface_reference(&dst_view, NULL);
1070 pipe_sampler_view_reference(&src_view, NULL);
1071 }
1072
1073 static void si_do_CB_resolve(struct si_context *sctx,
1074 const struct pipe_blit_info *info,
1075 struct pipe_resource *dst,
1076 unsigned dst_level, unsigned dst_z,
1077 enum pipe_format format)
1078 {
1079 /* Required before and after CB_RESOLVE. */
1080 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1081
1082 si_blitter_begin(sctx, SI_COLOR_RESOLVE |
1083 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1084 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1085 info->src.resource, info->src.box.z,
1086 ~0, sctx->custom_blend_resolve,
1087 format);
1088 si_blitter_end(sctx);
1089
1090 /* Flush caches for possible texturing. */
1091 si_make_CB_shader_coherent(sctx, 1, false);
1092 }
1093
1094 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1095 const struct pipe_blit_info *info)
1096 {
1097 struct si_context *sctx = (struct si_context*)ctx;
1098 struct si_texture *src = (struct si_texture*)info->src.resource;
1099 struct si_texture *dst = (struct si_texture*)info->dst.resource;
1100 MAYBE_UNUSED struct si_texture *stmp;
1101 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1102 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1103 enum pipe_format format = info->src.format;
1104 struct pipe_resource *tmp, templ;
1105 struct pipe_blit_info blit;
1106
1107 /* Check basic requirements for hw resolve. */
1108 if (!(info->src.resource->nr_samples > 1 &&
1109 info->dst.resource->nr_samples <= 1 &&
1110 !util_format_is_pure_integer(format) &&
1111 !util_format_is_depth_or_stencil(format) &&
1112 util_max_layer(info->src.resource, 0) == 0))
1113 return false;
1114
1115 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1116 * the format is R16G16. Use R16A16, which does work.
1117 */
1118 if (format == PIPE_FORMAT_R16G16_UNORM)
1119 format = PIPE_FORMAT_R16A16_UNORM;
1120 if (format == PIPE_FORMAT_R16G16_SNORM)
1121 format = PIPE_FORMAT_R16A16_SNORM;
1122
1123 /* Check the remaining requirements for hw resolve. */
1124 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1125 !info->scissor_enable &&
1126 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1127 util_is_format_compatible(util_format_description(info->src.format),
1128 util_format_description(info->dst.format)) &&
1129 dst_width == info->src.resource->width0 &&
1130 dst_height == info->src.resource->height0 &&
1131 info->dst.box.x == 0 &&
1132 info->dst.box.y == 0 &&
1133 info->dst.box.width == dst_width &&
1134 info->dst.box.height == dst_height &&
1135 info->dst.box.depth == 1 &&
1136 info->src.box.x == 0 &&
1137 info->src.box.y == 0 &&
1138 info->src.box.width == dst_width &&
1139 info->src.box.height == dst_height &&
1140 info->src.box.depth == 1 &&
1141 !dst->surface.is_linear &&
1142 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1143 /* Check the last constraint. */
1144 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1145 /* The next fast clear will switch to this mode to
1146 * get direct hw resolve next time if the mode is
1147 * different now.
1148 */
1149 src->last_msaa_resolve_target_micro_mode =
1150 dst->surface.micro_tile_mode;
1151 goto resolve_to_temp;
1152 }
1153
1154 /* Resolving into a surface with DCC is unsupported. Since
1155 * it's being overwritten anyway, clear it to uncompressed.
1156 * This is still the fastest codepath even with this clear.
1157 */
1158 if (vi_dcc_enabled(dst, info->dst.level)) {
1159 /* TODO: Implement per-level DCC clears for GFX9. */
1160 if (sctx->chip_class >= GFX9 &&
1161 info->dst.resource->last_level != 0)
1162 goto resolve_to_temp;
1163
1164 vi_dcc_clear_level(sctx, dst, info->dst.level,
1165 0xFFFFFFFF);
1166 dst->dirty_level_mask &= ~(1 << info->dst.level);
1167 }
1168
1169 /* Resolve directly from src to dst. */
1170 si_do_CB_resolve(sctx, info, info->dst.resource,
1171 info->dst.level, info->dst.box.z, format);
1172 return true;
1173 }
1174
1175 resolve_to_temp:
1176 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1177 * a temporary texture and blit.
1178 */
1179 memset(&templ, 0, sizeof(templ));
1180 templ.target = PIPE_TEXTURE_2D;
1181 templ.format = info->src.resource->format;
1182 templ.width0 = info->src.resource->width0;
1183 templ.height0 = info->src.resource->height0;
1184 templ.depth0 = 1;
1185 templ.array_size = 1;
1186 templ.usage = PIPE_USAGE_DEFAULT;
1187 templ.flags = SI_RESOURCE_FLAG_FORCE_TILING |
1188 SI_RESOURCE_FLAG_DISABLE_DCC;
1189
1190 /* The src and dst microtile modes must be the same. */
1191 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1192 templ.bind = PIPE_BIND_SCANOUT;
1193 else
1194 templ.bind = 0;
1195
1196 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1197 if (!tmp)
1198 return false;
1199 stmp = (struct si_texture*)tmp;
1200
1201 assert(!stmp->surface.is_linear);
1202 assert(src->surface.micro_tile_mode == stmp->surface.micro_tile_mode);
1203
1204 /* resolve */
1205 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1206
1207 /* blit */
1208 blit = *info;
1209 blit.src.resource = tmp;
1210 blit.src.box.z = 0;
1211
1212 si_blitter_begin(sctx, SI_BLIT |
1213 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1214 util_blitter_blit(sctx->blitter, &blit);
1215 si_blitter_end(sctx);
1216
1217 pipe_resource_reference(&tmp, NULL);
1218 return true;
1219 }
1220
1221 static void si_blit(struct pipe_context *ctx,
1222 const struct pipe_blit_info *info)
1223 {
1224 struct si_context *sctx = (struct si_context*)ctx;
1225 struct si_texture *dst = (struct si_texture *)info->dst.resource;
1226
1227 if (do_hardware_msaa_resolve(ctx, info)) {
1228 return;
1229 }
1230
1231 /* Using SDMA for copying to a linear texture in GTT is much faster.
1232 * This improves DRI PRIME performance.
1233 *
1234 * resource_copy_region can't do this yet, because dma_copy calls it
1235 * on failure (recursion).
1236 */
1237 if (dst->surface.is_linear &&
1238 sctx->dma_copy &&
1239 util_can_blit_via_copy_region(info, false)) {
1240 sctx->dma_copy(ctx, info->dst.resource, info->dst.level,
1241 info->dst.box.x, info->dst.box.y,
1242 info->dst.box.z,
1243 info->src.resource, info->src.level,
1244 &info->src.box);
1245 return;
1246 }
1247
1248 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1249
1250 /* The driver doesn't decompress resources automatically while
1251 * u_blitter is rendering. */
1252 vi_disable_dcc_if_incompatible_format(sctx, info->src.resource,
1253 info->src.level,
1254 info->src.format);
1255 vi_disable_dcc_if_incompatible_format(sctx, info->dst.resource,
1256 info->dst.level,
1257 info->dst.format);
1258 si_decompress_subresource(ctx, info->src.resource, info->mask,
1259 info->src.level,
1260 info->src.box.z,
1261 info->src.box.z + info->src.box.depth - 1);
1262
1263 if (sctx->screen->debug_flags & DBG(FORCE_DMA) &&
1264 util_try_blit_via_copy_region(ctx, info))
1265 return;
1266
1267 si_blitter_begin(sctx, SI_BLIT |
1268 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1269 util_blitter_blit(sctx->blitter, info);
1270 si_blitter_end(sctx);
1271 }
1272
1273 static boolean si_generate_mipmap(struct pipe_context *ctx,
1274 struct pipe_resource *tex,
1275 enum pipe_format format,
1276 unsigned base_level, unsigned last_level,
1277 unsigned first_layer, unsigned last_layer)
1278 {
1279 struct si_context *sctx = (struct si_context*)ctx;
1280 struct si_texture *stex = (struct si_texture *)tex;
1281
1282 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1283 return false;
1284
1285 /* The driver doesn't decompress resources automatically while
1286 * u_blitter is rendering. */
1287 vi_disable_dcc_if_incompatible_format(sctx, tex, base_level,
1288 format);
1289 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1290 base_level, first_layer, last_layer);
1291
1292 /* Clear dirty_level_mask for the levels that will be overwritten. */
1293 assert(base_level < last_level);
1294 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1295 last_level - base_level);
1296
1297 sctx->generate_mipmap_for_depth = stex->is_depth;
1298
1299 si_blitter_begin(sctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1300 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1301 base_level, last_level,
1302 first_layer, last_layer);
1303 si_blitter_end(sctx);
1304
1305 sctx->generate_mipmap_for_depth = false;
1306 return true;
1307 }
1308
1309 static void si_flush_resource(struct pipe_context *ctx,
1310 struct pipe_resource *res)
1311 {
1312 struct si_context *sctx = (struct si_context*)ctx;
1313 struct si_texture *tex = (struct si_texture*)res;
1314
1315 assert(res->target != PIPE_BUFFER);
1316 assert(!tex->dcc_separate_buffer || tex->dcc_gather_statistics);
1317
1318 /* st/dri calls flush twice per frame (not a bug), this prevents double
1319 * decompression. */
1320 if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
1321 return;
1322
1323 if (!tex->is_depth && (tex->cmask.size || tex->dcc_offset)) {
1324 si_blit_decompress_color(sctx, tex, 0, res->last_level,
1325 0, util_max_layer(res, 0),
1326 tex->dcc_separate_buffer != NULL);
1327 }
1328
1329 /* Always do the analysis even if DCC is disabled at the moment. */
1330 if (tex->dcc_gather_statistics && tex->separate_dcc_dirty) {
1331 tex->separate_dcc_dirty = false;
1332 vi_separate_dcc_process_and_reset_stats(ctx, tex);
1333 }
1334 }
1335
1336 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
1337 {
1338 if (!tex->dcc_offset)
1339 return;
1340
1341 si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level,
1342 0, util_max_layer(&tex->buffer.b.b, 0),
1343 true);
1344 }
1345
1346 void si_init_blit_functions(struct si_context *sctx)
1347 {
1348 sctx->b.resource_copy_region = si_resource_copy_region;
1349 sctx->b.blit = si_blit;
1350 sctx->b.flush_resource = si_flush_resource;
1351 sctx->b.generate_mipmap = si_generate_mipmap;
1352 }