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ac/surface: add radeon_surf::has_stencil for convenience
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_log.h"
28 #include "util/u_surface.h"
29
30 enum si_blitter_op /* bitmask */
31 {
32 SI_SAVE_TEXTURES = 1,
33 SI_SAVE_FRAMEBUFFER = 2,
34 SI_SAVE_FRAGMENT_STATE = 4,
35 SI_DISABLE_RENDER_COND = 8,
36
37 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
38
39 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
40
41 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
42 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
43
44 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
45 SI_SAVE_FRAGMENT_STATE,
46
47 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
48 SI_DISABLE_RENDER_COND,
49
50 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
51 };
52
53 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
54 {
55 struct si_context *sctx = (struct si_context *)ctx;
56
57 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
58 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
59 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
60 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
61 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
62 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
63 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
64 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
65 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
66
67 if (op & SI_SAVE_FRAGMENT_STATE) {
68 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
69 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
70 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
71 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
72 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
73 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
74 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
75 }
76
77 if (op & SI_SAVE_FRAMEBUFFER)
78 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
79
80 if (op & SI_SAVE_TEXTURES) {
81 util_blitter_save_fragment_sampler_states(
82 sctx->blitter, 2,
83 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
84
85 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
86 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
87 }
88
89 if (op & SI_DISABLE_RENDER_COND)
90 sctx->b.render_cond_force_off = true;
91 }
92
93 static void si_blitter_end(struct pipe_context *ctx)
94 {
95 struct si_context *sctx = (struct si_context *)ctx;
96
97 sctx->b.render_cond_force_off = false;
98 }
99
100 static unsigned u_max_sample(struct pipe_resource *r)
101 {
102 return r->nr_samples ? r->nr_samples - 1 : 0;
103 }
104
105 static unsigned
106 si_blit_dbcb_copy(struct si_context *sctx,
107 struct r600_texture *src,
108 struct r600_texture *dst,
109 unsigned planes, unsigned level_mask,
110 unsigned first_layer, unsigned last_layer,
111 unsigned first_sample, unsigned last_sample)
112 {
113 struct pipe_surface surf_tmpl = {{0}};
114 unsigned layer, sample, checked_last_layer, max_layer;
115 unsigned fully_copied_levels = 0;
116
117 if (planes & PIPE_MASK_Z)
118 sctx->dbcb_depth_copy_enabled = true;
119 if (planes & PIPE_MASK_S)
120 sctx->dbcb_stencil_copy_enabled = true;
121 si_mark_atom_dirty(sctx, &sctx->db_render_state);
122
123 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
124
125 sctx->decompression_enabled = true;
126
127 while (level_mask) {
128 unsigned level = u_bit_scan(&level_mask);
129
130 /* The smaller the mipmap level, the less layers there are
131 * as far as 3D textures are concerned. */
132 max_layer = util_max_layer(&src->resource.b.b, level);
133 checked_last_layer = MIN2(last_layer, max_layer);
134
135 surf_tmpl.u.tex.level = level;
136
137 for (layer = first_layer; layer <= checked_last_layer; layer++) {
138 struct pipe_surface *zsurf, *cbsurf;
139
140 surf_tmpl.format = src->resource.b.b.format;
141 surf_tmpl.u.tex.first_layer = layer;
142 surf_tmpl.u.tex.last_layer = layer;
143
144 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
145
146 surf_tmpl.format = dst->resource.b.b.format;
147 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
148
149 for (sample = first_sample; sample <= last_sample; sample++) {
150 if (sample != sctx->dbcb_copy_sample) {
151 sctx->dbcb_copy_sample = sample;
152 si_mark_atom_dirty(sctx, &sctx->db_render_state);
153 }
154
155 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
156 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
157 sctx->custom_dsa_flush, 1.0f);
158 si_blitter_end(&sctx->b.b);
159 }
160
161 pipe_surface_reference(&zsurf, NULL);
162 pipe_surface_reference(&cbsurf, NULL);
163 }
164
165 if (first_layer == 0 && last_layer >= max_layer &&
166 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
167 fully_copied_levels |= 1u << level;
168 }
169
170 sctx->decompression_enabled = false;
171 sctx->dbcb_depth_copy_enabled = false;
172 sctx->dbcb_stencil_copy_enabled = false;
173 si_mark_atom_dirty(sctx, &sctx->db_render_state);
174
175 return fully_copied_levels;
176 }
177
178 static void si_blit_decompress_depth(struct pipe_context *ctx,
179 struct r600_texture *texture,
180 struct r600_texture *staging,
181 unsigned first_level, unsigned last_level,
182 unsigned first_layer, unsigned last_layer,
183 unsigned first_sample, unsigned last_sample)
184 {
185 const struct util_format_description *desc;
186 unsigned planes = 0;
187
188 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
189
190 desc = util_format_description(staging->resource.b.b.format);
191
192 if (util_format_has_depth(desc))
193 planes |= PIPE_MASK_Z;
194 if (util_format_has_stencil(desc))
195 planes |= PIPE_MASK_S;
196
197 si_blit_dbcb_copy(
198 (struct si_context *)ctx, texture, staging, planes,
199 u_bit_consecutive(first_level, last_level - first_level + 1),
200 first_layer, last_layer, first_sample, last_sample);
201 }
202
203 /* Helper function for si_blit_decompress_zs_in_place.
204 */
205 static void
206 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
207 struct r600_texture *texture,
208 unsigned planes, unsigned level_mask,
209 unsigned first_layer, unsigned last_layer)
210 {
211 struct pipe_surface *zsurf, surf_tmpl = {{0}};
212 unsigned layer, max_layer, checked_last_layer;
213 unsigned fully_decompressed_mask = 0;
214
215 if (!level_mask)
216 return;
217
218 if (planes & PIPE_MASK_S)
219 sctx->db_flush_stencil_inplace = true;
220 if (planes & PIPE_MASK_Z)
221 sctx->db_flush_depth_inplace = true;
222 si_mark_atom_dirty(sctx, &sctx->db_render_state);
223
224 surf_tmpl.format = texture->resource.b.b.format;
225
226 sctx->decompression_enabled = true;
227
228 while (level_mask) {
229 unsigned level = u_bit_scan(&level_mask);
230
231 surf_tmpl.u.tex.level = level;
232
233 /* The smaller the mipmap level, the less layers there are
234 * as far as 3D textures are concerned. */
235 max_layer = util_max_layer(&texture->resource.b.b, level);
236 checked_last_layer = MIN2(last_layer, max_layer);
237
238 for (layer = first_layer; layer <= checked_last_layer; layer++) {
239 surf_tmpl.u.tex.first_layer = layer;
240 surf_tmpl.u.tex.last_layer = layer;
241
242 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
243
244 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
245 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
246 sctx->custom_dsa_flush,
247 1.0f);
248 si_blitter_end(&sctx->b.b);
249
250 pipe_surface_reference(&zsurf, NULL);
251 }
252
253 /* The texture will always be dirty if some layers aren't flushed.
254 * I don't think this case occurs often though. */
255 if (first_layer == 0 && last_layer >= max_layer) {
256 fully_decompressed_mask |= 1u << level;
257 }
258 }
259
260 if (planes & PIPE_MASK_Z)
261 texture->dirty_level_mask &= ~fully_decompressed_mask;
262 if (planes & PIPE_MASK_S)
263 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
264
265 sctx->decompression_enabled = false;
266 sctx->db_flush_depth_inplace = false;
267 sctx->db_flush_stencil_inplace = false;
268 si_mark_atom_dirty(sctx, &sctx->db_render_state);
269 }
270
271 /* Helper function of si_flush_depth_texture: decompress the given levels
272 * of Z and/or S planes in place.
273 */
274 static void
275 si_blit_decompress_zs_in_place(struct si_context *sctx,
276 struct r600_texture *texture,
277 unsigned levels_z, unsigned levels_s,
278 unsigned first_layer, unsigned last_layer)
279 {
280 unsigned both = levels_z & levels_s;
281
282 /* First, do combined Z & S decompresses for levels that need it. */
283 if (both) {
284 si_blit_decompress_zs_planes_in_place(
285 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
286 both,
287 first_layer, last_layer);
288 levels_z &= ~both;
289 levels_s &= ~both;
290 }
291
292 /* Now do separate Z and S decompresses. */
293 if (levels_z) {
294 si_blit_decompress_zs_planes_in_place(
295 sctx, texture, PIPE_MASK_Z,
296 levels_z,
297 first_layer, last_layer);
298 }
299
300 if (levels_s) {
301 si_blit_decompress_zs_planes_in_place(
302 sctx, texture, PIPE_MASK_S,
303 levels_s,
304 first_layer, last_layer);
305 }
306 }
307
308 static void
309 si_decompress_depth(struct si_context *sctx,
310 struct r600_texture *tex,
311 unsigned required_planes,
312 unsigned first_level, unsigned last_level,
313 unsigned first_layer, unsigned last_layer)
314 {
315 unsigned inplace_planes = 0;
316 unsigned copy_planes = 0;
317 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
318 unsigned levels_z = 0;
319 unsigned levels_s = 0;
320
321 if (required_planes & PIPE_MASK_Z) {
322 levels_z = level_mask & tex->dirty_level_mask;
323
324 if (levels_z) {
325 if (r600_can_sample_zs(tex, false))
326 inplace_planes |= PIPE_MASK_Z;
327 else
328 copy_planes |= PIPE_MASK_Z;
329 }
330 }
331 if (required_planes & PIPE_MASK_S) {
332 levels_s = level_mask & tex->stencil_dirty_level_mask;
333
334 if (levels_s) {
335 if (r600_can_sample_zs(tex, true))
336 inplace_planes |= PIPE_MASK_S;
337 else
338 copy_planes |= PIPE_MASK_S;
339 }
340 }
341
342 if (unlikely(sctx->b.log))
343 u_log_printf(sctx->b.log,
344 "\n------------------------------------------------\n"
345 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
346 first_level, last_level, levels_z, levels_s);
347
348 /* We may have to allocate the flushed texture here when called from
349 * si_decompress_subresource.
350 */
351 if (copy_planes &&
352 (tex->flushed_depth_texture ||
353 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
354 struct r600_texture *dst = tex->flushed_depth_texture;
355 unsigned fully_copied_levels;
356 unsigned levels = 0;
357
358 assert(tex->flushed_depth_texture);
359
360 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
361 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
362
363 if (copy_planes & PIPE_MASK_Z) {
364 levels |= levels_z;
365 levels_z = 0;
366 }
367 if (copy_planes & PIPE_MASK_S) {
368 levels |= levels_s;
369 levels_s = 0;
370 }
371
372 fully_copied_levels = si_blit_dbcb_copy(
373 sctx, tex, dst, copy_planes, levels,
374 first_layer, last_layer,
375 0, u_max_sample(&tex->resource.b.b));
376
377 if (copy_planes & PIPE_MASK_Z)
378 tex->dirty_level_mask &= ~fully_copied_levels;
379 if (copy_planes & PIPE_MASK_S)
380 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
381 }
382
383 if (inplace_planes) {
384 bool has_htile = r600_htile_enabled(tex, first_level);
385 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
386
387 /* Don't decompress if there is no HTILE or when HTILE is
388 * TC-compatible. */
389 if (has_htile && !tc_compat_htile) {
390 si_blit_decompress_zs_in_place(
391 sctx, tex,
392 levels_z, levels_s,
393 first_layer, last_layer);
394 } else {
395 /* This is only a cache flush.
396 *
397 * Only clear the mask that we are flushing, because
398 * si_make_DB_shader_coherent() treats different levels
399 * and depth and stencil differently.
400 */
401 if (inplace_planes & PIPE_MASK_Z)
402 tex->dirty_level_mask &= ~levels_z;
403 if (inplace_planes & PIPE_MASK_S)
404 tex->stencil_dirty_level_mask &= ~levels_s;
405 }
406
407 /* Only in-place decompression needs to flush DB caches, or
408 * when we don't decompress but TC-compatible planes are dirty.
409 */
410 si_make_DB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
411 inplace_planes & PIPE_MASK_S,
412 tc_compat_htile);
413 }
414 /* set_framebuffer_state takes care of coherency for single-sample.
415 * The DB->CB copy uses CB for the final writes.
416 */
417 if (copy_planes && tex->resource.b.b.nr_samples > 1)
418 si_make_CB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
419 false);
420 }
421
422 static void
423 si_decompress_sampler_depth_textures(struct si_context *sctx,
424 struct si_textures_info *textures)
425 {
426 unsigned i;
427 unsigned mask = textures->needs_depth_decompress_mask;
428
429 while (mask) {
430 struct pipe_sampler_view *view;
431 struct si_sampler_view *sview;
432 struct r600_texture *tex;
433
434 i = u_bit_scan(&mask);
435
436 view = textures->views.views[i];
437 assert(view);
438 sview = (struct si_sampler_view*)view;
439
440 tex = (struct r600_texture *)view->texture;
441 assert(tex->db_compatible);
442
443 si_decompress_depth(sctx, tex,
444 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
445 view->u.tex.first_level, view->u.tex.last_level,
446 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
447 }
448 }
449
450 static void si_blit_decompress_color(struct pipe_context *ctx,
451 struct r600_texture *rtex,
452 unsigned first_level, unsigned last_level,
453 unsigned first_layer, unsigned last_layer,
454 bool need_dcc_decompress)
455 {
456 struct si_context *sctx = (struct si_context *)ctx;
457 void* custom_blend;
458 unsigned layer, checked_last_layer, max_layer;
459 unsigned level_mask =
460 u_bit_consecutive(first_level, last_level - first_level + 1);
461
462 if (!need_dcc_decompress)
463 level_mask &= rtex->dirty_level_mask;
464 if (!level_mask)
465 return;
466
467 if (unlikely(sctx->b.log))
468 u_log_printf(sctx->b.log,
469 "\n------------------------------------------------\n"
470 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
471 first_level, last_level, level_mask);
472
473 if (rtex->dcc_offset && need_dcc_decompress) {
474 custom_blend = sctx->custom_blend_dcc_decompress;
475
476 /* disable levels without DCC */
477 for (int i = first_level; i <= last_level; i++) {
478 if (!vi_dcc_enabled(rtex, i))
479 level_mask &= ~(1 << i);
480 }
481 } else if (rtex->fmask.size) {
482 custom_blend = sctx->custom_blend_fmask_decompress;
483 } else {
484 custom_blend = sctx->custom_blend_eliminate_fastclear;
485 }
486
487 sctx->decompression_enabled = true;
488
489 while (level_mask) {
490 unsigned level = u_bit_scan(&level_mask);
491
492 /* The smaller the mipmap level, the less layers there are
493 * as far as 3D textures are concerned. */
494 max_layer = util_max_layer(&rtex->resource.b.b, level);
495 checked_last_layer = MIN2(last_layer, max_layer);
496
497 for (layer = first_layer; layer <= checked_last_layer; layer++) {
498 struct pipe_surface *cbsurf, surf_tmpl;
499
500 surf_tmpl.format = rtex->resource.b.b.format;
501 surf_tmpl.u.tex.level = level;
502 surf_tmpl.u.tex.first_layer = layer;
503 surf_tmpl.u.tex.last_layer = layer;
504 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
505
506 /* Required before and after FMASK and DCC_DECOMPRESS. */
507 if (custom_blend == sctx->custom_blend_fmask_decompress ||
508 custom_blend == sctx->custom_blend_dcc_decompress)
509 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
510
511 si_blitter_begin(ctx, SI_DECOMPRESS);
512 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
513 si_blitter_end(ctx);
514
515 if (custom_blend == sctx->custom_blend_fmask_decompress ||
516 custom_blend == sctx->custom_blend_dcc_decompress)
517 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
518
519 pipe_surface_reference(&cbsurf, NULL);
520 }
521
522 /* The texture will always be dirty if some layers aren't flushed.
523 * I don't think this case occurs often though. */
524 if (first_layer == 0 && last_layer >= max_layer) {
525 rtex->dirty_level_mask &= ~(1 << level);
526 }
527 }
528
529 sctx->decompression_enabled = false;
530 si_make_CB_shader_coherent(sctx, rtex->resource.b.b.nr_samples,
531 vi_dcc_enabled(rtex, first_level));
532 }
533
534 static void
535 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
536 unsigned first_level, unsigned last_level)
537 {
538 /* CMASK or DCC can be discarded and we can still end up here. */
539 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
540 return;
541
542 si_blit_decompress_color(&sctx->b.b, tex, first_level, last_level, 0,
543 util_max_layer(&tex->resource.b.b, first_level),
544 false);
545 }
546
547 static void
548 si_decompress_sampler_color_textures(struct si_context *sctx,
549 struct si_textures_info *textures)
550 {
551 unsigned i;
552 unsigned mask = textures->needs_color_decompress_mask;
553
554 while (mask) {
555 struct pipe_sampler_view *view;
556 struct r600_texture *tex;
557
558 i = u_bit_scan(&mask);
559
560 view = textures->views.views[i];
561 assert(view);
562
563 tex = (struct r600_texture *)view->texture;
564
565 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
566 view->u.tex.last_level);
567 }
568 }
569
570 static void
571 si_decompress_image_color_textures(struct si_context *sctx,
572 struct si_images_info *images)
573 {
574 unsigned i;
575 unsigned mask = images->needs_color_decompress_mask;
576
577 while (mask) {
578 const struct pipe_image_view *view;
579 struct r600_texture *tex;
580
581 i = u_bit_scan(&mask);
582
583 view = &images->views[i];
584 assert(view->resource->target != PIPE_BUFFER);
585
586 tex = (struct r600_texture *)view->resource;
587
588 si_decompress_color_texture(sctx, tex, view->u.tex.level,
589 view->u.tex.level);
590 }
591 }
592
593 static void si_check_render_feedback_texture(struct si_context *sctx,
594 struct r600_texture *tex,
595 unsigned first_level,
596 unsigned last_level,
597 unsigned first_layer,
598 unsigned last_layer)
599 {
600 bool render_feedback = false;
601
602 if (!tex->dcc_offset)
603 return;
604
605 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
606 struct r600_surface * surf;
607
608 if (!sctx->framebuffer.state.cbufs[j])
609 continue;
610
611 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
612
613 if (tex == (struct r600_texture *)surf->base.texture &&
614 surf->base.u.tex.level >= first_level &&
615 surf->base.u.tex.level <= last_level &&
616 surf->base.u.tex.first_layer <= last_layer &&
617 surf->base.u.tex.last_layer >= first_layer) {
618 render_feedback = true;
619 break;
620 }
621 }
622
623 if (render_feedback)
624 r600_texture_disable_dcc(&sctx->b, tex);
625 }
626
627 static void si_check_render_feedback_textures(struct si_context *sctx,
628 struct si_textures_info *textures)
629 {
630 uint32_t mask = textures->views.enabled_mask;
631
632 while (mask) {
633 const struct pipe_sampler_view *view;
634 struct r600_texture *tex;
635
636 unsigned i = u_bit_scan(&mask);
637
638 view = textures->views.views[i];
639 if(view->texture->target == PIPE_BUFFER)
640 continue;
641
642 tex = (struct r600_texture *)view->texture;
643
644 si_check_render_feedback_texture(sctx, tex,
645 view->u.tex.first_level,
646 view->u.tex.last_level,
647 view->u.tex.first_layer,
648 view->u.tex.last_layer);
649 }
650 }
651
652 static void si_check_render_feedback_images(struct si_context *sctx,
653 struct si_images_info *images)
654 {
655 uint32_t mask = images->enabled_mask;
656
657 while (mask) {
658 const struct pipe_image_view *view;
659 struct r600_texture *tex;
660
661 unsigned i = u_bit_scan(&mask);
662
663 view = &images->views[i];
664 if (view->resource->target == PIPE_BUFFER)
665 continue;
666
667 tex = (struct r600_texture *)view->resource;
668
669 si_check_render_feedback_texture(sctx, tex,
670 view->u.tex.level,
671 view->u.tex.level,
672 view->u.tex.first_layer,
673 view->u.tex.last_layer);
674 }
675 }
676
677 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
678 {
679 util_dynarray_foreach(&sctx->resident_tex_handles,
680 struct si_texture_handle *, tex_handle) {
681 struct pipe_sampler_view *view;
682 struct r600_texture *tex;
683
684 view = (*tex_handle)->view;
685 if (view->texture->target == PIPE_BUFFER)
686 continue;
687
688 tex = (struct r600_texture *)view->texture;
689
690 si_check_render_feedback_texture(sctx, tex,
691 view->u.tex.first_level,
692 view->u.tex.last_level,
693 view->u.tex.first_layer,
694 view->u.tex.last_layer);
695 }
696 }
697
698 static void si_check_render_feedback_resident_images(struct si_context *sctx)
699 {
700 util_dynarray_foreach(&sctx->resident_img_handles,
701 struct si_image_handle *, img_handle) {
702 struct pipe_image_view *view;
703 struct r600_texture *tex;
704
705 view = &(*img_handle)->view;
706 if (view->resource->target == PIPE_BUFFER)
707 continue;
708
709 tex = (struct r600_texture *)view->resource;
710
711 si_check_render_feedback_texture(sctx, tex,
712 view->u.tex.level,
713 view->u.tex.level,
714 view->u.tex.first_layer,
715 view->u.tex.last_layer);
716 }
717 }
718
719 static void si_check_render_feedback(struct si_context *sctx)
720 {
721
722 if (!sctx->need_check_render_feedback)
723 return;
724
725 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
726 si_check_render_feedback_images(sctx, &sctx->images[i]);
727 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
728 }
729
730 si_check_render_feedback_resident_images(sctx);
731 si_check_render_feedback_resident_textures(sctx);
732
733 sctx->need_check_render_feedback = false;
734 }
735
736 static void si_decompress_resident_textures(struct si_context *sctx)
737 {
738 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
739 struct si_texture_handle *, tex_handle) {
740 struct pipe_sampler_view *view = (*tex_handle)->view;
741 struct r600_texture *tex = (struct r600_texture *)view->texture;
742
743 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
744 view->u.tex.last_level);
745 }
746
747 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
748 struct si_texture_handle *, tex_handle) {
749 struct pipe_sampler_view *view = (*tex_handle)->view;
750 struct si_sampler_view *sview = (struct si_sampler_view *)view;
751 struct r600_texture *tex = (struct r600_texture *)view->texture;
752
753 si_decompress_depth(sctx, tex,
754 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
755 view->u.tex.first_level, view->u.tex.last_level,
756 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
757 }
758 }
759
760 static void si_decompress_resident_images(struct si_context *sctx)
761 {
762 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
763 struct si_image_handle *, img_handle) {
764 struct pipe_image_view *view = &(*img_handle)->view;
765 struct r600_texture *tex = (struct r600_texture *)view->resource;
766
767 si_decompress_color_texture(sctx, tex, view->u.tex.level,
768 view->u.tex.level);
769 }
770 }
771
772 static void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
773 {
774 unsigned compressed_colortex_counter, mask;
775
776 if (sctx->blitter->running)
777 return;
778
779 /* Update the compressed_colortex_mask if necessary. */
780 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
781 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
782 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
783 si_update_needs_color_decompress_masks(sctx);
784 }
785
786 /* Decompress color & depth textures if needed. */
787 mask = sctx->shader_needs_decompress_mask & shader_mask;
788 while (mask) {
789 unsigned i = u_bit_scan(&mask);
790
791 if (sctx->samplers[i].needs_depth_decompress_mask) {
792 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
793 }
794 if (sctx->samplers[i].needs_color_decompress_mask) {
795 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
796 }
797 if (sctx->images[i].needs_color_decompress_mask) {
798 si_decompress_image_color_textures(sctx, &sctx->images[i]);
799 }
800 }
801
802 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
803 if (sctx->uses_bindless_samplers)
804 si_decompress_resident_textures(sctx);
805 if (sctx->uses_bindless_images)
806 si_decompress_resident_images(sctx);
807 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
808 if (sctx->cs_shader_state.program->uses_bindless_samplers)
809 si_decompress_resident_textures(sctx);
810 if (sctx->cs_shader_state.program->uses_bindless_images)
811 si_decompress_resident_images(sctx);
812 }
813
814 si_check_render_feedback(sctx);
815 }
816
817 void si_decompress_graphics_textures(struct si_context *sctx)
818 {
819 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
820 }
821
822 void si_decompress_compute_textures(struct si_context *sctx)
823 {
824 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
825 }
826
827 static void si_clear(struct pipe_context *ctx, unsigned buffers,
828 const union pipe_color_union *color,
829 double depth, unsigned stencil)
830 {
831 struct si_context *sctx = (struct si_context *)ctx;
832 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
833 struct pipe_surface *zsbuf = fb->zsbuf;
834 struct r600_texture *zstex =
835 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
836
837 if (buffers & PIPE_CLEAR_COLOR) {
838 evergreen_do_fast_color_clear(&sctx->b, fb,
839 &sctx->framebuffer.atom, &buffers,
840 &sctx->framebuffer.dirty_cbufs,
841 color);
842 if (!buffers)
843 return; /* all buffers have been fast cleared */
844 }
845
846 if (buffers & PIPE_CLEAR_COLOR) {
847 int i;
848
849 /* These buffers cannot use fast clear, make sure to disable expansion. */
850 for (i = 0; i < fb->nr_cbufs; i++) {
851 struct r600_texture *tex;
852
853 /* If not clearing this buffer, skip. */
854 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
855 continue;
856
857 if (!fb->cbufs[i])
858 continue;
859
860 tex = (struct r600_texture *)fb->cbufs[i]->texture;
861 if (tex->fmask.size == 0)
862 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
863 }
864 }
865
866 if (zstex &&
867 r600_htile_enabled(zstex, zsbuf->u.tex.level) &&
868 zsbuf->u.tex.first_layer == 0 &&
869 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
870 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
871 if (buffers & PIPE_CLEAR_DEPTH &&
872 (!zstex->tc_compatible_htile ||
873 depth == 0 || depth == 1)) {
874 /* Need to disable EXPCLEAR temporarily if clearing
875 * to a new value. */
876 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
877 sctx->db_depth_disable_expclear = true;
878 }
879
880 zstex->depth_clear_value = depth;
881 sctx->framebuffer.dirty_zsbuf = true;
882 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
883 sctx->db_depth_clear = true;
884 si_mark_atom_dirty(sctx, &sctx->db_render_state);
885 }
886
887 /* TC-compatible HTILE only supports stencil clears to 0. */
888 if (buffers & PIPE_CLEAR_STENCIL &&
889 (!zstex->tc_compatible_htile || stencil == 0)) {
890 stencil &= 0xff;
891
892 /* Need to disable EXPCLEAR temporarily if clearing
893 * to a new value. */
894 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
895 sctx->db_stencil_disable_expclear = true;
896 }
897
898 zstex->stencil_clear_value = stencil;
899 sctx->framebuffer.dirty_zsbuf = true;
900 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
901 sctx->db_stencil_clear = true;
902 si_mark_atom_dirty(sctx, &sctx->db_render_state);
903 }
904 }
905
906 si_blitter_begin(ctx, SI_CLEAR);
907 util_blitter_clear(sctx->blitter, fb->width, fb->height,
908 util_framebuffer_get_num_layers(fb),
909 buffers, color, depth, stencil);
910 si_blitter_end(ctx);
911
912 if (sctx->db_depth_clear) {
913 sctx->db_depth_clear = false;
914 sctx->db_depth_disable_expclear = false;
915 zstex->depth_cleared = true;
916 si_mark_atom_dirty(sctx, &sctx->db_render_state);
917 }
918
919 if (sctx->db_stencil_clear) {
920 sctx->db_stencil_clear = false;
921 sctx->db_stencil_disable_expclear = false;
922 zstex->stencil_cleared = true;
923 si_mark_atom_dirty(sctx, &sctx->db_render_state);
924 }
925 }
926
927 static void si_clear_render_target(struct pipe_context *ctx,
928 struct pipe_surface *dst,
929 const union pipe_color_union *color,
930 unsigned dstx, unsigned dsty,
931 unsigned width, unsigned height,
932 bool render_condition_enabled)
933 {
934 struct si_context *sctx = (struct si_context *)ctx;
935
936 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
937 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
938 util_blitter_clear_render_target(sctx->blitter, dst, color,
939 dstx, dsty, width, height);
940 si_blitter_end(ctx);
941 }
942
943 static void si_clear_depth_stencil(struct pipe_context *ctx,
944 struct pipe_surface *dst,
945 unsigned clear_flags,
946 double depth,
947 unsigned stencil,
948 unsigned dstx, unsigned dsty,
949 unsigned width, unsigned height,
950 bool render_condition_enabled)
951 {
952 struct si_context *sctx = (struct si_context *)ctx;
953
954 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
955 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
956 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
957 dstx, dsty, width, height);
958 si_blitter_end(ctx);
959 }
960
961 /* Helper for decompressing a portion of a color or depth resource before
962 * blitting if any decompression is needed.
963 * The driver doesn't decompress resources automatically while u_blitter is
964 * rendering. */
965 static void si_decompress_subresource(struct pipe_context *ctx,
966 struct pipe_resource *tex,
967 unsigned planes, unsigned level,
968 unsigned first_layer, unsigned last_layer)
969 {
970 struct si_context *sctx = (struct si_context *)ctx;
971 struct r600_texture *rtex = (struct r600_texture*)tex;
972
973 if (rtex->db_compatible) {
974 planes &= PIPE_MASK_Z | PIPE_MASK_S;
975
976 if (!rtex->surface.has_stencil)
977 planes &= ~PIPE_MASK_S;
978
979 /* If we've rendered into the framebuffer and it's a blitting
980 * source, make sure the decompression pass is invoked
981 * by dirtying the framebuffer.
982 */
983 if (sctx->framebuffer.state.zsbuf &&
984 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
985 sctx->framebuffer.state.zsbuf->texture == tex)
986 si_update_fb_dirtiness_after_rendering(sctx);
987
988 si_decompress_depth(sctx, rtex, planes,
989 level, level,
990 first_layer, last_layer);
991 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
992 /* If we've rendered into the framebuffer and it's a blitting
993 * source, make sure the decompression pass is invoked
994 * by dirtying the framebuffer.
995 */
996 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
997 if (sctx->framebuffer.state.cbufs[i] &&
998 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
999 sctx->framebuffer.state.cbufs[i]->texture == tex) {
1000 si_update_fb_dirtiness_after_rendering(sctx);
1001 break;
1002 }
1003 }
1004
1005 si_blit_decompress_color(ctx, rtex, level, level,
1006 first_layer, last_layer, false);
1007 }
1008 }
1009
1010 struct texture_orig_info {
1011 unsigned format;
1012 unsigned width0;
1013 unsigned height0;
1014 unsigned npix_x;
1015 unsigned npix_y;
1016 unsigned npix0_x;
1017 unsigned npix0_y;
1018 };
1019
1020 void si_resource_copy_region(struct pipe_context *ctx,
1021 struct pipe_resource *dst,
1022 unsigned dst_level,
1023 unsigned dstx, unsigned dsty, unsigned dstz,
1024 struct pipe_resource *src,
1025 unsigned src_level,
1026 const struct pipe_box *src_box)
1027 {
1028 struct si_context *sctx = (struct si_context *)ctx;
1029 struct r600_texture *rsrc = (struct r600_texture*)src;
1030 struct pipe_surface *dst_view, dst_templ;
1031 struct pipe_sampler_view src_templ, *src_view;
1032 unsigned dst_width, dst_height, src_width0, src_height0;
1033 unsigned dst_width0, dst_height0, src_force_level = 0;
1034 struct pipe_box sbox, dstbox;
1035
1036 /* Handle buffers first. */
1037 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
1038 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
1039 return;
1040 }
1041
1042 assert(u_max_sample(dst) == u_max_sample(src));
1043
1044 /* The driver doesn't decompress resources automatically while
1045 * u_blitter is rendering. */
1046 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
1047 src_box->z, src_box->z + src_box->depth - 1);
1048
1049 dst_width = u_minify(dst->width0, dst_level);
1050 dst_height = u_minify(dst->height0, dst_level);
1051 dst_width0 = dst->width0;
1052 dst_height0 = dst->height0;
1053 src_width0 = src->width0;
1054 src_height0 = src->height0;
1055
1056 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
1057 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
1058
1059 if (util_format_is_compressed(src->format) ||
1060 util_format_is_compressed(dst->format)) {
1061 unsigned blocksize = rsrc->surface.bpe;
1062
1063 if (blocksize == 8)
1064 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
1065 else
1066 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
1067 dst_templ.format = src_templ.format;
1068
1069 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1070 dst_height = util_format_get_nblocksy(dst->format, dst_height);
1071 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1072 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
1073 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1074 src_height0 = util_format_get_nblocksy(src->format, src_height0);
1075
1076 dstx = util_format_get_nblocksx(dst->format, dstx);
1077 dsty = util_format_get_nblocksy(dst->format, dsty);
1078
1079 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1080 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
1081 sbox.z = src_box->z;
1082 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1083 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
1084 sbox.depth = src_box->depth;
1085 src_box = &sbox;
1086
1087 src_force_level = src_level;
1088 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
1089 if (util_format_is_subsampled_422(src->format)) {
1090 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1091 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1092
1093 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1094 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1095 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1096
1097 dstx = util_format_get_nblocksx(dst->format, dstx);
1098
1099 sbox = *src_box;
1100 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1101 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1102 src_box = &sbox;
1103 } else {
1104 unsigned blocksize = rsrc->surface.bpe;
1105
1106 switch (blocksize) {
1107 case 1:
1108 dst_templ.format = PIPE_FORMAT_R8_UNORM;
1109 src_templ.format = PIPE_FORMAT_R8_UNORM;
1110 break;
1111 case 2:
1112 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
1113 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
1114 break;
1115 case 4:
1116 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1117 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1118 break;
1119 case 8:
1120 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1121 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1122 break;
1123 case 16:
1124 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1125 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1126 break;
1127 default:
1128 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1129 util_format_short_name(src->format), blocksize);
1130 assert(0);
1131 }
1132 }
1133 }
1134
1135 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1136 * equivalent instead, which doesn't force DCC decompression.
1137 * Note that some chips avoid this issue by using SDMA.
1138 */
1139 if (util_format_is_snorm8(dst_templ.format)) {
1140 switch (dst_templ.format) {
1141 case PIPE_FORMAT_R8_SNORM:
1142 dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
1143 break;
1144 case PIPE_FORMAT_R8G8_SNORM:
1145 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
1146 break;
1147 case PIPE_FORMAT_R8G8B8X8_SNORM:
1148 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
1149 break;
1150 case PIPE_FORMAT_R8G8B8A8_SNORM:
1151 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1152 case PIPE_FORMAT_A8B8G8R8_SNORM:
1153 case PIPE_FORMAT_X8B8G8R8_SNORM:
1154 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
1155 break;
1156 case PIPE_FORMAT_A8_SNORM:
1157 dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
1158 break;
1159 case PIPE_FORMAT_L8_SNORM:
1160 dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
1161 break;
1162 case PIPE_FORMAT_L8A8_SNORM:
1163 dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
1164 break;
1165 case PIPE_FORMAT_I8_SNORM:
1166 dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
1167 break;
1168 default:; /* fall through */
1169 }
1170 }
1171
1172 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
1173 dst_templ.format);
1174 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
1175 src_templ.format);
1176
1177 /* Initialize the surface. */
1178 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
1179 dst_width0, dst_height0,
1180 dst_width, dst_height);
1181
1182 /* Initialize the sampler view. */
1183 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1184 src_width0, src_height0,
1185 src_force_level);
1186
1187 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1188 abs(src_box->depth), &dstbox);
1189
1190 /* Copy. */
1191 si_blitter_begin(ctx, SI_COPY);
1192 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1193 src_view, src_box, src_width0, src_height0,
1194 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1195 false);
1196 si_blitter_end(ctx);
1197
1198 pipe_surface_reference(&dst_view, NULL);
1199 pipe_sampler_view_reference(&src_view, NULL);
1200 }
1201
1202 static void si_do_CB_resolve(struct si_context *sctx,
1203 const struct pipe_blit_info *info,
1204 struct pipe_resource *dst,
1205 unsigned dst_level, unsigned dst_z,
1206 enum pipe_format format)
1207 {
1208 /* Required before and after CB_RESOLVE. */
1209 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1210
1211 si_blitter_begin(&sctx->b.b, SI_COLOR_RESOLVE |
1212 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1213 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1214 info->src.resource, info->src.box.z,
1215 ~0, sctx->custom_blend_resolve,
1216 format);
1217 si_blitter_end(&sctx->b.b);
1218
1219 /* Flush caches for possible texturing. */
1220 si_make_CB_shader_coherent(sctx, 1, false);
1221 }
1222
1223 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1224 const struct pipe_blit_info *info)
1225 {
1226 struct si_context *sctx = (struct si_context*)ctx;
1227 struct r600_texture *src = (struct r600_texture*)info->src.resource;
1228 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
1229 MAYBE_UNUSED struct r600_texture *rtmp;
1230 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1231 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1232 enum pipe_format format = info->src.format;
1233 struct pipe_resource *tmp, templ;
1234 struct pipe_blit_info blit;
1235
1236 /* Check basic requirements for hw resolve. */
1237 if (!(info->src.resource->nr_samples > 1 &&
1238 info->dst.resource->nr_samples <= 1 &&
1239 !util_format_is_pure_integer(format) &&
1240 !util_format_is_depth_or_stencil(format) &&
1241 util_max_layer(info->src.resource, 0) == 0))
1242 return false;
1243
1244 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1245 * the format is R16G16. Use R16A16, which does work.
1246 */
1247 if (format == PIPE_FORMAT_R16G16_UNORM)
1248 format = PIPE_FORMAT_R16A16_UNORM;
1249 if (format == PIPE_FORMAT_R16G16_SNORM)
1250 format = PIPE_FORMAT_R16A16_SNORM;
1251
1252 /* Check the remaining requirements for hw resolve. */
1253 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1254 !info->scissor_enable &&
1255 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1256 util_is_format_compatible(util_format_description(info->src.format),
1257 util_format_description(info->dst.format)) &&
1258 dst_width == info->src.resource->width0 &&
1259 dst_height == info->src.resource->height0 &&
1260 info->dst.box.x == 0 &&
1261 info->dst.box.y == 0 &&
1262 info->dst.box.width == dst_width &&
1263 info->dst.box.height == dst_height &&
1264 info->dst.box.depth == 1 &&
1265 info->src.box.x == 0 &&
1266 info->src.box.y == 0 &&
1267 info->src.box.width == dst_width &&
1268 info->src.box.height == dst_height &&
1269 info->src.box.depth == 1 &&
1270 !dst->surface.is_linear &&
1271 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1272 /* Check the last constraint. */
1273 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1274 /* The next fast clear will switch to this mode to
1275 * get direct hw resolve next time if the mode is
1276 * different now.
1277 */
1278 src->last_msaa_resolve_target_micro_mode =
1279 dst->surface.micro_tile_mode;
1280 goto resolve_to_temp;
1281 }
1282
1283 /* Resolving into a surface with DCC is unsupported. Since
1284 * it's being overwritten anyway, clear it to uncompressed.
1285 * This is still the fastest codepath even with this clear.
1286 */
1287 if (vi_dcc_enabled(dst, info->dst.level)) {
1288 /* TODO: Implement per-level DCC clears for GFX9. */
1289 if (sctx->b.chip_class >= GFX9 &&
1290 info->dst.resource->last_level != 0)
1291 goto resolve_to_temp;
1292
1293 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1294 0xFFFFFFFF);
1295 dst->dirty_level_mask &= ~(1 << info->dst.level);
1296 }
1297
1298 /* Resolve directly from src to dst. */
1299 si_do_CB_resolve(sctx, info, info->dst.resource,
1300 info->dst.level, info->dst.box.z, format);
1301 return true;
1302 }
1303
1304 resolve_to_temp:
1305 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1306 * a temporary texture and blit.
1307 */
1308 memset(&templ, 0, sizeof(templ));
1309 templ.target = PIPE_TEXTURE_2D;
1310 templ.format = info->src.resource->format;
1311 templ.width0 = info->src.resource->width0;
1312 templ.height0 = info->src.resource->height0;
1313 templ.depth0 = 1;
1314 templ.array_size = 1;
1315 templ.usage = PIPE_USAGE_DEFAULT;
1316 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1317 R600_RESOURCE_FLAG_DISABLE_DCC;
1318
1319 /* The src and dst microtile modes must be the same. */
1320 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1321 templ.bind = PIPE_BIND_SCANOUT;
1322 else
1323 templ.bind = 0;
1324
1325 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1326 if (!tmp)
1327 return false;
1328 rtmp = (struct r600_texture*)tmp;
1329
1330 assert(!rtmp->surface.is_linear);
1331 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1332
1333 /* resolve */
1334 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1335
1336 /* blit */
1337 blit = *info;
1338 blit.src.resource = tmp;
1339 blit.src.box.z = 0;
1340
1341 si_blitter_begin(ctx, SI_BLIT |
1342 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1343 util_blitter_blit(sctx->blitter, &blit);
1344 si_blitter_end(ctx);
1345
1346 pipe_resource_reference(&tmp, NULL);
1347 return true;
1348 }
1349
1350 static void si_blit(struct pipe_context *ctx,
1351 const struct pipe_blit_info *info)
1352 {
1353 struct si_context *sctx = (struct si_context*)ctx;
1354 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1355
1356 if (do_hardware_msaa_resolve(ctx, info)) {
1357 return;
1358 }
1359
1360 /* Using SDMA for copying to a linear texture in GTT is much faster.
1361 * This improves DRI PRIME performance.
1362 *
1363 * resource_copy_region can't do this yet, because dma_copy calls it
1364 * on failure (recursion).
1365 */
1366 if (rdst->surface.is_linear &&
1367 sctx->b.dma_copy &&
1368 util_can_blit_via_copy_region(info, false)) {
1369 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1370 info->dst.box.x, info->dst.box.y,
1371 info->dst.box.z,
1372 info->src.resource, info->src.level,
1373 &info->src.box);
1374 return;
1375 }
1376
1377 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1378
1379 /* The driver doesn't decompress resources automatically while
1380 * u_blitter is rendering. */
1381 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1382 info->src.level,
1383 info->src.format);
1384 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1385 info->dst.level,
1386 info->dst.format);
1387 si_decompress_subresource(ctx, info->src.resource, info->mask,
1388 info->src.level,
1389 info->src.box.z,
1390 info->src.box.z + info->src.box.depth - 1);
1391
1392 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1393 util_try_blit_via_copy_region(ctx, info))
1394 return;
1395
1396 si_blitter_begin(ctx, SI_BLIT |
1397 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1398 util_blitter_blit(sctx->blitter, info);
1399 si_blitter_end(ctx);
1400 }
1401
1402 static boolean si_generate_mipmap(struct pipe_context *ctx,
1403 struct pipe_resource *tex,
1404 enum pipe_format format,
1405 unsigned base_level, unsigned last_level,
1406 unsigned first_layer, unsigned last_layer)
1407 {
1408 struct si_context *sctx = (struct si_context*)ctx;
1409 struct r600_texture *rtex = (struct r600_texture *)tex;
1410
1411 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1412 return false;
1413
1414 /* The driver doesn't decompress resources automatically while
1415 * u_blitter is rendering. */
1416 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1417 format);
1418 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1419 base_level, first_layer, last_layer);
1420
1421 /* Clear dirty_level_mask for the levels that will be overwritten. */
1422 assert(base_level < last_level);
1423 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1424 last_level - base_level);
1425
1426 sctx->generate_mipmap_for_depth = rtex->is_depth;
1427
1428 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1429 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1430 base_level, last_level,
1431 first_layer, last_layer);
1432 si_blitter_end(ctx);
1433
1434 sctx->generate_mipmap_for_depth = false;
1435 return true;
1436 }
1437
1438 static void si_flush_resource(struct pipe_context *ctx,
1439 struct pipe_resource *res)
1440 {
1441 struct r600_texture *rtex = (struct r600_texture*)res;
1442
1443 assert(res->target != PIPE_BUFFER);
1444 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1445
1446 /* st/dri calls flush twice per frame (not a bug), this prevents double
1447 * decompression. */
1448 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1449 return;
1450
1451 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1452 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1453 0, util_max_layer(res, 0),
1454 rtex->dcc_separate_buffer != NULL);
1455 }
1456
1457 /* Always do the analysis even if DCC is disabled at the moment. */
1458 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1459 rtex->separate_dcc_dirty = false;
1460 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1461 }
1462 }
1463
1464 static void si_decompress_dcc(struct pipe_context *ctx,
1465 struct r600_texture *rtex)
1466 {
1467 if (!rtex->dcc_offset)
1468 return;
1469
1470 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1471 0, util_max_layer(&rtex->resource.b.b, 0),
1472 true);
1473 }
1474
1475 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1476 struct pipe_resource *dst,
1477 unsigned offset, unsigned size,
1478 const void *clear_value_ptr,
1479 int clear_value_size)
1480 {
1481 struct si_context *sctx = (struct si_context*)ctx;
1482 uint32_t dword_value;
1483 unsigned i;
1484
1485 assert(offset % clear_value_size == 0);
1486 assert(size % clear_value_size == 0);
1487
1488 if (clear_value_size > 4) {
1489 const uint32_t *u32 = clear_value_ptr;
1490 bool clear_dword_duplicated = true;
1491
1492 /* See if we can lower large fills to dword fills. */
1493 for (i = 1; i < clear_value_size / 4; i++)
1494 if (u32[0] != u32[i]) {
1495 clear_dword_duplicated = false;
1496 break;
1497 }
1498
1499 if (!clear_dword_duplicated) {
1500 /* Use transform feedback for 64-bit, 96-bit, and
1501 * 128-bit fills.
1502 */
1503 union pipe_color_union clear_value;
1504
1505 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1506 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1507 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1508 size, clear_value_size / 4,
1509 &clear_value);
1510 si_blitter_end(ctx);
1511 return;
1512 }
1513 }
1514
1515 /* Expand the clear value to a dword. */
1516 switch (clear_value_size) {
1517 case 1:
1518 dword_value = *(uint8_t*)clear_value_ptr;
1519 dword_value |= (dword_value << 8) |
1520 (dword_value << 16) |
1521 (dword_value << 24);
1522 break;
1523 case 2:
1524 dword_value = *(uint16_t*)clear_value_ptr;
1525 dword_value |= dword_value << 16;
1526 break;
1527 default:
1528 dword_value = *(uint32_t*)clear_value_ptr;
1529 }
1530
1531 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1532 R600_COHERENCY_SHADER);
1533 }
1534
1535 void si_init_blit_functions(struct si_context *sctx)
1536 {
1537 sctx->b.b.clear = si_clear;
1538 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1539 sctx->b.b.clear_render_target = si_clear_render_target;
1540 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1541 sctx->b.b.resource_copy_region = si_resource_copy_region;
1542 sctx->b.b.blit = si_blit;
1543 sctx->b.b.flush_resource = si_flush_resource;
1544 sctx->b.b.generate_mipmap = si_generate_mipmap;
1545 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1546 sctx->b.decompress_dcc = si_decompress_dcc;
1547 }