2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_compute.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_surface.h"
33 SI_COPY
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
34 SI_SAVE_FRAGMENT_STATE
| SI_DISABLE_RENDER_COND
,
36 SI_BLIT
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
37 SI_SAVE_FRAGMENT_STATE
,
39 SI_DECOMPRESS
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
|
40 SI_DISABLE_RENDER_COND
,
42 SI_COLOR_RESOLVE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
45 void si_blitter_begin(struct pipe_context
*ctx
, enum si_blitter_op op
)
47 struct si_context
*sctx
= (struct si_context
*)ctx
;
49 util_blitter_save_vertex_shader(sctx
->blitter
, sctx
->vs_shader
.cso
);
50 util_blitter_save_tessctrl_shader(sctx
->blitter
, sctx
->tcs_shader
.cso
);
51 util_blitter_save_tesseval_shader(sctx
->blitter
, sctx
->tes_shader
.cso
);
52 util_blitter_save_geometry_shader(sctx
->blitter
, sctx
->gs_shader
.cso
);
53 util_blitter_save_so_targets(sctx
->blitter
, sctx
->streamout
.num_targets
,
54 (struct pipe_stream_output_target
**)sctx
->streamout
.targets
);
55 util_blitter_save_rasterizer(sctx
->blitter
, sctx
->queued
.named
.rasterizer
);
57 if (op
& SI_SAVE_FRAGMENT_STATE
) {
58 util_blitter_save_blend(sctx
->blitter
, sctx
->queued
.named
.blend
);
59 util_blitter_save_depth_stencil_alpha(sctx
->blitter
, sctx
->queued
.named
.dsa
);
60 util_blitter_save_stencil_ref(sctx
->blitter
, &sctx
->stencil_ref
.state
);
61 util_blitter_save_fragment_shader(sctx
->blitter
, sctx
->ps_shader
.cso
);
62 util_blitter_save_sample_mask(sctx
->blitter
, sctx
->sample_mask
.sample_mask
);
63 util_blitter_save_scissor(sctx
->blitter
, &sctx
->scissors
.states
[0]);
66 if (op
& SI_SAVE_FRAMEBUFFER
)
67 util_blitter_save_framebuffer(sctx
->blitter
, &sctx
->framebuffer
.state
);
69 if (op
& SI_SAVE_TEXTURES
) {
70 util_blitter_save_fragment_sampler_states(
72 (void**)sctx
->samplers
[PIPE_SHADER_FRAGMENT
].sampler_states
);
74 util_blitter_save_fragment_sampler_views(sctx
->blitter
, 2,
75 sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
);
78 if (op
& SI_DISABLE_RENDER_COND
)
79 sctx
->b
.render_cond_force_off
= true;
82 void si_blitter_end(struct pipe_context
*ctx
)
84 struct si_context
*sctx
= (struct si_context
*)ctx
;
86 sctx
->b
.render_cond_force_off
= false;
88 /* Restore shader pointers because the VS blit shader changed all
89 * non-global VS user SGPRs. */
90 sctx
->shader_pointers_dirty
|= SI_DESCS_SHADER_MASK(VERTEX
);
91 sctx
->vertex_buffer_pointer_dirty
= sctx
->vb_descriptors_buffer
!= NULL
;
92 si_mark_atom_dirty(sctx
, &sctx
->shader_pointers
.atom
);
95 static unsigned u_max_sample(struct pipe_resource
*r
)
97 return r
->nr_samples
? r
->nr_samples
- 1 : 0;
101 si_blit_dbcb_copy(struct si_context
*sctx
,
102 struct r600_texture
*src
,
103 struct r600_texture
*dst
,
104 unsigned planes
, unsigned level_mask
,
105 unsigned first_layer
, unsigned last_layer
,
106 unsigned first_sample
, unsigned last_sample
)
108 struct pipe_surface surf_tmpl
= {{0}};
109 unsigned layer
, sample
, checked_last_layer
, max_layer
;
110 unsigned fully_copied_levels
= 0;
112 if (planes
& PIPE_MASK_Z
)
113 sctx
->dbcb_depth_copy_enabled
= true;
114 if (planes
& PIPE_MASK_S
)
115 sctx
->dbcb_stencil_copy_enabled
= true;
116 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
118 assert(sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
);
120 sctx
->decompression_enabled
= true;
123 unsigned level
= u_bit_scan(&level_mask
);
125 /* The smaller the mipmap level, the less layers there are
126 * as far as 3D textures are concerned. */
127 max_layer
= util_max_layer(&src
->resource
.b
.b
, level
);
128 checked_last_layer
= MIN2(last_layer
, max_layer
);
130 surf_tmpl
.u
.tex
.level
= level
;
132 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
133 struct pipe_surface
*zsurf
, *cbsurf
;
135 surf_tmpl
.format
= src
->resource
.b
.b
.format
;
136 surf_tmpl
.u
.tex
.first_layer
= layer
;
137 surf_tmpl
.u
.tex
.last_layer
= layer
;
139 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &src
->resource
.b
.b
, &surf_tmpl
);
141 surf_tmpl
.format
= dst
->resource
.b
.b
.format
;
142 cbsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &dst
->resource
.b
.b
, &surf_tmpl
);
144 for (sample
= first_sample
; sample
<= last_sample
; sample
++) {
145 if (sample
!= sctx
->dbcb_copy_sample
) {
146 sctx
->dbcb_copy_sample
= sample
;
147 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
150 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
151 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, cbsurf
, 1 << sample
,
152 sctx
->custom_dsa_flush
, 1.0f
);
153 si_blitter_end(&sctx
->b
.b
);
156 pipe_surface_reference(&zsurf
, NULL
);
157 pipe_surface_reference(&cbsurf
, NULL
);
160 if (first_layer
== 0 && last_layer
>= max_layer
&&
161 first_sample
== 0 && last_sample
>= u_max_sample(&src
->resource
.b
.b
))
162 fully_copied_levels
|= 1u << level
;
165 sctx
->decompression_enabled
= false;
166 sctx
->dbcb_depth_copy_enabled
= false;
167 sctx
->dbcb_stencil_copy_enabled
= false;
168 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
170 return fully_copied_levels
;
173 void si_blit_decompress_depth(struct pipe_context
*ctx
,
174 struct r600_texture
*texture
,
175 struct r600_texture
*staging
,
176 unsigned first_level
, unsigned last_level
,
177 unsigned first_layer
, unsigned last_layer
,
178 unsigned first_sample
, unsigned last_sample
)
180 const struct util_format_description
*desc
;
183 assert(staging
!= NULL
&& "use si_blit_decompress_zs_in_place instead");
185 desc
= util_format_description(staging
->resource
.b
.b
.format
);
187 if (util_format_has_depth(desc
))
188 planes
|= PIPE_MASK_Z
;
189 if (util_format_has_stencil(desc
))
190 planes
|= PIPE_MASK_S
;
193 (struct si_context
*)ctx
, texture
, staging
, planes
,
194 u_bit_consecutive(first_level
, last_level
- first_level
+ 1),
195 first_layer
, last_layer
, first_sample
, last_sample
);
198 /* Helper function for si_blit_decompress_zs_in_place.
201 si_blit_decompress_zs_planes_in_place(struct si_context
*sctx
,
202 struct r600_texture
*texture
,
203 unsigned planes
, unsigned level_mask
,
204 unsigned first_layer
, unsigned last_layer
)
206 struct pipe_surface
*zsurf
, surf_tmpl
= {{0}};
207 unsigned layer
, max_layer
, checked_last_layer
;
208 unsigned fully_decompressed_mask
= 0;
213 if (planes
& PIPE_MASK_S
)
214 sctx
->db_flush_stencil_inplace
= true;
215 if (planes
& PIPE_MASK_Z
)
216 sctx
->db_flush_depth_inplace
= true;
217 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
219 surf_tmpl
.format
= texture
->resource
.b
.b
.format
;
221 sctx
->decompression_enabled
= true;
224 unsigned level
= u_bit_scan(&level_mask
);
226 surf_tmpl
.u
.tex
.level
= level
;
228 /* The smaller the mipmap level, the less layers there are
229 * as far as 3D textures are concerned. */
230 max_layer
= util_max_layer(&texture
->resource
.b
.b
, level
);
231 checked_last_layer
= MIN2(last_layer
, max_layer
);
233 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
234 surf_tmpl
.u
.tex
.first_layer
= layer
;
235 surf_tmpl
.u
.tex
.last_layer
= layer
;
237 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &texture
->resource
.b
.b
, &surf_tmpl
);
239 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
240 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, NULL
, ~0,
241 sctx
->custom_dsa_flush
,
243 si_blitter_end(&sctx
->b
.b
);
245 pipe_surface_reference(&zsurf
, NULL
);
248 /* The texture will always be dirty if some layers aren't flushed.
249 * I don't think this case occurs often though. */
250 if (first_layer
== 0 && last_layer
>= max_layer
) {
251 fully_decompressed_mask
|= 1u << level
;
255 if (planes
& PIPE_MASK_Z
)
256 texture
->dirty_level_mask
&= ~fully_decompressed_mask
;
257 if (planes
& PIPE_MASK_S
)
258 texture
->stencil_dirty_level_mask
&= ~fully_decompressed_mask
;
260 sctx
->decompression_enabled
= false;
261 sctx
->db_flush_depth_inplace
= false;
262 sctx
->db_flush_stencil_inplace
= false;
263 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
266 /* Helper function of si_flush_depth_texture: decompress the given levels
267 * of Z and/or S planes in place.
270 si_blit_decompress_zs_in_place(struct si_context
*sctx
,
271 struct r600_texture
*texture
,
272 unsigned levels_z
, unsigned levels_s
,
273 unsigned first_layer
, unsigned last_layer
)
275 unsigned both
= levels_z
& levels_s
;
277 /* First, do combined Z & S decompresses for levels that need it. */
279 si_blit_decompress_zs_planes_in_place(
280 sctx
, texture
, PIPE_MASK_Z
| PIPE_MASK_S
,
282 first_layer
, last_layer
);
287 /* Now do separate Z and S decompresses. */
289 si_blit_decompress_zs_planes_in_place(
290 sctx
, texture
, PIPE_MASK_Z
,
292 first_layer
, last_layer
);
296 si_blit_decompress_zs_planes_in_place(
297 sctx
, texture
, PIPE_MASK_S
,
299 first_layer
, last_layer
);
304 si_decompress_depth(struct si_context
*sctx
,
305 struct r600_texture
*tex
,
306 unsigned required_planes
,
307 unsigned first_level
, unsigned last_level
,
308 unsigned first_layer
, unsigned last_layer
)
310 unsigned inplace_planes
= 0;
311 unsigned copy_planes
= 0;
312 unsigned level_mask
= u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
313 unsigned levels_z
= 0;
314 unsigned levels_s
= 0;
316 if (required_planes
& PIPE_MASK_Z
) {
317 levels_z
= level_mask
& tex
->dirty_level_mask
;
320 if (si_can_sample_zs(tex
, false))
321 inplace_planes
|= PIPE_MASK_Z
;
323 copy_planes
|= PIPE_MASK_Z
;
326 if (required_planes
& PIPE_MASK_S
) {
327 levels_s
= level_mask
& tex
->stencil_dirty_level_mask
;
330 if (si_can_sample_zs(tex
, true))
331 inplace_planes
|= PIPE_MASK_S
;
333 copy_planes
|= PIPE_MASK_S
;
337 if (unlikely(sctx
->b
.log
))
338 u_log_printf(sctx
->b
.log
,
339 "\n------------------------------------------------\n"
340 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
341 first_level
, last_level
, levels_z
, levels_s
);
343 /* We may have to allocate the flushed texture here when called from
344 * si_decompress_subresource.
347 (tex
->flushed_depth_texture
||
348 si_init_flushed_depth_texture(&sctx
->b
.b
, &tex
->resource
.b
.b
, NULL
))) {
349 struct r600_texture
*dst
= tex
->flushed_depth_texture
;
350 unsigned fully_copied_levels
;
353 assert(tex
->flushed_depth_texture
);
355 if (util_format_is_depth_and_stencil(dst
->resource
.b
.b
.format
))
356 copy_planes
= PIPE_MASK_Z
| PIPE_MASK_S
;
358 if (copy_planes
& PIPE_MASK_Z
) {
362 if (copy_planes
& PIPE_MASK_S
) {
367 fully_copied_levels
= si_blit_dbcb_copy(
368 sctx
, tex
, dst
, copy_planes
, levels
,
369 first_layer
, last_layer
,
370 0, u_max_sample(&tex
->resource
.b
.b
));
372 if (copy_planes
& PIPE_MASK_Z
)
373 tex
->dirty_level_mask
&= ~fully_copied_levels
;
374 if (copy_planes
& PIPE_MASK_S
)
375 tex
->stencil_dirty_level_mask
&= ~fully_copied_levels
;
378 if (inplace_planes
) {
379 bool has_htile
= si_htile_enabled(tex
, first_level
);
380 bool tc_compat_htile
= vi_tc_compat_htile_enabled(tex
, first_level
);
382 /* Don't decompress if there is no HTILE or when HTILE is
384 if (has_htile
&& !tc_compat_htile
) {
385 si_blit_decompress_zs_in_place(
388 first_layer
, last_layer
);
390 /* This is only a cache flush.
392 * Only clear the mask that we are flushing, because
393 * si_make_DB_shader_coherent() treats different levels
394 * and depth and stencil differently.
396 if (inplace_planes
& PIPE_MASK_Z
)
397 tex
->dirty_level_mask
&= ~levels_z
;
398 if (inplace_planes
& PIPE_MASK_S
)
399 tex
->stencil_dirty_level_mask
&= ~levels_s
;
402 /* Only in-place decompression needs to flush DB caches, or
403 * when we don't decompress but TC-compatible planes are dirty.
405 si_make_DB_shader_coherent(sctx
, tex
->resource
.b
.b
.nr_samples
,
406 inplace_planes
& PIPE_MASK_S
,
409 /* set_framebuffer_state takes care of coherency for single-sample.
410 * The DB->CB copy uses CB for the final writes.
412 if (copy_planes
&& tex
->resource
.b
.b
.nr_samples
> 1)
413 si_make_CB_shader_coherent(sctx
, tex
->resource
.b
.b
.nr_samples
,
418 si_decompress_sampler_depth_textures(struct si_context
*sctx
,
419 struct si_samplers
*textures
)
422 unsigned mask
= textures
->needs_depth_decompress_mask
;
425 struct pipe_sampler_view
*view
;
426 struct si_sampler_view
*sview
;
427 struct r600_texture
*tex
;
429 i
= u_bit_scan(&mask
);
431 view
= textures
->views
[i
];
433 sview
= (struct si_sampler_view
*)view
;
435 tex
= (struct r600_texture
*)view
->texture
;
436 assert(tex
->db_compatible
);
438 si_decompress_depth(sctx
, tex
,
439 sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
440 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
441 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
));
445 static void si_blit_decompress_color(struct pipe_context
*ctx
,
446 struct r600_texture
*rtex
,
447 unsigned first_level
, unsigned last_level
,
448 unsigned first_layer
, unsigned last_layer
,
449 bool need_dcc_decompress
)
451 struct si_context
*sctx
= (struct si_context
*)ctx
;
453 unsigned layer
, checked_last_layer
, max_layer
;
454 unsigned level_mask
=
455 u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
457 if (!need_dcc_decompress
)
458 level_mask
&= rtex
->dirty_level_mask
;
462 if (unlikely(sctx
->b
.log
))
463 u_log_printf(sctx
->b
.log
,
464 "\n------------------------------------------------\n"
465 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
466 first_level
, last_level
, level_mask
);
468 if (need_dcc_decompress
) {
469 custom_blend
= sctx
->custom_blend_dcc_decompress
;
471 assert(rtex
->dcc_offset
);
473 /* disable levels without DCC */
474 for (int i
= first_level
; i
<= last_level
; i
++) {
475 if (!vi_dcc_enabled(rtex
, i
))
476 level_mask
&= ~(1 << i
);
478 } else if (rtex
->fmask
.size
) {
479 custom_blend
= sctx
->custom_blend_fmask_decompress
;
481 custom_blend
= sctx
->custom_blend_eliminate_fastclear
;
484 sctx
->decompression_enabled
= true;
487 unsigned level
= u_bit_scan(&level_mask
);
489 /* The smaller the mipmap level, the less layers there are
490 * as far as 3D textures are concerned. */
491 max_layer
= util_max_layer(&rtex
->resource
.b
.b
, level
);
492 checked_last_layer
= MIN2(last_layer
, max_layer
);
494 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
495 struct pipe_surface
*cbsurf
, surf_tmpl
;
497 surf_tmpl
.format
= rtex
->resource
.b
.b
.format
;
498 surf_tmpl
.u
.tex
.level
= level
;
499 surf_tmpl
.u
.tex
.first_layer
= layer
;
500 surf_tmpl
.u
.tex
.last_layer
= layer
;
501 cbsurf
= ctx
->create_surface(ctx
, &rtex
->resource
.b
.b
, &surf_tmpl
);
503 /* Required before and after FMASK and DCC_DECOMPRESS. */
504 if (custom_blend
== sctx
->custom_blend_fmask_decompress
||
505 custom_blend
== sctx
->custom_blend_dcc_decompress
)
506 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
508 si_blitter_begin(ctx
, SI_DECOMPRESS
);
509 util_blitter_custom_color(sctx
->blitter
, cbsurf
, custom_blend
);
512 if (custom_blend
== sctx
->custom_blend_fmask_decompress
||
513 custom_blend
== sctx
->custom_blend_dcc_decompress
)
514 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
516 pipe_surface_reference(&cbsurf
, NULL
);
519 /* The texture will always be dirty if some layers aren't flushed.
520 * I don't think this case occurs often though. */
521 if (first_layer
== 0 && last_layer
>= max_layer
) {
522 rtex
->dirty_level_mask
&= ~(1 << level
);
526 sctx
->decompression_enabled
= false;
527 si_make_CB_shader_coherent(sctx
, rtex
->resource
.b
.b
.nr_samples
,
528 vi_dcc_enabled(rtex
, first_level
));
532 si_decompress_color_texture(struct si_context
*sctx
, struct r600_texture
*tex
,
533 unsigned first_level
, unsigned last_level
)
535 /* CMASK or DCC can be discarded and we can still end up here. */
536 if (!tex
->cmask
.size
&& !tex
->fmask
.size
&& !tex
->dcc_offset
)
539 si_blit_decompress_color(&sctx
->b
.b
, tex
, first_level
, last_level
, 0,
540 util_max_layer(&tex
->resource
.b
.b
, first_level
),
545 si_decompress_sampler_color_textures(struct si_context
*sctx
,
546 struct si_samplers
*textures
)
549 unsigned mask
= textures
->needs_color_decompress_mask
;
552 struct pipe_sampler_view
*view
;
553 struct r600_texture
*tex
;
555 i
= u_bit_scan(&mask
);
557 view
= textures
->views
[i
];
560 tex
= (struct r600_texture
*)view
->texture
;
562 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
,
563 view
->u
.tex
.last_level
);
568 si_decompress_image_color_textures(struct si_context
*sctx
,
569 struct si_images
*images
)
572 unsigned mask
= images
->needs_color_decompress_mask
;
575 const struct pipe_image_view
*view
;
576 struct r600_texture
*tex
;
578 i
= u_bit_scan(&mask
);
580 view
= &images
->views
[i
];
581 assert(view
->resource
->target
!= PIPE_BUFFER
);
583 tex
= (struct r600_texture
*)view
->resource
;
585 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
,
590 static void si_check_render_feedback_texture(struct si_context
*sctx
,
591 struct r600_texture
*tex
,
592 unsigned first_level
,
594 unsigned first_layer
,
597 bool render_feedback
= false;
599 if (!tex
->dcc_offset
)
602 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
603 struct r600_surface
* surf
;
605 if (!sctx
->framebuffer
.state
.cbufs
[j
])
608 surf
= (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
610 if (tex
== (struct r600_texture
*)surf
->base
.texture
&&
611 surf
->base
.u
.tex
.level
>= first_level
&&
612 surf
->base
.u
.tex
.level
<= last_level
&&
613 surf
->base
.u
.tex
.first_layer
<= last_layer
&&
614 surf
->base
.u
.tex
.last_layer
>= first_layer
) {
615 render_feedback
= true;
621 si_texture_disable_dcc(sctx
, tex
);
624 static void si_check_render_feedback_textures(struct si_context
*sctx
,
625 struct si_samplers
*textures
)
627 uint32_t mask
= textures
->enabled_mask
;
630 const struct pipe_sampler_view
*view
;
631 struct r600_texture
*tex
;
633 unsigned i
= u_bit_scan(&mask
);
635 view
= textures
->views
[i
];
636 if(view
->texture
->target
== PIPE_BUFFER
)
639 tex
= (struct r600_texture
*)view
->texture
;
641 si_check_render_feedback_texture(sctx
, tex
,
642 view
->u
.tex
.first_level
,
643 view
->u
.tex
.last_level
,
644 view
->u
.tex
.first_layer
,
645 view
->u
.tex
.last_layer
);
649 static void si_check_render_feedback_images(struct si_context
*sctx
,
650 struct si_images
*images
)
652 uint32_t mask
= images
->enabled_mask
;
655 const struct pipe_image_view
*view
;
656 struct r600_texture
*tex
;
658 unsigned i
= u_bit_scan(&mask
);
660 view
= &images
->views
[i
];
661 if (view
->resource
->target
== PIPE_BUFFER
)
664 tex
= (struct r600_texture
*)view
->resource
;
666 si_check_render_feedback_texture(sctx
, tex
,
669 view
->u
.tex
.first_layer
,
670 view
->u
.tex
.last_layer
);
674 static void si_check_render_feedback_resident_textures(struct si_context
*sctx
)
676 util_dynarray_foreach(&sctx
->resident_tex_handles
,
677 struct si_texture_handle
*, tex_handle
) {
678 struct pipe_sampler_view
*view
;
679 struct r600_texture
*tex
;
681 view
= (*tex_handle
)->view
;
682 if (view
->texture
->target
== PIPE_BUFFER
)
685 tex
= (struct r600_texture
*)view
->texture
;
687 si_check_render_feedback_texture(sctx
, tex
,
688 view
->u
.tex
.first_level
,
689 view
->u
.tex
.last_level
,
690 view
->u
.tex
.first_layer
,
691 view
->u
.tex
.last_layer
);
695 static void si_check_render_feedback_resident_images(struct si_context
*sctx
)
697 util_dynarray_foreach(&sctx
->resident_img_handles
,
698 struct si_image_handle
*, img_handle
) {
699 struct pipe_image_view
*view
;
700 struct r600_texture
*tex
;
702 view
= &(*img_handle
)->view
;
703 if (view
->resource
->target
== PIPE_BUFFER
)
706 tex
= (struct r600_texture
*)view
->resource
;
708 si_check_render_feedback_texture(sctx
, tex
,
711 view
->u
.tex
.first_layer
,
712 view
->u
.tex
.last_layer
);
716 static void si_check_render_feedback(struct si_context
*sctx
)
718 /* There is no render feedback if color writes are disabled.
719 * (e.g. a pixel shader with image stores)
721 if (!si_get_total_colormask(sctx
))
724 if (!sctx
->need_check_render_feedback
)
727 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
728 si_check_render_feedback_images(sctx
, &sctx
->images
[i
]);
729 si_check_render_feedback_textures(sctx
, &sctx
->samplers
[i
]);
732 si_check_render_feedback_resident_images(sctx
);
733 si_check_render_feedback_resident_textures(sctx
);
735 sctx
->need_check_render_feedback
= false;
738 static void si_decompress_resident_textures(struct si_context
*sctx
)
740 util_dynarray_foreach(&sctx
->resident_tex_needs_color_decompress
,
741 struct si_texture_handle
*, tex_handle
) {
742 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
743 struct r600_texture
*tex
= (struct r600_texture
*)view
->texture
;
745 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
,
746 view
->u
.tex
.last_level
);
749 util_dynarray_foreach(&sctx
->resident_tex_needs_depth_decompress
,
750 struct si_texture_handle
*, tex_handle
) {
751 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
752 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
753 struct r600_texture
*tex
= (struct r600_texture
*)view
->texture
;
755 si_decompress_depth(sctx
, tex
,
756 sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
757 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
758 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
));
762 static void si_decompress_resident_images(struct si_context
*sctx
)
764 util_dynarray_foreach(&sctx
->resident_img_needs_color_decompress
,
765 struct si_image_handle
*, img_handle
) {
766 struct pipe_image_view
*view
= &(*img_handle
)->view
;
767 struct r600_texture
*tex
= (struct r600_texture
*)view
->resource
;
769 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
,
774 void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
)
776 unsigned compressed_colortex_counter
, mask
;
778 if (sctx
->blitter
->running
)
781 /* Update the compressed_colortex_mask if necessary. */
782 compressed_colortex_counter
= p_atomic_read(&sctx
->screen
->compressed_colortex_counter
);
783 if (compressed_colortex_counter
!= sctx
->b
.last_compressed_colortex_counter
) {
784 sctx
->b
.last_compressed_colortex_counter
= compressed_colortex_counter
;
785 si_update_needs_color_decompress_masks(sctx
);
788 /* Decompress color & depth textures if needed. */
789 mask
= sctx
->shader_needs_decompress_mask
& shader_mask
;
791 unsigned i
= u_bit_scan(&mask
);
793 if (sctx
->samplers
[i
].needs_depth_decompress_mask
) {
794 si_decompress_sampler_depth_textures(sctx
, &sctx
->samplers
[i
]);
796 if (sctx
->samplers
[i
].needs_color_decompress_mask
) {
797 si_decompress_sampler_color_textures(sctx
, &sctx
->samplers
[i
]);
799 if (sctx
->images
[i
].needs_color_decompress_mask
) {
800 si_decompress_image_color_textures(sctx
, &sctx
->images
[i
]);
804 if (shader_mask
& u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
)) {
805 if (sctx
->uses_bindless_samplers
)
806 si_decompress_resident_textures(sctx
);
807 if (sctx
->uses_bindless_images
)
808 si_decompress_resident_images(sctx
);
809 } else if (shader_mask
& (1 << PIPE_SHADER_COMPUTE
)) {
810 if (sctx
->cs_shader_state
.program
->uses_bindless_samplers
)
811 si_decompress_resident_textures(sctx
);
812 if (sctx
->cs_shader_state
.program
->uses_bindless_images
)
813 si_decompress_resident_images(sctx
);
816 if (sctx
->ps_uses_fbfetch
) {
817 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
818 si_decompress_color_texture(sctx
,
819 (struct r600_texture
*)cb0
->texture
,
820 cb0
->u
.tex
.first_layer
,
821 cb0
->u
.tex
.last_layer
);
824 si_check_render_feedback(sctx
);
827 /* Helper for decompressing a portion of a color or depth resource before
828 * blitting if any decompression is needed.
829 * The driver doesn't decompress resources automatically while u_blitter is
831 static void si_decompress_subresource(struct pipe_context
*ctx
,
832 struct pipe_resource
*tex
,
833 unsigned planes
, unsigned level
,
834 unsigned first_layer
, unsigned last_layer
)
836 struct si_context
*sctx
= (struct si_context
*)ctx
;
837 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
839 if (rtex
->db_compatible
) {
840 planes
&= PIPE_MASK_Z
| PIPE_MASK_S
;
842 if (!rtex
->surface
.has_stencil
)
843 planes
&= ~PIPE_MASK_S
;
845 /* If we've rendered into the framebuffer and it's a blitting
846 * source, make sure the decompression pass is invoked
847 * by dirtying the framebuffer.
849 if (sctx
->framebuffer
.state
.zsbuf
&&
850 sctx
->framebuffer
.state
.zsbuf
->u
.tex
.level
== level
&&
851 sctx
->framebuffer
.state
.zsbuf
->texture
== tex
)
852 si_update_fb_dirtiness_after_rendering(sctx
);
854 si_decompress_depth(sctx
, rtex
, planes
,
856 first_layer
, last_layer
);
857 } else if (rtex
->fmask
.size
|| rtex
->cmask
.size
|| rtex
->dcc_offset
) {
858 /* If we've rendered into the framebuffer and it's a blitting
859 * source, make sure the decompression pass is invoked
860 * by dirtying the framebuffer.
862 for (unsigned i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
863 if (sctx
->framebuffer
.state
.cbufs
[i
] &&
864 sctx
->framebuffer
.state
.cbufs
[i
]->u
.tex
.level
== level
&&
865 sctx
->framebuffer
.state
.cbufs
[i
]->texture
== tex
) {
866 si_update_fb_dirtiness_after_rendering(sctx
);
871 si_blit_decompress_color(ctx
, rtex
, level
, level
,
872 first_layer
, last_layer
, false);
876 struct texture_orig_info
{
886 void si_resource_copy_region(struct pipe_context
*ctx
,
887 struct pipe_resource
*dst
,
889 unsigned dstx
, unsigned dsty
, unsigned dstz
,
890 struct pipe_resource
*src
,
892 const struct pipe_box
*src_box
)
894 struct si_context
*sctx
= (struct si_context
*)ctx
;
895 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
896 struct pipe_surface
*dst_view
, dst_templ
;
897 struct pipe_sampler_view src_templ
, *src_view
;
898 unsigned dst_width
, dst_height
, src_width0
, src_height0
;
899 unsigned dst_width0
, dst_height0
, src_force_level
= 0;
900 struct pipe_box sbox
, dstbox
;
902 /* Handle buffers first. */
903 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
904 si_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
, 0);
908 assert(u_max_sample(dst
) == u_max_sample(src
));
910 /* The driver doesn't decompress resources automatically while
911 * u_blitter is rendering. */
912 si_decompress_subresource(ctx
, src
, PIPE_MASK_RGBAZS
, src_level
,
913 src_box
->z
, src_box
->z
+ src_box
->depth
- 1);
915 dst_width
= u_minify(dst
->width0
, dst_level
);
916 dst_height
= u_minify(dst
->height0
, dst_level
);
917 dst_width0
= dst
->width0
;
918 dst_height0
= dst
->height0
;
919 src_width0
= src
->width0
;
920 src_height0
= src
->height0
;
922 util_blitter_default_dst_texture(&dst_templ
, dst
, dst_level
, dstz
);
923 util_blitter_default_src_texture(sctx
->blitter
, &src_templ
, src
, src_level
);
925 if (util_format_is_compressed(src
->format
) ||
926 util_format_is_compressed(dst
->format
)) {
927 unsigned blocksize
= rsrc
->surface
.bpe
;
930 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; /* 64-bit block */
932 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; /* 128-bit block */
933 dst_templ
.format
= src_templ
.format
;
935 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
936 dst_height
= util_format_get_nblocksy(dst
->format
, dst_height
);
937 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
938 dst_height0
= util_format_get_nblocksy(dst
->format
, dst_height0
);
939 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
940 src_height0
= util_format_get_nblocksy(src
->format
, src_height0
);
942 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
943 dsty
= util_format_get_nblocksy(dst
->format
, dsty
);
945 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
946 sbox
.y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
948 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
949 sbox
.height
= util_format_get_nblocksy(src
->format
, src_box
->height
);
950 sbox
.depth
= src_box
->depth
;
953 src_force_level
= src_level
;
954 } else if (!util_blitter_is_copy_supported(sctx
->blitter
, dst
, src
)) {
955 if (util_format_is_subsampled_422(src
->format
)) {
956 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
957 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
959 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
960 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
961 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
963 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
966 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
967 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
970 unsigned blocksize
= rsrc
->surface
.bpe
;
974 dst_templ
.format
= PIPE_FORMAT_R8_UNORM
;
975 src_templ
.format
= PIPE_FORMAT_R8_UNORM
;
978 dst_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
979 src_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
982 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
983 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
986 dst_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
987 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
990 dst_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
991 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
994 fprintf(stderr
, "Unhandled format %s with blocksize %u\n",
995 util_format_short_name(src
->format
), blocksize
);
1001 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1002 * equivalent instead, which doesn't force DCC decompression.
1003 * Note that some chips avoid this issue by using SDMA.
1005 if (util_format_is_snorm8(dst_templ
.format
)) {
1006 switch (dst_templ
.format
) {
1007 case PIPE_FORMAT_R8_SNORM
:
1008 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8_SINT
;
1010 case PIPE_FORMAT_R8G8_SNORM
:
1011 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8_SINT
;
1013 case PIPE_FORMAT_R8G8B8X8_SNORM
:
1014 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8B8X8_SINT
;
1016 case PIPE_FORMAT_R8G8B8A8_SNORM
:
1017 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1018 case PIPE_FORMAT_A8B8G8R8_SNORM
:
1019 case PIPE_FORMAT_X8B8G8R8_SNORM
:
1020 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8B8A8_SINT
;
1022 case PIPE_FORMAT_A8_SNORM
:
1023 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_A8_SINT
;
1025 case PIPE_FORMAT_L8_SNORM
:
1026 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_L8_SINT
;
1028 case PIPE_FORMAT_L8A8_SNORM
:
1029 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_L8A8_SINT
;
1031 case PIPE_FORMAT_I8_SNORM
:
1032 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_I8_SINT
;
1034 default:; /* fall through */
1038 vi_disable_dcc_if_incompatible_format(sctx
, dst
, dst_level
,
1040 vi_disable_dcc_if_incompatible_format(sctx
, src
, src_level
,
1043 /* Initialize the surface. */
1044 dst_view
= si_create_surface_custom(ctx
, dst
, &dst_templ
,
1045 dst_width0
, dst_height0
,
1046 dst_width
, dst_height
);
1048 /* Initialize the sampler view. */
1049 src_view
= si_create_sampler_view_custom(ctx
, src
, &src_templ
,
1050 src_width0
, src_height0
,
1053 u_box_3d(dstx
, dsty
, dstz
, abs(src_box
->width
), abs(src_box
->height
),
1054 abs(src_box
->depth
), &dstbox
);
1057 si_blitter_begin(ctx
, SI_COPY
);
1058 util_blitter_blit_generic(sctx
->blitter
, dst_view
, &dstbox
,
1059 src_view
, src_box
, src_width0
, src_height0
,
1060 PIPE_MASK_RGBAZS
, PIPE_TEX_FILTER_NEAREST
, NULL
,
1062 si_blitter_end(ctx
);
1064 pipe_surface_reference(&dst_view
, NULL
);
1065 pipe_sampler_view_reference(&src_view
, NULL
);
1068 static void si_do_CB_resolve(struct si_context
*sctx
,
1069 const struct pipe_blit_info
*info
,
1070 struct pipe_resource
*dst
,
1071 unsigned dst_level
, unsigned dst_z
,
1072 enum pipe_format format
)
1074 /* Required before and after CB_RESOLVE. */
1075 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
1077 si_blitter_begin(&sctx
->b
.b
, SI_COLOR_RESOLVE
|
1078 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1079 util_blitter_custom_resolve_color(sctx
->blitter
, dst
, dst_level
, dst_z
,
1080 info
->src
.resource
, info
->src
.box
.z
,
1081 ~0, sctx
->custom_blend_resolve
,
1083 si_blitter_end(&sctx
->b
.b
);
1085 /* Flush caches for possible texturing. */
1086 si_make_CB_shader_coherent(sctx
, 1, false);
1089 static bool do_hardware_msaa_resolve(struct pipe_context
*ctx
,
1090 const struct pipe_blit_info
*info
)
1092 struct si_context
*sctx
= (struct si_context
*)ctx
;
1093 struct r600_texture
*src
= (struct r600_texture
*)info
->src
.resource
;
1094 struct r600_texture
*dst
= (struct r600_texture
*)info
->dst
.resource
;
1095 MAYBE_UNUSED
struct r600_texture
*rtmp
;
1096 unsigned dst_width
= u_minify(info
->dst
.resource
->width0
, info
->dst
.level
);
1097 unsigned dst_height
= u_minify(info
->dst
.resource
->height0
, info
->dst
.level
);
1098 enum pipe_format format
= info
->src
.format
;
1099 struct pipe_resource
*tmp
, templ
;
1100 struct pipe_blit_info blit
;
1102 /* Check basic requirements for hw resolve. */
1103 if (!(info
->src
.resource
->nr_samples
> 1 &&
1104 info
->dst
.resource
->nr_samples
<= 1 &&
1105 !util_format_is_pure_integer(format
) &&
1106 !util_format_is_depth_or_stencil(format
) &&
1107 util_max_layer(info
->src
.resource
, 0) == 0))
1110 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1111 * the format is R16G16. Use R16A16, which does work.
1113 if (format
== PIPE_FORMAT_R16G16_UNORM
)
1114 format
= PIPE_FORMAT_R16A16_UNORM
;
1115 if (format
== PIPE_FORMAT_R16G16_SNORM
)
1116 format
= PIPE_FORMAT_R16A16_SNORM
;
1118 /* Check the remaining requirements for hw resolve. */
1119 if (util_max_layer(info
->dst
.resource
, info
->dst
.level
) == 0 &&
1120 !info
->scissor_enable
&&
1121 (info
->mask
& PIPE_MASK_RGBA
) == PIPE_MASK_RGBA
&&
1122 util_is_format_compatible(util_format_description(info
->src
.format
),
1123 util_format_description(info
->dst
.format
)) &&
1124 dst_width
== info
->src
.resource
->width0
&&
1125 dst_height
== info
->src
.resource
->height0
&&
1126 info
->dst
.box
.x
== 0 &&
1127 info
->dst
.box
.y
== 0 &&
1128 info
->dst
.box
.width
== dst_width
&&
1129 info
->dst
.box
.height
== dst_height
&&
1130 info
->dst
.box
.depth
== 1 &&
1131 info
->src
.box
.x
== 0 &&
1132 info
->src
.box
.y
== 0 &&
1133 info
->src
.box
.width
== dst_width
&&
1134 info
->src
.box
.height
== dst_height
&&
1135 info
->src
.box
.depth
== 1 &&
1136 !dst
->surface
.is_linear
&&
1137 (!dst
->cmask
.size
|| !dst
->dirty_level_mask
)) { /* dst cannot be fast-cleared */
1138 /* Check the last constraint. */
1139 if (src
->surface
.micro_tile_mode
!= dst
->surface
.micro_tile_mode
) {
1140 /* The next fast clear will switch to this mode to
1141 * get direct hw resolve next time if the mode is
1144 src
->last_msaa_resolve_target_micro_mode
=
1145 dst
->surface
.micro_tile_mode
;
1146 goto resolve_to_temp
;
1149 /* Resolving into a surface with DCC is unsupported. Since
1150 * it's being overwritten anyway, clear it to uncompressed.
1151 * This is still the fastest codepath even with this clear.
1153 if (vi_dcc_enabled(dst
, info
->dst
.level
)) {
1154 /* TODO: Implement per-level DCC clears for GFX9. */
1155 if (sctx
->b
.chip_class
>= GFX9
&&
1156 info
->dst
.resource
->last_level
!= 0)
1157 goto resolve_to_temp
;
1159 vi_dcc_clear_level(sctx
, dst
, info
->dst
.level
,
1161 dst
->dirty_level_mask
&= ~(1 << info
->dst
.level
);
1164 /* Resolve directly from src to dst. */
1165 si_do_CB_resolve(sctx
, info
, info
->dst
.resource
,
1166 info
->dst
.level
, info
->dst
.box
.z
, format
);
1171 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1172 * a temporary texture and blit.
1174 memset(&templ
, 0, sizeof(templ
));
1175 templ
.target
= PIPE_TEXTURE_2D
;
1176 templ
.format
= info
->src
.resource
->format
;
1177 templ
.width0
= info
->src
.resource
->width0
;
1178 templ
.height0
= info
->src
.resource
->height0
;
1180 templ
.array_size
= 1;
1181 templ
.usage
= PIPE_USAGE_DEFAULT
;
1182 templ
.flags
= R600_RESOURCE_FLAG_FORCE_TILING
|
1183 R600_RESOURCE_FLAG_DISABLE_DCC
;
1185 /* The src and dst microtile modes must be the same. */
1186 if (src
->surface
.micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
)
1187 templ
.bind
= PIPE_BIND_SCANOUT
;
1191 tmp
= ctx
->screen
->resource_create(ctx
->screen
, &templ
);
1194 rtmp
= (struct r600_texture
*)tmp
;
1196 assert(!rtmp
->surface
.is_linear
);
1197 assert(src
->surface
.micro_tile_mode
== rtmp
->surface
.micro_tile_mode
);
1200 si_do_CB_resolve(sctx
, info
, tmp
, 0, 0, format
);
1204 blit
.src
.resource
= tmp
;
1207 si_blitter_begin(ctx
, SI_BLIT
|
1208 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1209 util_blitter_blit(sctx
->blitter
, &blit
);
1210 si_blitter_end(ctx
);
1212 pipe_resource_reference(&tmp
, NULL
);
1216 static void si_blit(struct pipe_context
*ctx
,
1217 const struct pipe_blit_info
*info
)
1219 struct si_context
*sctx
= (struct si_context
*)ctx
;
1220 struct r600_texture
*rdst
= (struct r600_texture
*)info
->dst
.resource
;
1222 if (do_hardware_msaa_resolve(ctx
, info
)) {
1226 /* Using SDMA for copying to a linear texture in GTT is much faster.
1227 * This improves DRI PRIME performance.
1229 * resource_copy_region can't do this yet, because dma_copy calls it
1230 * on failure (recursion).
1232 if (rdst
->surface
.is_linear
&&
1234 util_can_blit_via_copy_region(info
, false)) {
1235 sctx
->b
.dma_copy(ctx
, info
->dst
.resource
, info
->dst
.level
,
1236 info
->dst
.box
.x
, info
->dst
.box
.y
,
1238 info
->src
.resource
, info
->src
.level
,
1243 assert(util_blitter_is_blit_supported(sctx
->blitter
, info
));
1245 /* The driver doesn't decompress resources automatically while
1246 * u_blitter is rendering. */
1247 vi_disable_dcc_if_incompatible_format(sctx
, info
->src
.resource
,
1250 vi_disable_dcc_if_incompatible_format(sctx
, info
->dst
.resource
,
1253 si_decompress_subresource(ctx
, info
->src
.resource
, info
->mask
,
1256 info
->src
.box
.z
+ info
->src
.box
.depth
- 1);
1258 if (sctx
->screen
->debug_flags
& DBG(FORCE_DMA
) &&
1259 util_try_blit_via_copy_region(ctx
, info
))
1262 si_blitter_begin(ctx
, SI_BLIT
|
1263 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1264 util_blitter_blit(sctx
->blitter
, info
);
1265 si_blitter_end(ctx
);
1268 static boolean
si_generate_mipmap(struct pipe_context
*ctx
,
1269 struct pipe_resource
*tex
,
1270 enum pipe_format format
,
1271 unsigned base_level
, unsigned last_level
,
1272 unsigned first_layer
, unsigned last_layer
)
1274 struct si_context
*sctx
= (struct si_context
*)ctx
;
1275 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1277 if (!util_blitter_is_copy_supported(sctx
->blitter
, tex
, tex
))
1280 /* The driver doesn't decompress resources automatically while
1281 * u_blitter is rendering. */
1282 vi_disable_dcc_if_incompatible_format(sctx
, tex
, base_level
,
1284 si_decompress_subresource(ctx
, tex
, PIPE_MASK_RGBAZS
,
1285 base_level
, first_layer
, last_layer
);
1287 /* Clear dirty_level_mask for the levels that will be overwritten. */
1288 assert(base_level
< last_level
);
1289 rtex
->dirty_level_mask
&= ~u_bit_consecutive(base_level
+ 1,
1290 last_level
- base_level
);
1292 sctx
->generate_mipmap_for_depth
= rtex
->is_depth
;
1294 si_blitter_begin(ctx
, SI_BLIT
| SI_DISABLE_RENDER_COND
);
1295 util_blitter_generate_mipmap(sctx
->blitter
, tex
, format
,
1296 base_level
, last_level
,
1297 first_layer
, last_layer
);
1298 si_blitter_end(ctx
);
1300 sctx
->generate_mipmap_for_depth
= false;
1304 static void si_flush_resource(struct pipe_context
*ctx
,
1305 struct pipe_resource
*res
)
1307 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
1309 assert(res
->target
!= PIPE_BUFFER
);
1310 assert(!rtex
->dcc_separate_buffer
|| rtex
->dcc_gather_statistics
);
1312 /* st/dri calls flush twice per frame (not a bug), this prevents double
1314 if (rtex
->dcc_separate_buffer
&& !rtex
->separate_dcc_dirty
)
1317 if (!rtex
->is_depth
&& (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
1318 si_blit_decompress_color(ctx
, rtex
, 0, res
->last_level
,
1319 0, util_max_layer(res
, 0),
1320 rtex
->dcc_separate_buffer
!= NULL
);
1323 /* Always do the analysis even if DCC is disabled at the moment. */
1324 if (rtex
->dcc_gather_statistics
&& rtex
->separate_dcc_dirty
) {
1325 rtex
->separate_dcc_dirty
= false;
1326 vi_separate_dcc_process_and_reset_stats(ctx
, rtex
);
1330 void si_decompress_dcc(struct pipe_context
*ctx
, struct r600_texture
*rtex
)
1332 if (!rtex
->dcc_offset
)
1335 si_blit_decompress_color(ctx
, rtex
, 0, rtex
->resource
.b
.b
.last_level
,
1336 0, util_max_layer(&rtex
->resource
.b
.b
, 0),
1340 void si_init_blit_functions(struct si_context
*sctx
)
1342 sctx
->b
.b
.resource_copy_region
= si_resource_copy_region
;
1343 sctx
->b
.b
.blit
= si_blit
;
1344 sctx
->b
.b
.flush_resource
= si_flush_resource
;
1345 sctx
->b
.b
.generate_mipmap
= si_generate_mipmap
;