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radeonsi: unify CB_RESOLVE blitter invocation code
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_surface.h"
28
29 enum si_blitter_op /* bitmask */
30 {
31 SI_SAVE_TEXTURES = 1,
32 SI_SAVE_FRAMEBUFFER = 2,
33 SI_SAVE_FRAGMENT_STATE = 4,
34 SI_DISABLE_RENDER_COND = 8,
35
36 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
37
38 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
39
40 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
41 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
42
43 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
44 SI_SAVE_FRAGMENT_STATE,
45
46 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
47 SI_DISABLE_RENDER_COND,
48
49 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
50 };
51
52 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
53 {
54 struct si_context *sctx = (struct si_context *)ctx;
55
56 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
57 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
58 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
59 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
60 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
61 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
62 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
63 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
64 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
65
66 if (op & SI_SAVE_FRAGMENT_STATE) {
67 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
68 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
69 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
70 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
71 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
72 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
73 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
74 }
75
76 if (op & SI_SAVE_FRAMEBUFFER)
77 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
78
79 if (op & SI_SAVE_TEXTURES) {
80 util_blitter_save_fragment_sampler_states(
81 sctx->blitter, 2,
82 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
83
84 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
85 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
86 }
87
88 if (op & SI_DISABLE_RENDER_COND)
89 sctx->b.render_cond_force_off = true;
90 }
91
92 static void si_blitter_end(struct pipe_context *ctx)
93 {
94 struct si_context *sctx = (struct si_context *)ctx;
95
96 sctx->b.render_cond_force_off = false;
97 }
98
99 static unsigned u_max_sample(struct pipe_resource *r)
100 {
101 return r->nr_samples ? r->nr_samples - 1 : 0;
102 }
103
104 static unsigned
105 si_blit_dbcb_copy(struct si_context *sctx,
106 struct r600_texture *src,
107 struct r600_texture *dst,
108 unsigned planes, unsigned level_mask,
109 unsigned first_layer, unsigned last_layer,
110 unsigned first_sample, unsigned last_sample)
111 {
112 struct pipe_surface surf_tmpl = {{0}};
113 unsigned layer, sample, checked_last_layer, max_layer;
114 unsigned fully_copied_levels = 0;
115
116 if (planes & PIPE_MASK_Z)
117 sctx->dbcb_depth_copy_enabled = true;
118 if (planes & PIPE_MASK_S)
119 sctx->dbcb_stencil_copy_enabled = true;
120 si_mark_atom_dirty(sctx, &sctx->db_render_state);
121
122 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
123
124 bool old_update_dirtiness = sctx->framebuffer.do_update_surf_dirtiness;
125 sctx->decompression_enabled = true;
126 sctx->framebuffer.do_update_surf_dirtiness = false;
127
128 while (level_mask) {
129 unsigned level = u_bit_scan(&level_mask);
130
131 /* The smaller the mipmap level, the less layers there are
132 * as far as 3D textures are concerned. */
133 max_layer = util_max_layer(&src->resource.b.b, level);
134 checked_last_layer = MIN2(last_layer, max_layer);
135
136 surf_tmpl.u.tex.level = level;
137
138 for (layer = first_layer; layer <= checked_last_layer; layer++) {
139 struct pipe_surface *zsurf, *cbsurf;
140
141 surf_tmpl.format = src->resource.b.b.format;
142 surf_tmpl.u.tex.first_layer = layer;
143 surf_tmpl.u.tex.last_layer = layer;
144
145 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
146
147 surf_tmpl.format = dst->resource.b.b.format;
148 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
149
150 for (sample = first_sample; sample <= last_sample; sample++) {
151 if (sample != sctx->dbcb_copy_sample) {
152 sctx->dbcb_copy_sample = sample;
153 si_mark_atom_dirty(sctx, &sctx->db_render_state);
154 }
155
156 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
157 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
158 sctx->custom_dsa_flush, 1.0f);
159 si_blitter_end(&sctx->b.b);
160 }
161
162 pipe_surface_reference(&zsurf, NULL);
163 pipe_surface_reference(&cbsurf, NULL);
164 }
165
166 if (first_layer == 0 && last_layer >= max_layer &&
167 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
168 fully_copied_levels |= 1u << level;
169 }
170
171 sctx->decompression_enabled = false;
172 sctx->framebuffer.do_update_surf_dirtiness = old_update_dirtiness;
173 sctx->dbcb_depth_copy_enabled = false;
174 sctx->dbcb_stencil_copy_enabled = false;
175 si_mark_atom_dirty(sctx, &sctx->db_render_state);
176
177 return fully_copied_levels;
178 }
179
180 static void si_blit_decompress_depth(struct pipe_context *ctx,
181 struct r600_texture *texture,
182 struct r600_texture *staging,
183 unsigned first_level, unsigned last_level,
184 unsigned first_layer, unsigned last_layer,
185 unsigned first_sample, unsigned last_sample)
186 {
187 const struct util_format_description *desc;
188 unsigned planes = 0;
189
190 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
191
192 desc = util_format_description(staging->resource.b.b.format);
193
194 if (util_format_has_depth(desc))
195 planes |= PIPE_MASK_Z;
196 if (util_format_has_stencil(desc))
197 planes |= PIPE_MASK_S;
198
199 si_blit_dbcb_copy(
200 (struct si_context *)ctx, texture, staging, planes,
201 u_bit_consecutive(first_level, last_level - first_level + 1),
202 first_layer, last_layer, first_sample, last_sample);
203 }
204
205 /* Helper function for si_blit_decompress_zs_in_place.
206 */
207 static void
208 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
209 struct r600_texture *texture,
210 unsigned planes, unsigned level_mask,
211 unsigned first_layer, unsigned last_layer)
212 {
213 struct pipe_surface *zsurf, surf_tmpl = {{0}};
214 unsigned layer, max_layer, checked_last_layer;
215 unsigned fully_decompressed_mask = 0;
216
217 if (!level_mask)
218 return;
219
220 if (planes & PIPE_MASK_S)
221 sctx->db_flush_stencil_inplace = true;
222 if (planes & PIPE_MASK_Z)
223 sctx->db_flush_depth_inplace = true;
224 si_mark_atom_dirty(sctx, &sctx->db_render_state);
225
226 surf_tmpl.format = texture->resource.b.b.format;
227
228 bool old_update_dirtiness = sctx->framebuffer.do_update_surf_dirtiness;
229 sctx->decompression_enabled = true;
230 sctx->framebuffer.do_update_surf_dirtiness = false;
231
232 while (level_mask) {
233 unsigned level = u_bit_scan(&level_mask);
234
235 surf_tmpl.u.tex.level = level;
236
237 /* The smaller the mipmap level, the less layers there are
238 * as far as 3D textures are concerned. */
239 max_layer = util_max_layer(&texture->resource.b.b, level);
240 checked_last_layer = MIN2(last_layer, max_layer);
241
242 for (layer = first_layer; layer <= checked_last_layer; layer++) {
243 surf_tmpl.u.tex.first_layer = layer;
244 surf_tmpl.u.tex.last_layer = layer;
245
246 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
247
248 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
249 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
250 sctx->custom_dsa_flush,
251 1.0f);
252 si_blitter_end(&sctx->b.b);
253
254 pipe_surface_reference(&zsurf, NULL);
255 }
256
257 /* The texture will always be dirty if some layers aren't flushed.
258 * I don't think this case occurs often though. */
259 if (first_layer == 0 && last_layer >= max_layer) {
260 fully_decompressed_mask |= 1u << level;
261 }
262 }
263
264 if (planes & PIPE_MASK_Z)
265 texture->dirty_level_mask &= ~fully_decompressed_mask;
266 if (planes & PIPE_MASK_S)
267 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
268
269 sctx->decompression_enabled = false;
270 sctx->framebuffer.do_update_surf_dirtiness = old_update_dirtiness;
271 sctx->db_flush_depth_inplace = false;
272 sctx->db_flush_stencil_inplace = false;
273 si_mark_atom_dirty(sctx, &sctx->db_render_state);
274 }
275
276 /* Helper function of si_flush_depth_texture: decompress the given levels
277 * of Z and/or S planes in place.
278 */
279 static void
280 si_blit_decompress_zs_in_place(struct si_context *sctx,
281 struct r600_texture *texture,
282 unsigned levels_z, unsigned levels_s,
283 unsigned first_layer, unsigned last_layer)
284 {
285 unsigned both = levels_z & levels_s;
286
287 /* First, do combined Z & S decompresses for levels that need it. */
288 if (both) {
289 si_blit_decompress_zs_planes_in_place(
290 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
291 both,
292 first_layer, last_layer);
293 levels_z &= ~both;
294 levels_s &= ~both;
295 }
296
297 /* Now do separate Z and S decompresses. */
298 if (levels_z) {
299 si_blit_decompress_zs_planes_in_place(
300 sctx, texture, PIPE_MASK_Z,
301 levels_z,
302 first_layer, last_layer);
303 }
304
305 if (levels_s) {
306 si_blit_decompress_zs_planes_in_place(
307 sctx, texture, PIPE_MASK_S,
308 levels_s,
309 first_layer, last_layer);
310 }
311 }
312
313 static void
314 si_decompress_depth(struct si_context *sctx,
315 struct r600_texture *tex,
316 unsigned required_planes,
317 unsigned first_level, unsigned last_level,
318 unsigned first_layer, unsigned last_layer)
319 {
320 unsigned inplace_planes = 0;
321 unsigned copy_planes = 0;
322 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
323 unsigned levels_z = 0;
324 unsigned levels_s = 0;
325
326 if (required_planes & PIPE_MASK_Z) {
327 levels_z = level_mask & tex->dirty_level_mask;
328
329 if (levels_z) {
330 if (r600_can_sample_zs(tex, false))
331 inplace_planes |= PIPE_MASK_Z;
332 else
333 copy_planes |= PIPE_MASK_Z;
334 }
335 }
336 if (required_planes & PIPE_MASK_S) {
337 levels_s = level_mask & tex->stencil_dirty_level_mask;
338
339 if (levels_s) {
340 if (r600_can_sample_zs(tex, true))
341 inplace_planes |= PIPE_MASK_S;
342 else
343 copy_planes |= PIPE_MASK_S;
344 }
345 }
346
347 /* We may have to allocate the flushed texture here when called from
348 * si_decompress_subresource.
349 */
350 if (copy_planes &&
351 (tex->flushed_depth_texture ||
352 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
353 struct r600_texture *dst = tex->flushed_depth_texture;
354 unsigned fully_copied_levels;
355 unsigned levels = 0;
356
357 assert(tex->flushed_depth_texture);
358
359 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
360 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
361
362 if (copy_planes & PIPE_MASK_Z) {
363 levels |= levels_z;
364 levels_z = 0;
365 }
366 if (copy_planes & PIPE_MASK_S) {
367 levels |= levels_s;
368 levels_s = 0;
369 }
370
371 fully_copied_levels = si_blit_dbcb_copy(
372 sctx, tex, dst, copy_planes, levels,
373 first_layer, last_layer,
374 0, u_max_sample(&tex->resource.b.b));
375
376 if (copy_planes & PIPE_MASK_Z)
377 tex->dirty_level_mask &= ~fully_copied_levels;
378 if (copy_planes & PIPE_MASK_S)
379 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
380 }
381
382 if (inplace_planes) {
383 if (!tex->tc_compatible_htile) {
384 si_blit_decompress_zs_in_place(
385 sctx, tex,
386 levels_z, levels_s,
387 first_layer, last_layer);
388 }
389
390 /* Only in-place decompression needs to flush DB caches, or
391 * when we don't decompress but TC-compatible planes are dirty.
392 */
393 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
394 SI_CONTEXT_INV_GLOBAL_L2 |
395 SI_CONTEXT_INV_VMEM_L1;
396
397 /* If we flush DB caches for TC-compatible depth, the dirty
398 * state becomes 0 for the whole mipmap tree and all planes.
399 * (there is nothing else to flush)
400 */
401 if (tex->tc_compatible_htile) {
402 if (r600_can_sample_zs(tex, false))
403 tex->dirty_level_mask = 0;
404 if (r600_can_sample_zs(tex, true))
405 tex->stencil_dirty_level_mask = 0;
406 }
407 }
408 }
409
410 static void
411 si_decompress_sampler_depth_textures(struct si_context *sctx,
412 struct si_textures_info *textures)
413 {
414 unsigned i;
415 unsigned mask = textures->needs_depth_decompress_mask;
416
417 while (mask) {
418 struct pipe_sampler_view *view;
419 struct si_sampler_view *sview;
420 struct r600_texture *tex;
421
422 i = u_bit_scan(&mask);
423
424 view = textures->views.views[i];
425 assert(view);
426 sview = (struct si_sampler_view*)view;
427
428 tex = (struct r600_texture *)view->texture;
429 assert(tex->db_compatible);
430
431 si_decompress_depth(sctx, tex,
432 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
433 view->u.tex.first_level, view->u.tex.last_level,
434 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
435 }
436 }
437
438 static void si_blit_decompress_color(struct pipe_context *ctx,
439 struct r600_texture *rtex,
440 unsigned first_level, unsigned last_level,
441 unsigned first_layer, unsigned last_layer,
442 bool need_dcc_decompress)
443 {
444 struct si_context *sctx = (struct si_context *)ctx;
445 void* custom_blend;
446 unsigned layer, checked_last_layer, max_layer;
447 unsigned level_mask =
448 u_bit_consecutive(first_level, last_level - first_level + 1);
449
450 if (!need_dcc_decompress)
451 level_mask &= rtex->dirty_level_mask;
452 if (!level_mask)
453 return;
454
455 if (rtex->dcc_offset && need_dcc_decompress) {
456 custom_blend = sctx->custom_blend_dcc_decompress;
457
458 /* disable levels without DCC */
459 for (int i = first_level; i <= last_level; i++) {
460 if (!vi_dcc_enabled(rtex, i))
461 level_mask &= ~(1 << i);
462 }
463 } else if (rtex->fmask.size) {
464 custom_blend = sctx->custom_blend_fmask_decompress;
465 } else {
466 custom_blend = sctx->custom_blend_eliminate_fastclear;
467 }
468
469 bool old_update_dirtiness = sctx->framebuffer.do_update_surf_dirtiness;
470 sctx->decompression_enabled = true;
471 sctx->framebuffer.do_update_surf_dirtiness = false;
472
473 while (level_mask) {
474 unsigned level = u_bit_scan(&level_mask);
475
476 /* The smaller the mipmap level, the less layers there are
477 * as far as 3D textures are concerned. */
478 max_layer = util_max_layer(&rtex->resource.b.b, level);
479 checked_last_layer = MIN2(last_layer, max_layer);
480
481 for (layer = first_layer; layer <= checked_last_layer; layer++) {
482 struct pipe_surface *cbsurf, surf_tmpl;
483
484 surf_tmpl.format = rtex->resource.b.b.format;
485 surf_tmpl.u.tex.level = level;
486 surf_tmpl.u.tex.first_layer = layer;
487 surf_tmpl.u.tex.last_layer = layer;
488 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
489
490 si_blitter_begin(ctx, SI_DECOMPRESS);
491 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
492 si_blitter_end(ctx);
493
494 pipe_surface_reference(&cbsurf, NULL);
495 }
496
497 /* The texture will always be dirty if some layers aren't flushed.
498 * I don't think this case occurs often though. */
499 if (first_layer == 0 && last_layer >= max_layer) {
500 rtex->dirty_level_mask &= ~(1 << level);
501 }
502 }
503
504 sctx->decompression_enabled = false;
505 sctx->framebuffer.do_update_surf_dirtiness = old_update_dirtiness;
506 }
507
508 static void
509 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
510 unsigned first_level, unsigned last_level)
511 {
512 /* CMASK or DCC can be discarded and we can still end up here. */
513 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
514 return;
515
516 si_blit_decompress_color(&sctx->b.b, tex, first_level, last_level, 0,
517 util_max_layer(&tex->resource.b.b, first_level),
518 false);
519 }
520
521 static void
522 si_decompress_sampler_color_textures(struct si_context *sctx,
523 struct si_textures_info *textures)
524 {
525 unsigned i;
526 unsigned mask = textures->needs_color_decompress_mask;
527
528 while (mask) {
529 struct pipe_sampler_view *view;
530 struct r600_texture *tex;
531
532 i = u_bit_scan(&mask);
533
534 view = textures->views.views[i];
535 assert(view);
536
537 tex = (struct r600_texture *)view->texture;
538
539 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
540 view->u.tex.last_level);
541 }
542 }
543
544 static void
545 si_decompress_image_color_textures(struct si_context *sctx,
546 struct si_images_info *images)
547 {
548 unsigned i;
549 unsigned mask = images->needs_color_decompress_mask;
550
551 while (mask) {
552 const struct pipe_image_view *view;
553 struct r600_texture *tex;
554
555 i = u_bit_scan(&mask);
556
557 view = &images->views[i];
558 assert(view->resource->target != PIPE_BUFFER);
559
560 tex = (struct r600_texture *)view->resource;
561
562 si_decompress_color_texture(sctx, tex, view->u.tex.level,
563 view->u.tex.level);
564 }
565 }
566
567 static void si_check_render_feedback_texture(struct si_context *sctx,
568 struct r600_texture *tex,
569 unsigned first_level,
570 unsigned last_level,
571 unsigned first_layer,
572 unsigned last_layer)
573 {
574 bool render_feedback = false;
575
576 if (!tex->dcc_offset)
577 return;
578
579 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
580 struct r600_surface * surf;
581
582 if (!sctx->framebuffer.state.cbufs[j])
583 continue;
584
585 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
586
587 if (tex == (struct r600_texture *)surf->base.texture &&
588 surf->base.u.tex.level >= first_level &&
589 surf->base.u.tex.level <= last_level &&
590 surf->base.u.tex.first_layer <= last_layer &&
591 surf->base.u.tex.last_layer >= first_layer) {
592 render_feedback = true;
593 break;
594 }
595 }
596
597 if (render_feedback)
598 r600_texture_disable_dcc(&sctx->b, tex);
599 }
600
601 static void si_check_render_feedback_textures(struct si_context *sctx,
602 struct si_textures_info *textures)
603 {
604 uint32_t mask = textures->views.enabled_mask;
605
606 while (mask) {
607 const struct pipe_sampler_view *view;
608 struct r600_texture *tex;
609
610 unsigned i = u_bit_scan(&mask);
611
612 view = textures->views.views[i];
613 if(view->texture->target == PIPE_BUFFER)
614 continue;
615
616 tex = (struct r600_texture *)view->texture;
617
618 si_check_render_feedback_texture(sctx, tex,
619 view->u.tex.first_level,
620 view->u.tex.last_level,
621 view->u.tex.first_layer,
622 view->u.tex.last_layer);
623 }
624 }
625
626 static void si_check_render_feedback_images(struct si_context *sctx,
627 struct si_images_info *images)
628 {
629 uint32_t mask = images->enabled_mask;
630
631 while (mask) {
632 const struct pipe_image_view *view;
633 struct r600_texture *tex;
634
635 unsigned i = u_bit_scan(&mask);
636
637 view = &images->views[i];
638 if (view->resource->target == PIPE_BUFFER)
639 continue;
640
641 tex = (struct r600_texture *)view->resource;
642
643 si_check_render_feedback_texture(sctx, tex,
644 view->u.tex.level,
645 view->u.tex.level,
646 view->u.tex.first_layer,
647 view->u.tex.last_layer);
648 }
649 }
650
651 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
652 {
653 util_dynarray_foreach(&sctx->resident_tex_handles,
654 struct si_texture_handle *, tex_handle) {
655 struct pipe_sampler_view *view;
656 struct r600_texture *tex;
657
658 view = (*tex_handle)->view;
659 if (view->texture->target == PIPE_BUFFER)
660 continue;
661
662 tex = (struct r600_texture *)view->texture;
663
664 si_check_render_feedback_texture(sctx, tex,
665 view->u.tex.first_level,
666 view->u.tex.last_level,
667 view->u.tex.first_layer,
668 view->u.tex.last_layer);
669 }
670 }
671
672 static void si_check_render_feedback_resident_images(struct si_context *sctx)
673 {
674 util_dynarray_foreach(&sctx->resident_img_handles,
675 struct si_image_handle *, img_handle) {
676 struct pipe_image_view *view;
677 struct r600_texture *tex;
678
679 view = &(*img_handle)->view;
680 if (view->resource->target == PIPE_BUFFER)
681 continue;
682
683 tex = (struct r600_texture *)view->resource;
684
685 si_check_render_feedback_texture(sctx, tex,
686 view->u.tex.level,
687 view->u.tex.level,
688 view->u.tex.first_layer,
689 view->u.tex.last_layer);
690 }
691 }
692
693 static void si_check_render_feedback(struct si_context *sctx)
694 {
695
696 if (!sctx->need_check_render_feedback)
697 return;
698
699 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
700 si_check_render_feedback_images(sctx, &sctx->images[i]);
701 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
702 }
703
704 si_check_render_feedback_resident_images(sctx);
705 si_check_render_feedback_resident_textures(sctx);
706
707 sctx->need_check_render_feedback = false;
708 }
709
710 static void si_decompress_resident_textures(struct si_context *sctx)
711 {
712 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
713 struct si_texture_handle *, tex_handle) {
714 struct pipe_sampler_view *view = (*tex_handle)->view;
715 struct r600_texture *tex = (struct r600_texture *)view->texture;
716
717 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
718 view->u.tex.last_level);
719 }
720
721 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
722 struct si_texture_handle *, tex_handle) {
723 struct pipe_sampler_view *view = (*tex_handle)->view;
724 struct si_sampler_view *sview = (struct si_sampler_view *)view;
725 struct r600_texture *tex = (struct r600_texture *)view->texture;
726
727 si_decompress_depth(sctx, tex,
728 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
729 view->u.tex.first_level, view->u.tex.last_level,
730 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
731 }
732 }
733
734 static void si_decompress_resident_images(struct si_context *sctx)
735 {
736 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
737 struct si_image_handle *, img_handle) {
738 struct pipe_image_view *view = &(*img_handle)->view;
739 struct r600_texture *tex = (struct r600_texture *)view->resource;
740
741 si_decompress_color_texture(sctx, tex, view->u.tex.level,
742 view->u.tex.level);
743 }
744 }
745
746 static void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
747 {
748 unsigned compressed_colortex_counter, mask;
749
750 if (sctx->blitter->running)
751 return;
752
753 /* Update the compressed_colortex_mask if necessary. */
754 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
755 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
756 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
757 si_update_needs_color_decompress_masks(sctx);
758 }
759
760 /* Decompress color & depth textures if needed. */
761 mask = sctx->shader_needs_decompress_mask & shader_mask;
762 while (mask) {
763 unsigned i = u_bit_scan(&mask);
764
765 if (sctx->samplers[i].needs_depth_decompress_mask) {
766 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
767 }
768 if (sctx->samplers[i].needs_color_decompress_mask) {
769 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
770 }
771 if (sctx->images[i].needs_color_decompress_mask) {
772 si_decompress_image_color_textures(sctx, &sctx->images[i]);
773 }
774 }
775
776 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
777 if (sctx->uses_bindless_samplers)
778 si_decompress_resident_textures(sctx);
779 if (sctx->uses_bindless_images)
780 si_decompress_resident_images(sctx);
781 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
782 if (sctx->cs_shader_state.program->uses_bindless_samplers)
783 si_decompress_resident_textures(sctx);
784 if (sctx->cs_shader_state.program->uses_bindless_images)
785 si_decompress_resident_images(sctx);
786 }
787
788 si_check_render_feedback(sctx);
789 }
790
791 void si_decompress_graphics_textures(struct si_context *sctx)
792 {
793 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
794 }
795
796 void si_decompress_compute_textures(struct si_context *sctx)
797 {
798 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
799 }
800
801 static void si_clear(struct pipe_context *ctx, unsigned buffers,
802 const union pipe_color_union *color,
803 double depth, unsigned stencil)
804 {
805 struct si_context *sctx = (struct si_context *)ctx;
806 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
807 struct pipe_surface *zsbuf = fb->zsbuf;
808 struct r600_texture *zstex =
809 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
810
811 if (buffers & PIPE_CLEAR_COLOR) {
812 evergreen_do_fast_color_clear(&sctx->b, fb,
813 &sctx->framebuffer.atom, &buffers,
814 &sctx->framebuffer.dirty_cbufs,
815 color);
816 if (!buffers)
817 return; /* all buffers have been fast cleared */
818 }
819
820 if (buffers & PIPE_CLEAR_COLOR) {
821 int i;
822
823 /* These buffers cannot use fast clear, make sure to disable expansion. */
824 for (i = 0; i < fb->nr_cbufs; i++) {
825 struct r600_texture *tex;
826
827 /* If not clearing this buffer, skip. */
828 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
829 continue;
830
831 if (!fb->cbufs[i])
832 continue;
833
834 tex = (struct r600_texture *)fb->cbufs[i]->texture;
835 if (tex->fmask.size == 0)
836 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
837 }
838 }
839
840 if (zstex && zstex->htile_offset &&
841 zsbuf->u.tex.level == 0 &&
842 zsbuf->u.tex.first_layer == 0 &&
843 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
844 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
845 if (buffers & PIPE_CLEAR_DEPTH &&
846 (!zstex->tc_compatible_htile ||
847 depth == 0 || depth == 1)) {
848 /* Need to disable EXPCLEAR temporarily if clearing
849 * to a new value. */
850 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
851 sctx->db_depth_disable_expclear = true;
852 }
853
854 zstex->depth_clear_value = depth;
855 sctx->framebuffer.dirty_zsbuf = true;
856 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
857 sctx->db_depth_clear = true;
858 si_mark_atom_dirty(sctx, &sctx->db_render_state);
859 }
860
861 /* TC-compatible HTILE only supports stencil clears to 0. */
862 if (buffers & PIPE_CLEAR_STENCIL &&
863 (!zstex->tc_compatible_htile || stencil == 0)) {
864 stencil &= 0xff;
865
866 /* Need to disable EXPCLEAR temporarily if clearing
867 * to a new value. */
868 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
869 sctx->db_stencil_disable_expclear = true;
870 }
871
872 zstex->stencil_clear_value = stencil;
873 sctx->framebuffer.dirty_zsbuf = true;
874 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
875 sctx->db_stencil_clear = true;
876 si_mark_atom_dirty(sctx, &sctx->db_render_state);
877 }
878 }
879
880 si_blitter_begin(ctx, SI_CLEAR);
881 util_blitter_clear(sctx->blitter, fb->width, fb->height,
882 util_framebuffer_get_num_layers(fb),
883 buffers, color, depth, stencil);
884 si_blitter_end(ctx);
885
886 if (sctx->db_depth_clear) {
887 sctx->db_depth_clear = false;
888 sctx->db_depth_disable_expclear = false;
889 zstex->depth_cleared = true;
890 si_mark_atom_dirty(sctx, &sctx->db_render_state);
891 }
892
893 if (sctx->db_stencil_clear) {
894 sctx->db_stencil_clear = false;
895 sctx->db_stencil_disable_expclear = false;
896 zstex->stencil_cleared = true;
897 si_mark_atom_dirty(sctx, &sctx->db_render_state);
898 }
899 }
900
901 static void si_clear_render_target(struct pipe_context *ctx,
902 struct pipe_surface *dst,
903 const union pipe_color_union *color,
904 unsigned dstx, unsigned dsty,
905 unsigned width, unsigned height,
906 bool render_condition_enabled)
907 {
908 struct si_context *sctx = (struct si_context *)ctx;
909
910 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
911 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
912 util_blitter_clear_render_target(sctx->blitter, dst, color,
913 dstx, dsty, width, height);
914 si_blitter_end(ctx);
915 }
916
917 static void si_clear_depth_stencil(struct pipe_context *ctx,
918 struct pipe_surface *dst,
919 unsigned clear_flags,
920 double depth,
921 unsigned stencil,
922 unsigned dstx, unsigned dsty,
923 unsigned width, unsigned height,
924 bool render_condition_enabled)
925 {
926 struct si_context *sctx = (struct si_context *)ctx;
927
928 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
929 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
930 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
931 dstx, dsty, width, height);
932 si_blitter_end(ctx);
933 }
934
935 /* Helper for decompressing a portion of a color or depth resource before
936 * blitting if any decompression is needed.
937 * The driver doesn't decompress resources automatically while u_blitter is
938 * rendering. */
939 static void si_decompress_subresource(struct pipe_context *ctx,
940 struct pipe_resource *tex,
941 unsigned planes, unsigned level,
942 unsigned first_layer, unsigned last_layer)
943 {
944 struct si_context *sctx = (struct si_context *)ctx;
945 struct r600_texture *rtex = (struct r600_texture*)tex;
946
947 if (rtex->db_compatible) {
948 planes &= PIPE_MASK_Z | PIPE_MASK_S;
949
950 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
951 planes &= ~PIPE_MASK_S;
952
953 si_decompress_depth(sctx, rtex, planes,
954 level, level,
955 first_layer, last_layer);
956 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
957 si_blit_decompress_color(ctx, rtex, level, level,
958 first_layer, last_layer, false);
959 }
960 }
961
962 struct texture_orig_info {
963 unsigned format;
964 unsigned width0;
965 unsigned height0;
966 unsigned npix_x;
967 unsigned npix_y;
968 unsigned npix0_x;
969 unsigned npix0_y;
970 };
971
972 void si_resource_copy_region(struct pipe_context *ctx,
973 struct pipe_resource *dst,
974 unsigned dst_level,
975 unsigned dstx, unsigned dsty, unsigned dstz,
976 struct pipe_resource *src,
977 unsigned src_level,
978 const struct pipe_box *src_box)
979 {
980 struct si_context *sctx = (struct si_context *)ctx;
981 struct r600_texture *rsrc = (struct r600_texture*)src;
982 struct pipe_surface *dst_view, dst_templ;
983 struct pipe_sampler_view src_templ, *src_view;
984 unsigned dst_width, dst_height, src_width0, src_height0;
985 unsigned dst_width0, dst_height0, src_force_level = 0;
986 struct pipe_box sbox, dstbox;
987
988 /* Handle buffers first. */
989 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
990 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
991 return;
992 }
993
994 assert(u_max_sample(dst) == u_max_sample(src));
995
996 /* The driver doesn't decompress resources automatically while
997 * u_blitter is rendering. */
998 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
999 src_box->z, src_box->z + src_box->depth - 1);
1000
1001 dst_width = u_minify(dst->width0, dst_level);
1002 dst_height = u_minify(dst->height0, dst_level);
1003 dst_width0 = dst->width0;
1004 dst_height0 = dst->height0;
1005 src_width0 = src->width0;
1006 src_height0 = src->height0;
1007
1008 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
1009 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
1010
1011 if (util_format_is_compressed(src->format) ||
1012 util_format_is_compressed(dst->format)) {
1013 unsigned blocksize = rsrc->surface.bpe;
1014
1015 if (blocksize == 8)
1016 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
1017 else
1018 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
1019 dst_templ.format = src_templ.format;
1020
1021 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1022 dst_height = util_format_get_nblocksy(dst->format, dst_height);
1023 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1024 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
1025 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1026 src_height0 = util_format_get_nblocksy(src->format, src_height0);
1027
1028 dstx = util_format_get_nblocksx(dst->format, dstx);
1029 dsty = util_format_get_nblocksy(dst->format, dsty);
1030
1031 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1032 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
1033 sbox.z = src_box->z;
1034 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1035 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
1036 sbox.depth = src_box->depth;
1037 src_box = &sbox;
1038
1039 src_force_level = src_level;
1040 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
1041 if (util_format_is_subsampled_422(src->format)) {
1042 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1043 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1044
1045 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1046 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1047 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1048
1049 dstx = util_format_get_nblocksx(dst->format, dstx);
1050
1051 sbox = *src_box;
1052 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1053 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1054 src_box = &sbox;
1055 } else {
1056 unsigned blocksize = rsrc->surface.bpe;
1057
1058 switch (blocksize) {
1059 case 1:
1060 dst_templ.format = PIPE_FORMAT_R8_UNORM;
1061 src_templ.format = PIPE_FORMAT_R8_UNORM;
1062 break;
1063 case 2:
1064 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
1065 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
1066 break;
1067 case 4:
1068 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1069 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1070 break;
1071 case 8:
1072 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1073 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1074 break;
1075 case 16:
1076 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1077 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1078 break;
1079 default:
1080 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1081 util_format_short_name(src->format), blocksize);
1082 assert(0);
1083 }
1084 }
1085 }
1086
1087 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1088 * equivalent instead, which doesn't force DCC decompression.
1089 * Note that some chips avoid this issue by using SDMA.
1090 */
1091 if (util_format_is_snorm8(dst_templ.format)) {
1092 switch (dst_templ.format) {
1093 case PIPE_FORMAT_R8_SNORM:
1094 dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
1095 break;
1096 case PIPE_FORMAT_R8G8_SNORM:
1097 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
1098 break;
1099 case PIPE_FORMAT_R8G8B8X8_SNORM:
1100 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
1101 break;
1102 case PIPE_FORMAT_R8G8B8A8_SNORM:
1103 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1104 case PIPE_FORMAT_A8B8G8R8_SNORM:
1105 case PIPE_FORMAT_X8B8G8R8_SNORM:
1106 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
1107 break;
1108 case PIPE_FORMAT_A8_SNORM:
1109 dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
1110 break;
1111 case PIPE_FORMAT_L8_SNORM:
1112 dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
1113 break;
1114 case PIPE_FORMAT_L8A8_SNORM:
1115 dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
1116 break;
1117 case PIPE_FORMAT_I8_SNORM:
1118 dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
1119 break;
1120 default:; /* fall through */
1121 }
1122 }
1123
1124 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
1125 dst_templ.format);
1126 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
1127 src_templ.format);
1128
1129 /* Initialize the surface. */
1130 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
1131 dst_width0, dst_height0,
1132 dst_width, dst_height);
1133
1134 /* Initialize the sampler view. */
1135 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1136 src_width0, src_height0,
1137 src_force_level);
1138
1139 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1140 abs(src_box->depth), &dstbox);
1141
1142 /* Copy. */
1143 si_blitter_begin(ctx, SI_COPY);
1144 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1145 src_view, src_box, src_width0, src_height0,
1146 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1147 false);
1148 si_blitter_end(ctx);
1149
1150 pipe_surface_reference(&dst_view, NULL);
1151 pipe_sampler_view_reference(&src_view, NULL);
1152 }
1153
1154 static void si_do_CB_resolve(struct si_context *sctx,
1155 const struct pipe_blit_info *info,
1156 struct pipe_resource *dst,
1157 unsigned dst_level, unsigned dst_z,
1158 enum pipe_format format)
1159 {
1160 si_blitter_begin(&sctx->b.b, SI_COLOR_RESOLVE |
1161 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1162 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1163 info->src.resource, info->src.box.z,
1164 ~0, sctx->custom_blend_resolve,
1165 format);
1166 si_blitter_end(&sctx->b.b);
1167 }
1168
1169 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1170 const struct pipe_blit_info *info)
1171 {
1172 struct si_context *sctx = (struct si_context*)ctx;
1173 struct r600_texture *src = (struct r600_texture*)info->src.resource;
1174 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
1175 MAYBE_UNUSED struct r600_texture *rtmp;
1176 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1177 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1178 enum pipe_format format = info->src.format;
1179 struct pipe_resource *tmp, templ;
1180 struct pipe_blit_info blit;
1181
1182 /* Check basic requirements for hw resolve. */
1183 if (!(info->src.resource->nr_samples > 1 &&
1184 info->dst.resource->nr_samples <= 1 &&
1185 !util_format_is_pure_integer(format) &&
1186 !util_format_is_depth_or_stencil(format) &&
1187 util_max_layer(info->src.resource, 0) == 0))
1188 return false;
1189
1190 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1191 * the format is R16G16. Use R16A16, which does work.
1192 */
1193 if (format == PIPE_FORMAT_R16G16_UNORM)
1194 format = PIPE_FORMAT_R16A16_UNORM;
1195 if (format == PIPE_FORMAT_R16G16_SNORM)
1196 format = PIPE_FORMAT_R16A16_SNORM;
1197
1198 /* Check the remaining requirements for hw resolve. */
1199 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1200 !info->scissor_enable &&
1201 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1202 util_is_format_compatible(util_format_description(info->src.format),
1203 util_format_description(info->dst.format)) &&
1204 dst_width == info->src.resource->width0 &&
1205 dst_height == info->src.resource->height0 &&
1206 info->dst.box.x == 0 &&
1207 info->dst.box.y == 0 &&
1208 info->dst.box.width == dst_width &&
1209 info->dst.box.height == dst_height &&
1210 info->dst.box.depth == 1 &&
1211 info->src.box.x == 0 &&
1212 info->src.box.y == 0 &&
1213 info->src.box.width == dst_width &&
1214 info->src.box.height == dst_height &&
1215 info->src.box.depth == 1 &&
1216 !dst->surface.is_linear &&
1217 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1218 /* Check the last constraint. */
1219 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1220 /* The next fast clear will switch to this mode to
1221 * get direct hw resolve next time if the mode is
1222 * different now.
1223 */
1224 src->last_msaa_resolve_target_micro_mode =
1225 dst->surface.micro_tile_mode;
1226 goto resolve_to_temp;
1227 }
1228
1229 /* Resolving into a surface with DCC is unsupported. Since
1230 * it's being overwritten anyway, clear it to uncompressed.
1231 * This is still the fastest codepath even with this clear.
1232 */
1233 if (vi_dcc_enabled(dst, info->dst.level)) {
1234 /* TODO: Implement per-level DCC clears for GFX9. */
1235 if (sctx->b.chip_class >= GFX9 &&
1236 info->dst.resource->last_level != 0)
1237 goto resolve_to_temp;
1238
1239 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1240 0xFFFFFFFF);
1241 dst->dirty_level_mask &= ~(1 << info->dst.level);
1242 }
1243
1244 /* Resolve directly from src to dst. */
1245 si_do_CB_resolve(sctx, info, info->dst.resource,
1246 info->dst.level, info->dst.box.z, format);
1247 return true;
1248 }
1249
1250 resolve_to_temp:
1251 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1252 * a temporary texture and blit.
1253 */
1254 memset(&templ, 0, sizeof(templ));
1255 templ.target = PIPE_TEXTURE_2D;
1256 templ.format = info->src.resource->format;
1257 templ.width0 = info->src.resource->width0;
1258 templ.height0 = info->src.resource->height0;
1259 templ.depth0 = 1;
1260 templ.array_size = 1;
1261 templ.usage = PIPE_USAGE_DEFAULT;
1262 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1263 R600_RESOURCE_FLAG_DISABLE_DCC;
1264
1265 /* The src and dst microtile modes must be the same. */
1266 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1267 templ.bind = PIPE_BIND_SCANOUT;
1268 else
1269 templ.bind = 0;
1270
1271 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1272 if (!tmp)
1273 return false;
1274 rtmp = (struct r600_texture*)tmp;
1275
1276 assert(!rtmp->surface.is_linear);
1277 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1278
1279 /* resolve */
1280 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1281
1282 /* blit */
1283 blit = *info;
1284 blit.src.resource = tmp;
1285 blit.src.box.z = 0;
1286
1287 si_blitter_begin(ctx, SI_BLIT |
1288 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1289 util_blitter_blit(sctx->blitter, &blit);
1290 si_blitter_end(ctx);
1291
1292 pipe_resource_reference(&tmp, NULL);
1293 return true;
1294 }
1295
1296 static void si_blit(struct pipe_context *ctx,
1297 const struct pipe_blit_info *info)
1298 {
1299 struct si_context *sctx = (struct si_context*)ctx;
1300 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1301
1302 if (do_hardware_msaa_resolve(ctx, info)) {
1303 return;
1304 }
1305
1306 /* Using SDMA for copying to a linear texture in GTT is much faster.
1307 * This improves DRI PRIME performance.
1308 *
1309 * resource_copy_region can't do this yet, because dma_copy calls it
1310 * on failure (recursion).
1311 */
1312 if (rdst->surface.is_linear &&
1313 sctx->b.dma_copy &&
1314 util_can_blit_via_copy_region(info, false)) {
1315 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1316 info->dst.box.x, info->dst.box.y,
1317 info->dst.box.z,
1318 info->src.resource, info->src.level,
1319 &info->src.box);
1320 return;
1321 }
1322
1323 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1324
1325 /* The driver doesn't decompress resources automatically while
1326 * u_blitter is rendering. */
1327 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1328 info->src.level,
1329 info->src.format);
1330 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1331 info->dst.level,
1332 info->dst.format);
1333 si_decompress_subresource(ctx, info->src.resource, info->mask,
1334 info->src.level,
1335 info->src.box.z,
1336 info->src.box.z + info->src.box.depth - 1);
1337
1338 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1339 util_try_blit_via_copy_region(ctx, info))
1340 return;
1341
1342 si_blitter_begin(ctx, SI_BLIT |
1343 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1344 util_blitter_blit(sctx->blitter, info);
1345 si_blitter_end(ctx);
1346 }
1347
1348 static boolean si_generate_mipmap(struct pipe_context *ctx,
1349 struct pipe_resource *tex,
1350 enum pipe_format format,
1351 unsigned base_level, unsigned last_level,
1352 unsigned first_layer, unsigned last_layer)
1353 {
1354 struct si_context *sctx = (struct si_context*)ctx;
1355 struct r600_texture *rtex = (struct r600_texture *)tex;
1356
1357 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1358 return false;
1359
1360 /* The driver doesn't decompress resources automatically while
1361 * u_blitter is rendering. */
1362 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1363 format);
1364 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1365 base_level, first_layer, last_layer);
1366
1367 /* Clear dirty_level_mask for the levels that will be overwritten. */
1368 assert(base_level < last_level);
1369 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1370 last_level - base_level);
1371
1372 sctx->generate_mipmap_for_depth = rtex->is_depth;
1373
1374 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1375 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1376 base_level, last_level,
1377 first_layer, last_layer);
1378 si_blitter_end(ctx);
1379
1380 sctx->generate_mipmap_for_depth = false;
1381 return true;
1382 }
1383
1384 static void si_flush_resource(struct pipe_context *ctx,
1385 struct pipe_resource *res)
1386 {
1387 struct r600_texture *rtex = (struct r600_texture*)res;
1388
1389 assert(res->target != PIPE_BUFFER);
1390 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1391
1392 /* st/dri calls flush twice per frame (not a bug), this prevents double
1393 * decompression. */
1394 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1395 return;
1396
1397 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1398 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1399 0, util_max_layer(res, 0),
1400 rtex->dcc_separate_buffer != NULL);
1401 }
1402
1403 /* Always do the analysis even if DCC is disabled at the moment. */
1404 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1405 rtex->separate_dcc_dirty = false;
1406 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1407 }
1408 }
1409
1410 static void si_decompress_dcc(struct pipe_context *ctx,
1411 struct r600_texture *rtex)
1412 {
1413 if (!rtex->dcc_offset)
1414 return;
1415
1416 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1417 0, util_max_layer(&rtex->resource.b.b, 0),
1418 true);
1419 }
1420
1421 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1422 struct pipe_resource *dst,
1423 unsigned offset, unsigned size,
1424 const void *clear_value_ptr,
1425 int clear_value_size)
1426 {
1427 struct si_context *sctx = (struct si_context*)ctx;
1428 uint32_t dword_value;
1429 unsigned i;
1430
1431 assert(offset % clear_value_size == 0);
1432 assert(size % clear_value_size == 0);
1433
1434 if (clear_value_size > 4) {
1435 const uint32_t *u32 = clear_value_ptr;
1436 bool clear_dword_duplicated = true;
1437
1438 /* See if we can lower large fills to dword fills. */
1439 for (i = 1; i < clear_value_size / 4; i++)
1440 if (u32[0] != u32[i]) {
1441 clear_dword_duplicated = false;
1442 break;
1443 }
1444
1445 if (!clear_dword_duplicated) {
1446 /* Use transform feedback for 64-bit, 96-bit, and
1447 * 128-bit fills.
1448 */
1449 union pipe_color_union clear_value;
1450
1451 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1452 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1453 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1454 size, clear_value_size / 4,
1455 &clear_value);
1456 si_blitter_end(ctx);
1457 return;
1458 }
1459 }
1460
1461 /* Expand the clear value to a dword. */
1462 switch (clear_value_size) {
1463 case 1:
1464 dword_value = *(uint8_t*)clear_value_ptr;
1465 dword_value |= (dword_value << 8) |
1466 (dword_value << 16) |
1467 (dword_value << 24);
1468 break;
1469 case 2:
1470 dword_value = *(uint16_t*)clear_value_ptr;
1471 dword_value |= dword_value << 16;
1472 break;
1473 default:
1474 dword_value = *(uint32_t*)clear_value_ptr;
1475 }
1476
1477 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1478 R600_COHERENCY_SHADER);
1479 }
1480
1481 void si_init_blit_functions(struct si_context *sctx)
1482 {
1483 sctx->b.b.clear = si_clear;
1484 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1485 sctx->b.b.clear_render_target = si_clear_render_target;
1486 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1487 sctx->b.b.resource_copy_region = si_resource_copy_region;
1488 sctx->b.b.blit = si_blit;
1489 sctx->b.b.flush_resource = si_flush_resource;
1490 sctx->b.b.generate_mipmap = si_generate_mipmap;
1491 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1492 sctx->b.decompress_dcc = si_decompress_dcc;
1493 }