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radeonsi: use new VS blit shaders (VS inputs in SGPRs)
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_log.h"
28 #include "util/u_surface.h"
29
30 enum si_blitter_op /* bitmask */
31 {
32 SI_SAVE_TEXTURES = 1,
33 SI_SAVE_FRAMEBUFFER = 2,
34 SI_SAVE_FRAGMENT_STATE = 4,
35 SI_DISABLE_RENDER_COND = 8,
36
37 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
38
39 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
40
41 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
42 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
43
44 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
45 SI_SAVE_FRAGMENT_STATE,
46
47 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
48 SI_DISABLE_RENDER_COND,
49
50 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
51 };
52
53 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
54 {
55 struct si_context *sctx = (struct si_context *)ctx;
56
57 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
58 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
59 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
60 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
61 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
62 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
63 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
64 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
65 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
66
67 if (op & SI_SAVE_FRAGMENT_STATE) {
68 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
69 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
70 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
71 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
72 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
73 util_blitter_save_viewport(sctx->blitter, &sctx->viewports.states[0]);
74 util_blitter_save_scissor(sctx->blitter, &sctx->scissors.states[0]);
75 }
76
77 if (op & SI_SAVE_FRAMEBUFFER)
78 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
79
80 if (op & SI_SAVE_TEXTURES) {
81 util_blitter_save_fragment_sampler_states(
82 sctx->blitter, 2,
83 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
84
85 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
86 sctx->samplers[PIPE_SHADER_FRAGMENT].views);
87 }
88
89 if (op & SI_DISABLE_RENDER_COND)
90 sctx->b.render_cond_force_off = true;
91 }
92
93 static void si_blitter_end(struct pipe_context *ctx)
94 {
95 struct si_context *sctx = (struct si_context *)ctx;
96
97 sctx->b.render_cond_force_off = false;
98
99 /* Restore shader pointers because the VS blit shader changed all
100 * non-global VS user SGPRs. */
101 sctx->shader_pointers_dirty |= SI_VS_SHADER_POINTER_MASK;
102 sctx->vertex_buffer_pointer_dirty = true;
103 si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
104 }
105
106 static unsigned u_max_sample(struct pipe_resource *r)
107 {
108 return r->nr_samples ? r->nr_samples - 1 : 0;
109 }
110
111 static unsigned
112 si_blit_dbcb_copy(struct si_context *sctx,
113 struct r600_texture *src,
114 struct r600_texture *dst,
115 unsigned planes, unsigned level_mask,
116 unsigned first_layer, unsigned last_layer,
117 unsigned first_sample, unsigned last_sample)
118 {
119 struct pipe_surface surf_tmpl = {{0}};
120 unsigned layer, sample, checked_last_layer, max_layer;
121 unsigned fully_copied_levels = 0;
122
123 if (planes & PIPE_MASK_Z)
124 sctx->dbcb_depth_copy_enabled = true;
125 if (planes & PIPE_MASK_S)
126 sctx->dbcb_stencil_copy_enabled = true;
127 si_mark_atom_dirty(sctx, &sctx->db_render_state);
128
129 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
130
131 sctx->decompression_enabled = true;
132
133 while (level_mask) {
134 unsigned level = u_bit_scan(&level_mask);
135
136 /* The smaller the mipmap level, the less layers there are
137 * as far as 3D textures are concerned. */
138 max_layer = util_max_layer(&src->resource.b.b, level);
139 checked_last_layer = MIN2(last_layer, max_layer);
140
141 surf_tmpl.u.tex.level = level;
142
143 for (layer = first_layer; layer <= checked_last_layer; layer++) {
144 struct pipe_surface *zsurf, *cbsurf;
145
146 surf_tmpl.format = src->resource.b.b.format;
147 surf_tmpl.u.tex.first_layer = layer;
148 surf_tmpl.u.tex.last_layer = layer;
149
150 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
151
152 surf_tmpl.format = dst->resource.b.b.format;
153 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
154
155 for (sample = first_sample; sample <= last_sample; sample++) {
156 if (sample != sctx->dbcb_copy_sample) {
157 sctx->dbcb_copy_sample = sample;
158 si_mark_atom_dirty(sctx, &sctx->db_render_state);
159 }
160
161 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
162 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
163 sctx->custom_dsa_flush, 1.0f);
164 si_blitter_end(&sctx->b.b);
165 }
166
167 pipe_surface_reference(&zsurf, NULL);
168 pipe_surface_reference(&cbsurf, NULL);
169 }
170
171 if (first_layer == 0 && last_layer >= max_layer &&
172 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
173 fully_copied_levels |= 1u << level;
174 }
175
176 sctx->decompression_enabled = false;
177 sctx->dbcb_depth_copy_enabled = false;
178 sctx->dbcb_stencil_copy_enabled = false;
179 si_mark_atom_dirty(sctx, &sctx->db_render_state);
180
181 return fully_copied_levels;
182 }
183
184 static void si_blit_decompress_depth(struct pipe_context *ctx,
185 struct r600_texture *texture,
186 struct r600_texture *staging,
187 unsigned first_level, unsigned last_level,
188 unsigned first_layer, unsigned last_layer,
189 unsigned first_sample, unsigned last_sample)
190 {
191 const struct util_format_description *desc;
192 unsigned planes = 0;
193
194 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
195
196 desc = util_format_description(staging->resource.b.b.format);
197
198 if (util_format_has_depth(desc))
199 planes |= PIPE_MASK_Z;
200 if (util_format_has_stencil(desc))
201 planes |= PIPE_MASK_S;
202
203 si_blit_dbcb_copy(
204 (struct si_context *)ctx, texture, staging, planes,
205 u_bit_consecutive(first_level, last_level - first_level + 1),
206 first_layer, last_layer, first_sample, last_sample);
207 }
208
209 /* Helper function for si_blit_decompress_zs_in_place.
210 */
211 static void
212 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
213 struct r600_texture *texture,
214 unsigned planes, unsigned level_mask,
215 unsigned first_layer, unsigned last_layer)
216 {
217 struct pipe_surface *zsurf, surf_tmpl = {{0}};
218 unsigned layer, max_layer, checked_last_layer;
219 unsigned fully_decompressed_mask = 0;
220
221 if (!level_mask)
222 return;
223
224 if (planes & PIPE_MASK_S)
225 sctx->db_flush_stencil_inplace = true;
226 if (planes & PIPE_MASK_Z)
227 sctx->db_flush_depth_inplace = true;
228 si_mark_atom_dirty(sctx, &sctx->db_render_state);
229
230 surf_tmpl.format = texture->resource.b.b.format;
231
232 sctx->decompression_enabled = true;
233
234 while (level_mask) {
235 unsigned level = u_bit_scan(&level_mask);
236
237 surf_tmpl.u.tex.level = level;
238
239 /* The smaller the mipmap level, the less layers there are
240 * as far as 3D textures are concerned. */
241 max_layer = util_max_layer(&texture->resource.b.b, level);
242 checked_last_layer = MIN2(last_layer, max_layer);
243
244 for (layer = first_layer; layer <= checked_last_layer; layer++) {
245 surf_tmpl.u.tex.first_layer = layer;
246 surf_tmpl.u.tex.last_layer = layer;
247
248 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
249
250 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
251 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
252 sctx->custom_dsa_flush,
253 1.0f);
254 si_blitter_end(&sctx->b.b);
255
256 pipe_surface_reference(&zsurf, NULL);
257 }
258
259 /* The texture will always be dirty if some layers aren't flushed.
260 * I don't think this case occurs often though. */
261 if (first_layer == 0 && last_layer >= max_layer) {
262 fully_decompressed_mask |= 1u << level;
263 }
264 }
265
266 if (planes & PIPE_MASK_Z)
267 texture->dirty_level_mask &= ~fully_decompressed_mask;
268 if (planes & PIPE_MASK_S)
269 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
270
271 sctx->decompression_enabled = false;
272 sctx->db_flush_depth_inplace = false;
273 sctx->db_flush_stencil_inplace = false;
274 si_mark_atom_dirty(sctx, &sctx->db_render_state);
275 }
276
277 /* Helper function of si_flush_depth_texture: decompress the given levels
278 * of Z and/or S planes in place.
279 */
280 static void
281 si_blit_decompress_zs_in_place(struct si_context *sctx,
282 struct r600_texture *texture,
283 unsigned levels_z, unsigned levels_s,
284 unsigned first_layer, unsigned last_layer)
285 {
286 unsigned both = levels_z & levels_s;
287
288 /* First, do combined Z & S decompresses for levels that need it. */
289 if (both) {
290 si_blit_decompress_zs_planes_in_place(
291 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
292 both,
293 first_layer, last_layer);
294 levels_z &= ~both;
295 levels_s &= ~both;
296 }
297
298 /* Now do separate Z and S decompresses. */
299 if (levels_z) {
300 si_blit_decompress_zs_planes_in_place(
301 sctx, texture, PIPE_MASK_Z,
302 levels_z,
303 first_layer, last_layer);
304 }
305
306 if (levels_s) {
307 si_blit_decompress_zs_planes_in_place(
308 sctx, texture, PIPE_MASK_S,
309 levels_s,
310 first_layer, last_layer);
311 }
312 }
313
314 static void
315 si_decompress_depth(struct si_context *sctx,
316 struct r600_texture *tex,
317 unsigned required_planes,
318 unsigned first_level, unsigned last_level,
319 unsigned first_layer, unsigned last_layer)
320 {
321 unsigned inplace_planes = 0;
322 unsigned copy_planes = 0;
323 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
324 unsigned levels_z = 0;
325 unsigned levels_s = 0;
326
327 if (required_planes & PIPE_MASK_Z) {
328 levels_z = level_mask & tex->dirty_level_mask;
329
330 if (levels_z) {
331 if (r600_can_sample_zs(tex, false))
332 inplace_planes |= PIPE_MASK_Z;
333 else
334 copy_planes |= PIPE_MASK_Z;
335 }
336 }
337 if (required_planes & PIPE_MASK_S) {
338 levels_s = level_mask & tex->stencil_dirty_level_mask;
339
340 if (levels_s) {
341 if (r600_can_sample_zs(tex, true))
342 inplace_planes |= PIPE_MASK_S;
343 else
344 copy_planes |= PIPE_MASK_S;
345 }
346 }
347
348 if (unlikely(sctx->b.log))
349 u_log_printf(sctx->b.log,
350 "\n------------------------------------------------\n"
351 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
352 first_level, last_level, levels_z, levels_s);
353
354 /* We may have to allocate the flushed texture here when called from
355 * si_decompress_subresource.
356 */
357 if (copy_planes &&
358 (tex->flushed_depth_texture ||
359 si_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
360 struct r600_texture *dst = tex->flushed_depth_texture;
361 unsigned fully_copied_levels;
362 unsigned levels = 0;
363
364 assert(tex->flushed_depth_texture);
365
366 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
367 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
368
369 if (copy_planes & PIPE_MASK_Z) {
370 levels |= levels_z;
371 levels_z = 0;
372 }
373 if (copy_planes & PIPE_MASK_S) {
374 levels |= levels_s;
375 levels_s = 0;
376 }
377
378 fully_copied_levels = si_blit_dbcb_copy(
379 sctx, tex, dst, copy_planes, levels,
380 first_layer, last_layer,
381 0, u_max_sample(&tex->resource.b.b));
382
383 if (copy_planes & PIPE_MASK_Z)
384 tex->dirty_level_mask &= ~fully_copied_levels;
385 if (copy_planes & PIPE_MASK_S)
386 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
387 }
388
389 if (inplace_planes) {
390 bool has_htile = r600_htile_enabled(tex, first_level);
391 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
392
393 /* Don't decompress if there is no HTILE or when HTILE is
394 * TC-compatible. */
395 if (has_htile && !tc_compat_htile) {
396 si_blit_decompress_zs_in_place(
397 sctx, tex,
398 levels_z, levels_s,
399 first_layer, last_layer);
400 } else {
401 /* This is only a cache flush.
402 *
403 * Only clear the mask that we are flushing, because
404 * si_make_DB_shader_coherent() treats different levels
405 * and depth and stencil differently.
406 */
407 if (inplace_planes & PIPE_MASK_Z)
408 tex->dirty_level_mask &= ~levels_z;
409 if (inplace_planes & PIPE_MASK_S)
410 tex->stencil_dirty_level_mask &= ~levels_s;
411 }
412
413 /* Only in-place decompression needs to flush DB caches, or
414 * when we don't decompress but TC-compatible planes are dirty.
415 */
416 si_make_DB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
417 inplace_planes & PIPE_MASK_S,
418 tc_compat_htile);
419 }
420 /* set_framebuffer_state takes care of coherency for single-sample.
421 * The DB->CB copy uses CB for the final writes.
422 */
423 if (copy_planes && tex->resource.b.b.nr_samples > 1)
424 si_make_CB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
425 false);
426 }
427
428 static void
429 si_decompress_sampler_depth_textures(struct si_context *sctx,
430 struct si_samplers *textures)
431 {
432 unsigned i;
433 unsigned mask = textures->needs_depth_decompress_mask;
434
435 while (mask) {
436 struct pipe_sampler_view *view;
437 struct si_sampler_view *sview;
438 struct r600_texture *tex;
439
440 i = u_bit_scan(&mask);
441
442 view = textures->views[i];
443 assert(view);
444 sview = (struct si_sampler_view*)view;
445
446 tex = (struct r600_texture *)view->texture;
447 assert(tex->db_compatible);
448
449 si_decompress_depth(sctx, tex,
450 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
451 view->u.tex.first_level, view->u.tex.last_level,
452 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
453 }
454 }
455
456 static void si_blit_decompress_color(struct pipe_context *ctx,
457 struct r600_texture *rtex,
458 unsigned first_level, unsigned last_level,
459 unsigned first_layer, unsigned last_layer,
460 bool need_dcc_decompress)
461 {
462 struct si_context *sctx = (struct si_context *)ctx;
463 void* custom_blend;
464 unsigned layer, checked_last_layer, max_layer;
465 unsigned level_mask =
466 u_bit_consecutive(first_level, last_level - first_level + 1);
467
468 if (!need_dcc_decompress)
469 level_mask &= rtex->dirty_level_mask;
470 if (!level_mask)
471 return;
472
473 if (unlikely(sctx->b.log))
474 u_log_printf(sctx->b.log,
475 "\n------------------------------------------------\n"
476 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
477 first_level, last_level, level_mask);
478
479 if (need_dcc_decompress) {
480 custom_blend = sctx->custom_blend_dcc_decompress;
481
482 assert(rtex->dcc_offset);
483
484 /* disable levels without DCC */
485 for (int i = first_level; i <= last_level; i++) {
486 if (!vi_dcc_enabled(rtex, i))
487 level_mask &= ~(1 << i);
488 }
489 } else if (rtex->fmask.size) {
490 custom_blend = sctx->custom_blend_fmask_decompress;
491 } else {
492 custom_blend = sctx->custom_blend_eliminate_fastclear;
493 }
494
495 sctx->decompression_enabled = true;
496
497 while (level_mask) {
498 unsigned level = u_bit_scan(&level_mask);
499
500 /* The smaller the mipmap level, the less layers there are
501 * as far as 3D textures are concerned. */
502 max_layer = util_max_layer(&rtex->resource.b.b, level);
503 checked_last_layer = MIN2(last_layer, max_layer);
504
505 for (layer = first_layer; layer <= checked_last_layer; layer++) {
506 struct pipe_surface *cbsurf, surf_tmpl;
507
508 surf_tmpl.format = rtex->resource.b.b.format;
509 surf_tmpl.u.tex.level = level;
510 surf_tmpl.u.tex.first_layer = layer;
511 surf_tmpl.u.tex.last_layer = layer;
512 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
513
514 /* Required before and after FMASK and DCC_DECOMPRESS. */
515 if (custom_blend == sctx->custom_blend_fmask_decompress ||
516 custom_blend == sctx->custom_blend_dcc_decompress)
517 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
518
519 si_blitter_begin(ctx, SI_DECOMPRESS);
520 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
521 si_blitter_end(ctx);
522
523 if (custom_blend == sctx->custom_blend_fmask_decompress ||
524 custom_blend == sctx->custom_blend_dcc_decompress)
525 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
526
527 pipe_surface_reference(&cbsurf, NULL);
528 }
529
530 /* The texture will always be dirty if some layers aren't flushed.
531 * I don't think this case occurs often though. */
532 if (first_layer == 0 && last_layer >= max_layer) {
533 rtex->dirty_level_mask &= ~(1 << level);
534 }
535 }
536
537 sctx->decompression_enabled = false;
538 si_make_CB_shader_coherent(sctx, rtex->resource.b.b.nr_samples,
539 vi_dcc_enabled(rtex, first_level));
540 }
541
542 static void
543 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
544 unsigned first_level, unsigned last_level)
545 {
546 /* CMASK or DCC can be discarded and we can still end up here. */
547 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
548 return;
549
550 si_blit_decompress_color(&sctx->b.b, tex, first_level, last_level, 0,
551 util_max_layer(&tex->resource.b.b, first_level),
552 false);
553 }
554
555 static void
556 si_decompress_sampler_color_textures(struct si_context *sctx,
557 struct si_samplers *textures)
558 {
559 unsigned i;
560 unsigned mask = textures->needs_color_decompress_mask;
561
562 while (mask) {
563 struct pipe_sampler_view *view;
564 struct r600_texture *tex;
565
566 i = u_bit_scan(&mask);
567
568 view = textures->views[i];
569 assert(view);
570
571 tex = (struct r600_texture *)view->texture;
572
573 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
574 view->u.tex.last_level);
575 }
576 }
577
578 static void
579 si_decompress_image_color_textures(struct si_context *sctx,
580 struct si_images *images)
581 {
582 unsigned i;
583 unsigned mask = images->needs_color_decompress_mask;
584
585 while (mask) {
586 const struct pipe_image_view *view;
587 struct r600_texture *tex;
588
589 i = u_bit_scan(&mask);
590
591 view = &images->views[i];
592 assert(view->resource->target != PIPE_BUFFER);
593
594 tex = (struct r600_texture *)view->resource;
595
596 si_decompress_color_texture(sctx, tex, view->u.tex.level,
597 view->u.tex.level);
598 }
599 }
600
601 static void si_check_render_feedback_texture(struct si_context *sctx,
602 struct r600_texture *tex,
603 unsigned first_level,
604 unsigned last_level,
605 unsigned first_layer,
606 unsigned last_layer)
607 {
608 bool render_feedback = false;
609
610 if (!tex->dcc_offset)
611 return;
612
613 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
614 struct r600_surface * surf;
615
616 if (!sctx->framebuffer.state.cbufs[j])
617 continue;
618
619 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
620
621 if (tex == (struct r600_texture *)surf->base.texture &&
622 surf->base.u.tex.level >= first_level &&
623 surf->base.u.tex.level <= last_level &&
624 surf->base.u.tex.first_layer <= last_layer &&
625 surf->base.u.tex.last_layer >= first_layer) {
626 render_feedback = true;
627 break;
628 }
629 }
630
631 if (render_feedback)
632 si_texture_disable_dcc(&sctx->b, tex);
633 }
634
635 static void si_check_render_feedback_textures(struct si_context *sctx,
636 struct si_samplers *textures)
637 {
638 uint32_t mask = textures->enabled_mask;
639
640 while (mask) {
641 const struct pipe_sampler_view *view;
642 struct r600_texture *tex;
643
644 unsigned i = u_bit_scan(&mask);
645
646 view = textures->views[i];
647 if(view->texture->target == PIPE_BUFFER)
648 continue;
649
650 tex = (struct r600_texture *)view->texture;
651
652 si_check_render_feedback_texture(sctx, tex,
653 view->u.tex.first_level,
654 view->u.tex.last_level,
655 view->u.tex.first_layer,
656 view->u.tex.last_layer);
657 }
658 }
659
660 static void si_check_render_feedback_images(struct si_context *sctx,
661 struct si_images *images)
662 {
663 uint32_t mask = images->enabled_mask;
664
665 while (mask) {
666 const struct pipe_image_view *view;
667 struct r600_texture *tex;
668
669 unsigned i = u_bit_scan(&mask);
670
671 view = &images->views[i];
672 if (view->resource->target == PIPE_BUFFER)
673 continue;
674
675 tex = (struct r600_texture *)view->resource;
676
677 si_check_render_feedback_texture(sctx, tex,
678 view->u.tex.level,
679 view->u.tex.level,
680 view->u.tex.first_layer,
681 view->u.tex.last_layer);
682 }
683 }
684
685 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
686 {
687 util_dynarray_foreach(&sctx->resident_tex_handles,
688 struct si_texture_handle *, tex_handle) {
689 struct pipe_sampler_view *view;
690 struct r600_texture *tex;
691
692 view = (*tex_handle)->view;
693 if (view->texture->target == PIPE_BUFFER)
694 continue;
695
696 tex = (struct r600_texture *)view->texture;
697
698 si_check_render_feedback_texture(sctx, tex,
699 view->u.tex.first_level,
700 view->u.tex.last_level,
701 view->u.tex.first_layer,
702 view->u.tex.last_layer);
703 }
704 }
705
706 static void si_check_render_feedback_resident_images(struct si_context *sctx)
707 {
708 util_dynarray_foreach(&sctx->resident_img_handles,
709 struct si_image_handle *, img_handle) {
710 struct pipe_image_view *view;
711 struct r600_texture *tex;
712
713 view = &(*img_handle)->view;
714 if (view->resource->target == PIPE_BUFFER)
715 continue;
716
717 tex = (struct r600_texture *)view->resource;
718
719 si_check_render_feedback_texture(sctx, tex,
720 view->u.tex.level,
721 view->u.tex.level,
722 view->u.tex.first_layer,
723 view->u.tex.last_layer);
724 }
725 }
726
727 static void si_check_render_feedback(struct si_context *sctx)
728 {
729
730 if (!sctx->need_check_render_feedback)
731 return;
732
733 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
734 si_check_render_feedback_images(sctx, &sctx->images[i]);
735 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
736 }
737
738 si_check_render_feedback_resident_images(sctx);
739 si_check_render_feedback_resident_textures(sctx);
740
741 sctx->need_check_render_feedback = false;
742 }
743
744 static void si_decompress_resident_textures(struct si_context *sctx)
745 {
746 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
747 struct si_texture_handle *, tex_handle) {
748 struct pipe_sampler_view *view = (*tex_handle)->view;
749 struct r600_texture *tex = (struct r600_texture *)view->texture;
750
751 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
752 view->u.tex.last_level);
753 }
754
755 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
756 struct si_texture_handle *, tex_handle) {
757 struct pipe_sampler_view *view = (*tex_handle)->view;
758 struct si_sampler_view *sview = (struct si_sampler_view *)view;
759 struct r600_texture *tex = (struct r600_texture *)view->texture;
760
761 si_decompress_depth(sctx, tex,
762 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
763 view->u.tex.first_level, view->u.tex.last_level,
764 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
765 }
766 }
767
768 static void si_decompress_resident_images(struct si_context *sctx)
769 {
770 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
771 struct si_image_handle *, img_handle) {
772 struct pipe_image_view *view = &(*img_handle)->view;
773 struct r600_texture *tex = (struct r600_texture *)view->resource;
774
775 si_decompress_color_texture(sctx, tex, view->u.tex.level,
776 view->u.tex.level);
777 }
778 }
779
780 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
781 {
782 unsigned compressed_colortex_counter, mask;
783
784 if (sctx->blitter->running)
785 return;
786
787 /* Update the compressed_colortex_mask if necessary. */
788 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
789 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
790 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
791 si_update_needs_color_decompress_masks(sctx);
792 }
793
794 /* Decompress color & depth textures if needed. */
795 mask = sctx->shader_needs_decompress_mask & shader_mask;
796 while (mask) {
797 unsigned i = u_bit_scan(&mask);
798
799 if (sctx->samplers[i].needs_depth_decompress_mask) {
800 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
801 }
802 if (sctx->samplers[i].needs_color_decompress_mask) {
803 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
804 }
805 if (sctx->images[i].needs_color_decompress_mask) {
806 si_decompress_image_color_textures(sctx, &sctx->images[i]);
807 }
808 }
809
810 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
811 if (sctx->uses_bindless_samplers)
812 si_decompress_resident_textures(sctx);
813 if (sctx->uses_bindless_images)
814 si_decompress_resident_images(sctx);
815 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
816 if (sctx->cs_shader_state.program->uses_bindless_samplers)
817 si_decompress_resident_textures(sctx);
818 if (sctx->cs_shader_state.program->uses_bindless_images)
819 si_decompress_resident_images(sctx);
820 }
821
822 si_check_render_feedback(sctx);
823 }
824
825 static void si_clear(struct pipe_context *ctx, unsigned buffers,
826 const union pipe_color_union *color,
827 double depth, unsigned stencil)
828 {
829 struct si_context *sctx = (struct si_context *)ctx;
830 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
831 struct pipe_surface *zsbuf = fb->zsbuf;
832 struct r600_texture *zstex =
833 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
834
835 if (buffers & PIPE_CLEAR_COLOR) {
836 si_do_fast_color_clear(&sctx->b, fb,
837 &sctx->framebuffer.atom, &buffers,
838 &sctx->framebuffer.dirty_cbufs,
839 color);
840 if (!buffers)
841 return; /* all buffers have been fast cleared */
842 }
843
844 if (buffers & PIPE_CLEAR_COLOR) {
845 int i;
846
847 /* These buffers cannot use fast clear, make sure to disable expansion. */
848 for (i = 0; i < fb->nr_cbufs; i++) {
849 struct r600_texture *tex;
850
851 /* If not clearing this buffer, skip. */
852 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
853 continue;
854
855 if (!fb->cbufs[i])
856 continue;
857
858 tex = (struct r600_texture *)fb->cbufs[i]->texture;
859 if (tex->fmask.size == 0)
860 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
861 }
862 }
863
864 if (zstex &&
865 r600_htile_enabled(zstex, zsbuf->u.tex.level) &&
866 zsbuf->u.tex.first_layer == 0 &&
867 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
868 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
869 if (buffers & PIPE_CLEAR_DEPTH &&
870 (!zstex->tc_compatible_htile ||
871 depth == 0 || depth == 1)) {
872 /* Need to disable EXPCLEAR temporarily if clearing
873 * to a new value. */
874 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
875 sctx->db_depth_disable_expclear = true;
876 }
877
878 zstex->depth_clear_value = depth;
879 sctx->framebuffer.dirty_zsbuf = true;
880 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
881 sctx->db_depth_clear = true;
882 si_mark_atom_dirty(sctx, &sctx->db_render_state);
883 }
884
885 /* TC-compatible HTILE only supports stencil clears to 0. */
886 if (buffers & PIPE_CLEAR_STENCIL &&
887 (!zstex->tc_compatible_htile || stencil == 0)) {
888 stencil &= 0xff;
889
890 /* Need to disable EXPCLEAR temporarily if clearing
891 * to a new value. */
892 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
893 sctx->db_stencil_disable_expclear = true;
894 }
895
896 zstex->stencil_clear_value = stencil;
897 sctx->framebuffer.dirty_zsbuf = true;
898 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
899 sctx->db_stencil_clear = true;
900 si_mark_atom_dirty(sctx, &sctx->db_render_state);
901 }
902
903 /* TODO: Find out what's wrong here. Fast depth clear leads to
904 * corruption in ARK: Survival Evolved, but that may just be
905 * a coincidence and the root cause is elsewhere.
906 *
907 * The corruption can be fixed by putting the DB metadata flush
908 * before or after the depth clear. (suprisingly)
909 *
910 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
911 *
912 * This hack decreases back-to-back ClearDepth performance.
913 */
914 if (sctx->screen->clear_db_meta_before_clear)
915 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META |
916 SI_CONTEXT_PS_PARTIAL_FLUSH;
917 }
918
919 si_blitter_begin(ctx, SI_CLEAR);
920 util_blitter_clear(sctx->blitter, fb->width, fb->height,
921 util_framebuffer_get_num_layers(fb),
922 buffers, color, depth, stencil);
923 si_blitter_end(ctx);
924
925 if (sctx->db_depth_clear) {
926 sctx->db_depth_clear = false;
927 sctx->db_depth_disable_expclear = false;
928 zstex->depth_cleared = true;
929 si_mark_atom_dirty(sctx, &sctx->db_render_state);
930 }
931
932 if (sctx->db_stencil_clear) {
933 sctx->db_stencil_clear = false;
934 sctx->db_stencil_disable_expclear = false;
935 zstex->stencil_cleared = true;
936 si_mark_atom_dirty(sctx, &sctx->db_render_state);
937 }
938 }
939
940 static void si_clear_render_target(struct pipe_context *ctx,
941 struct pipe_surface *dst,
942 const union pipe_color_union *color,
943 unsigned dstx, unsigned dsty,
944 unsigned width, unsigned height,
945 bool render_condition_enabled)
946 {
947 struct si_context *sctx = (struct si_context *)ctx;
948
949 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
950 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
951 util_blitter_clear_render_target(sctx->blitter, dst, color,
952 dstx, dsty, width, height);
953 si_blitter_end(ctx);
954 }
955
956 static void si_clear_depth_stencil(struct pipe_context *ctx,
957 struct pipe_surface *dst,
958 unsigned clear_flags,
959 double depth,
960 unsigned stencil,
961 unsigned dstx, unsigned dsty,
962 unsigned width, unsigned height,
963 bool render_condition_enabled)
964 {
965 struct si_context *sctx = (struct si_context *)ctx;
966
967 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
968 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
969 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
970 dstx, dsty, width, height);
971 si_blitter_end(ctx);
972 }
973
974 /* Helper for decompressing a portion of a color or depth resource before
975 * blitting if any decompression is needed.
976 * The driver doesn't decompress resources automatically while u_blitter is
977 * rendering. */
978 static void si_decompress_subresource(struct pipe_context *ctx,
979 struct pipe_resource *tex,
980 unsigned planes, unsigned level,
981 unsigned first_layer, unsigned last_layer)
982 {
983 struct si_context *sctx = (struct si_context *)ctx;
984 struct r600_texture *rtex = (struct r600_texture*)tex;
985
986 if (rtex->db_compatible) {
987 planes &= PIPE_MASK_Z | PIPE_MASK_S;
988
989 if (!rtex->surface.has_stencil)
990 planes &= ~PIPE_MASK_S;
991
992 /* If we've rendered into the framebuffer and it's a blitting
993 * source, make sure the decompression pass is invoked
994 * by dirtying the framebuffer.
995 */
996 if (sctx->framebuffer.state.zsbuf &&
997 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
998 sctx->framebuffer.state.zsbuf->texture == tex)
999 si_update_fb_dirtiness_after_rendering(sctx);
1000
1001 si_decompress_depth(sctx, rtex, planes,
1002 level, level,
1003 first_layer, last_layer);
1004 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
1005 /* If we've rendered into the framebuffer and it's a blitting
1006 * source, make sure the decompression pass is invoked
1007 * by dirtying the framebuffer.
1008 */
1009 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
1010 if (sctx->framebuffer.state.cbufs[i] &&
1011 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
1012 sctx->framebuffer.state.cbufs[i]->texture == tex) {
1013 si_update_fb_dirtiness_after_rendering(sctx);
1014 break;
1015 }
1016 }
1017
1018 si_blit_decompress_color(ctx, rtex, level, level,
1019 first_layer, last_layer, false);
1020 }
1021 }
1022
1023 struct texture_orig_info {
1024 unsigned format;
1025 unsigned width0;
1026 unsigned height0;
1027 unsigned npix_x;
1028 unsigned npix_y;
1029 unsigned npix0_x;
1030 unsigned npix0_y;
1031 };
1032
1033 void si_resource_copy_region(struct pipe_context *ctx,
1034 struct pipe_resource *dst,
1035 unsigned dst_level,
1036 unsigned dstx, unsigned dsty, unsigned dstz,
1037 struct pipe_resource *src,
1038 unsigned src_level,
1039 const struct pipe_box *src_box)
1040 {
1041 struct si_context *sctx = (struct si_context *)ctx;
1042 struct r600_texture *rsrc = (struct r600_texture*)src;
1043 struct pipe_surface *dst_view, dst_templ;
1044 struct pipe_sampler_view src_templ, *src_view;
1045 unsigned dst_width, dst_height, src_width0, src_height0;
1046 unsigned dst_width0, dst_height0, src_force_level = 0;
1047 struct pipe_box sbox, dstbox;
1048
1049 /* Handle buffers first. */
1050 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
1051 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
1052 return;
1053 }
1054
1055 assert(u_max_sample(dst) == u_max_sample(src));
1056
1057 /* The driver doesn't decompress resources automatically while
1058 * u_blitter is rendering. */
1059 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
1060 src_box->z, src_box->z + src_box->depth - 1);
1061
1062 dst_width = u_minify(dst->width0, dst_level);
1063 dst_height = u_minify(dst->height0, dst_level);
1064 dst_width0 = dst->width0;
1065 dst_height0 = dst->height0;
1066 src_width0 = src->width0;
1067 src_height0 = src->height0;
1068
1069 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
1070 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
1071
1072 if (util_format_is_compressed(src->format) ||
1073 util_format_is_compressed(dst->format)) {
1074 unsigned blocksize = rsrc->surface.bpe;
1075
1076 if (blocksize == 8)
1077 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
1078 else
1079 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
1080 dst_templ.format = src_templ.format;
1081
1082 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1083 dst_height = util_format_get_nblocksy(dst->format, dst_height);
1084 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1085 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
1086 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1087 src_height0 = util_format_get_nblocksy(src->format, src_height0);
1088
1089 dstx = util_format_get_nblocksx(dst->format, dstx);
1090 dsty = util_format_get_nblocksy(dst->format, dsty);
1091
1092 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1093 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
1094 sbox.z = src_box->z;
1095 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1096 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
1097 sbox.depth = src_box->depth;
1098 src_box = &sbox;
1099
1100 src_force_level = src_level;
1101 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
1102 if (util_format_is_subsampled_422(src->format)) {
1103 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1104 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1105
1106 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1107 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1108 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1109
1110 dstx = util_format_get_nblocksx(dst->format, dstx);
1111
1112 sbox = *src_box;
1113 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1114 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1115 src_box = &sbox;
1116 } else {
1117 unsigned blocksize = rsrc->surface.bpe;
1118
1119 switch (blocksize) {
1120 case 1:
1121 dst_templ.format = PIPE_FORMAT_R8_UNORM;
1122 src_templ.format = PIPE_FORMAT_R8_UNORM;
1123 break;
1124 case 2:
1125 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
1126 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
1127 break;
1128 case 4:
1129 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1130 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1131 break;
1132 case 8:
1133 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1134 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1135 break;
1136 case 16:
1137 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1138 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1139 break;
1140 default:
1141 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1142 util_format_short_name(src->format), blocksize);
1143 assert(0);
1144 }
1145 }
1146 }
1147
1148 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1149 * equivalent instead, which doesn't force DCC decompression.
1150 * Note that some chips avoid this issue by using SDMA.
1151 */
1152 if (util_format_is_snorm8(dst_templ.format)) {
1153 switch (dst_templ.format) {
1154 case PIPE_FORMAT_R8_SNORM:
1155 dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
1156 break;
1157 case PIPE_FORMAT_R8G8_SNORM:
1158 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
1159 break;
1160 case PIPE_FORMAT_R8G8B8X8_SNORM:
1161 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
1162 break;
1163 case PIPE_FORMAT_R8G8B8A8_SNORM:
1164 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1165 case PIPE_FORMAT_A8B8G8R8_SNORM:
1166 case PIPE_FORMAT_X8B8G8R8_SNORM:
1167 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
1168 break;
1169 case PIPE_FORMAT_A8_SNORM:
1170 dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
1171 break;
1172 case PIPE_FORMAT_L8_SNORM:
1173 dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
1174 break;
1175 case PIPE_FORMAT_L8A8_SNORM:
1176 dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
1177 break;
1178 case PIPE_FORMAT_I8_SNORM:
1179 dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
1180 break;
1181 default:; /* fall through */
1182 }
1183 }
1184
1185 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
1186 dst_templ.format);
1187 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
1188 src_templ.format);
1189
1190 /* Initialize the surface. */
1191 dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
1192 dst_width0, dst_height0,
1193 dst_width, dst_height);
1194
1195 /* Initialize the sampler view. */
1196 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1197 src_width0, src_height0,
1198 src_force_level);
1199
1200 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1201 abs(src_box->depth), &dstbox);
1202
1203 /* Copy. */
1204 si_blitter_begin(ctx, SI_COPY);
1205 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1206 src_view, src_box, src_width0, src_height0,
1207 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1208 false);
1209 si_blitter_end(ctx);
1210
1211 pipe_surface_reference(&dst_view, NULL);
1212 pipe_sampler_view_reference(&src_view, NULL);
1213 }
1214
1215 static void si_do_CB_resolve(struct si_context *sctx,
1216 const struct pipe_blit_info *info,
1217 struct pipe_resource *dst,
1218 unsigned dst_level, unsigned dst_z,
1219 enum pipe_format format)
1220 {
1221 /* Required before and after CB_RESOLVE. */
1222 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1223
1224 si_blitter_begin(&sctx->b.b, SI_COLOR_RESOLVE |
1225 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1226 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1227 info->src.resource, info->src.box.z,
1228 ~0, sctx->custom_blend_resolve,
1229 format);
1230 si_blitter_end(&sctx->b.b);
1231
1232 /* Flush caches for possible texturing. */
1233 si_make_CB_shader_coherent(sctx, 1, false);
1234 }
1235
1236 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1237 const struct pipe_blit_info *info)
1238 {
1239 struct si_context *sctx = (struct si_context*)ctx;
1240 struct r600_texture *src = (struct r600_texture*)info->src.resource;
1241 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
1242 MAYBE_UNUSED struct r600_texture *rtmp;
1243 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1244 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1245 enum pipe_format format = info->src.format;
1246 struct pipe_resource *tmp, templ;
1247 struct pipe_blit_info blit;
1248
1249 /* Check basic requirements for hw resolve. */
1250 if (!(info->src.resource->nr_samples > 1 &&
1251 info->dst.resource->nr_samples <= 1 &&
1252 !util_format_is_pure_integer(format) &&
1253 !util_format_is_depth_or_stencil(format) &&
1254 util_max_layer(info->src.resource, 0) == 0))
1255 return false;
1256
1257 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1258 * the format is R16G16. Use R16A16, which does work.
1259 */
1260 if (format == PIPE_FORMAT_R16G16_UNORM)
1261 format = PIPE_FORMAT_R16A16_UNORM;
1262 if (format == PIPE_FORMAT_R16G16_SNORM)
1263 format = PIPE_FORMAT_R16A16_SNORM;
1264
1265 /* Check the remaining requirements for hw resolve. */
1266 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1267 !info->scissor_enable &&
1268 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1269 util_is_format_compatible(util_format_description(info->src.format),
1270 util_format_description(info->dst.format)) &&
1271 dst_width == info->src.resource->width0 &&
1272 dst_height == info->src.resource->height0 &&
1273 info->dst.box.x == 0 &&
1274 info->dst.box.y == 0 &&
1275 info->dst.box.width == dst_width &&
1276 info->dst.box.height == dst_height &&
1277 info->dst.box.depth == 1 &&
1278 info->src.box.x == 0 &&
1279 info->src.box.y == 0 &&
1280 info->src.box.width == dst_width &&
1281 info->src.box.height == dst_height &&
1282 info->src.box.depth == 1 &&
1283 !dst->surface.is_linear &&
1284 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1285 /* Check the last constraint. */
1286 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1287 /* The next fast clear will switch to this mode to
1288 * get direct hw resolve next time if the mode is
1289 * different now.
1290 */
1291 src->last_msaa_resolve_target_micro_mode =
1292 dst->surface.micro_tile_mode;
1293 goto resolve_to_temp;
1294 }
1295
1296 /* Resolving into a surface with DCC is unsupported. Since
1297 * it's being overwritten anyway, clear it to uncompressed.
1298 * This is still the fastest codepath even with this clear.
1299 */
1300 if (vi_dcc_enabled(dst, info->dst.level)) {
1301 /* TODO: Implement per-level DCC clears for GFX9. */
1302 if (sctx->b.chip_class >= GFX9 &&
1303 info->dst.resource->last_level != 0)
1304 goto resolve_to_temp;
1305
1306 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1307 0xFFFFFFFF);
1308 dst->dirty_level_mask &= ~(1 << info->dst.level);
1309 }
1310
1311 /* Resolve directly from src to dst. */
1312 si_do_CB_resolve(sctx, info, info->dst.resource,
1313 info->dst.level, info->dst.box.z, format);
1314 return true;
1315 }
1316
1317 resolve_to_temp:
1318 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1319 * a temporary texture and blit.
1320 */
1321 memset(&templ, 0, sizeof(templ));
1322 templ.target = PIPE_TEXTURE_2D;
1323 templ.format = info->src.resource->format;
1324 templ.width0 = info->src.resource->width0;
1325 templ.height0 = info->src.resource->height0;
1326 templ.depth0 = 1;
1327 templ.array_size = 1;
1328 templ.usage = PIPE_USAGE_DEFAULT;
1329 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1330 R600_RESOURCE_FLAG_DISABLE_DCC;
1331
1332 /* The src and dst microtile modes must be the same. */
1333 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1334 templ.bind = PIPE_BIND_SCANOUT;
1335 else
1336 templ.bind = 0;
1337
1338 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1339 if (!tmp)
1340 return false;
1341 rtmp = (struct r600_texture*)tmp;
1342
1343 assert(!rtmp->surface.is_linear);
1344 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1345
1346 /* resolve */
1347 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1348
1349 /* blit */
1350 blit = *info;
1351 blit.src.resource = tmp;
1352 blit.src.box.z = 0;
1353
1354 si_blitter_begin(ctx, SI_BLIT |
1355 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1356 util_blitter_blit(sctx->blitter, &blit);
1357 si_blitter_end(ctx);
1358
1359 pipe_resource_reference(&tmp, NULL);
1360 return true;
1361 }
1362
1363 static void si_blit(struct pipe_context *ctx,
1364 const struct pipe_blit_info *info)
1365 {
1366 struct si_context *sctx = (struct si_context*)ctx;
1367 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1368
1369 if (do_hardware_msaa_resolve(ctx, info)) {
1370 return;
1371 }
1372
1373 /* Using SDMA for copying to a linear texture in GTT is much faster.
1374 * This improves DRI PRIME performance.
1375 *
1376 * resource_copy_region can't do this yet, because dma_copy calls it
1377 * on failure (recursion).
1378 */
1379 if (rdst->surface.is_linear &&
1380 sctx->b.dma_copy &&
1381 util_can_blit_via_copy_region(info, false)) {
1382 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1383 info->dst.box.x, info->dst.box.y,
1384 info->dst.box.z,
1385 info->src.resource, info->src.level,
1386 &info->src.box);
1387 return;
1388 }
1389
1390 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1391
1392 /* The driver doesn't decompress resources automatically while
1393 * u_blitter is rendering. */
1394 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1395 info->src.level,
1396 info->src.format);
1397 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1398 info->dst.level,
1399 info->dst.format);
1400 si_decompress_subresource(ctx, info->src.resource, info->mask,
1401 info->src.level,
1402 info->src.box.z,
1403 info->src.box.z + info->src.box.depth - 1);
1404
1405 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1406 util_try_blit_via_copy_region(ctx, info))
1407 return;
1408
1409 si_blitter_begin(ctx, SI_BLIT |
1410 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1411 util_blitter_blit(sctx->blitter, info);
1412 si_blitter_end(ctx);
1413 }
1414
1415 static boolean si_generate_mipmap(struct pipe_context *ctx,
1416 struct pipe_resource *tex,
1417 enum pipe_format format,
1418 unsigned base_level, unsigned last_level,
1419 unsigned first_layer, unsigned last_layer)
1420 {
1421 struct si_context *sctx = (struct si_context*)ctx;
1422 struct r600_texture *rtex = (struct r600_texture *)tex;
1423
1424 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1425 return false;
1426
1427 /* The driver doesn't decompress resources automatically while
1428 * u_blitter is rendering. */
1429 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1430 format);
1431 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1432 base_level, first_layer, last_layer);
1433
1434 /* Clear dirty_level_mask for the levels that will be overwritten. */
1435 assert(base_level < last_level);
1436 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1437 last_level - base_level);
1438
1439 sctx->generate_mipmap_for_depth = rtex->is_depth;
1440
1441 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1442 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1443 base_level, last_level,
1444 first_layer, last_layer);
1445 si_blitter_end(ctx);
1446
1447 sctx->generate_mipmap_for_depth = false;
1448 return true;
1449 }
1450
1451 static void si_flush_resource(struct pipe_context *ctx,
1452 struct pipe_resource *res)
1453 {
1454 struct r600_texture *rtex = (struct r600_texture*)res;
1455
1456 assert(res->target != PIPE_BUFFER);
1457 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1458
1459 /* st/dri calls flush twice per frame (not a bug), this prevents double
1460 * decompression. */
1461 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1462 return;
1463
1464 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1465 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1466 0, util_max_layer(res, 0),
1467 rtex->dcc_separate_buffer != NULL);
1468 }
1469
1470 /* Always do the analysis even if DCC is disabled at the moment. */
1471 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1472 rtex->separate_dcc_dirty = false;
1473 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1474 }
1475 }
1476
1477 static void si_decompress_dcc(struct pipe_context *ctx,
1478 struct r600_texture *rtex)
1479 {
1480 if (!rtex->dcc_offset)
1481 return;
1482
1483 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1484 0, util_max_layer(&rtex->resource.b.b, 0),
1485 true);
1486 }
1487
1488 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1489 struct pipe_resource *dst,
1490 unsigned offset, unsigned size,
1491 const void *clear_value_ptr,
1492 int clear_value_size)
1493 {
1494 struct si_context *sctx = (struct si_context*)ctx;
1495 uint32_t dword_value;
1496 unsigned i;
1497
1498 assert(offset % clear_value_size == 0);
1499 assert(size % clear_value_size == 0);
1500
1501 if (clear_value_size > 4) {
1502 const uint32_t *u32 = clear_value_ptr;
1503 bool clear_dword_duplicated = true;
1504
1505 /* See if we can lower large fills to dword fills. */
1506 for (i = 1; i < clear_value_size / 4; i++)
1507 if (u32[0] != u32[i]) {
1508 clear_dword_duplicated = false;
1509 break;
1510 }
1511
1512 if (!clear_dword_duplicated) {
1513 /* Use transform feedback for 64-bit, 96-bit, and
1514 * 128-bit fills.
1515 */
1516 union pipe_color_union clear_value;
1517
1518 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1519 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1520 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1521 size, clear_value_size / 4,
1522 &clear_value);
1523 si_blitter_end(ctx);
1524 return;
1525 }
1526 }
1527
1528 /* Expand the clear value to a dword. */
1529 switch (clear_value_size) {
1530 case 1:
1531 dword_value = *(uint8_t*)clear_value_ptr;
1532 dword_value |= (dword_value << 8) |
1533 (dword_value << 16) |
1534 (dword_value << 24);
1535 break;
1536 case 2:
1537 dword_value = *(uint16_t*)clear_value_ptr;
1538 dword_value |= dword_value << 16;
1539 break;
1540 default:
1541 dword_value = *(uint32_t*)clear_value_ptr;
1542 }
1543
1544 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1545 R600_COHERENCY_SHADER);
1546 }
1547
1548 void si_init_blit_functions(struct si_context *sctx)
1549 {
1550 sctx->b.b.clear = si_clear;
1551 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1552 sctx->b.b.clear_render_target = si_clear_render_target;
1553 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1554 sctx->b.b.resource_copy_region = si_resource_copy_region;
1555 sctx->b.b.blit = si_blit;
1556 sctx->b.b.flush_resource = si_flush_resource;
1557 sctx->b.b.generate_mipmap = si_generate_mipmap;
1558 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1559 sctx->b.decompress_dcc = si_decompress_dcc;
1560 }