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radeonsi: rename r600_texture::resource to buffer
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_compute.h"
28 #include "util/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
34 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
35
36 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
37 SI_SAVE_FRAGMENT_STATE,
38
39 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
40 SI_DISABLE_RENDER_COND,
41
42 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
43 };
44
45 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op)
46 {
47 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
48 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
49 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
50 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
51 util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets,
52 (struct pipe_stream_output_target**)sctx->streamout.targets);
53 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
54
55 if (op & SI_SAVE_FRAGMENT_STATE) {
56 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
57 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
58 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
59 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
60 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask);
61 util_blitter_save_scissor(sctx->blitter, &sctx->scissors.states[0]);
62 }
63
64 if (op & SI_SAVE_FRAMEBUFFER)
65 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
66
67 if (op & SI_SAVE_TEXTURES) {
68 util_blitter_save_fragment_sampler_states(
69 sctx->blitter, 2,
70 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
71
72 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
73 sctx->samplers[PIPE_SHADER_FRAGMENT].views);
74 }
75
76 if (op & SI_DISABLE_RENDER_COND)
77 sctx->render_cond_force_off = true;
78 }
79
80 void si_blitter_end(struct si_context *sctx)
81 {
82 sctx->render_cond_force_off = false;
83
84 /* Restore shader pointers because the VS blit shader changed all
85 * non-global VS user SGPRs. */
86 sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX);
87 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
88 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
89 }
90
91 static unsigned u_max_sample(struct pipe_resource *r)
92 {
93 return r->nr_samples ? r->nr_samples - 1 : 0;
94 }
95
96 static unsigned
97 si_blit_dbcb_copy(struct si_context *sctx,
98 struct r600_texture *src,
99 struct r600_texture *dst,
100 unsigned planes, unsigned level_mask,
101 unsigned first_layer, unsigned last_layer,
102 unsigned first_sample, unsigned last_sample)
103 {
104 struct pipe_surface surf_tmpl = {{0}};
105 unsigned layer, sample, checked_last_layer, max_layer;
106 unsigned fully_copied_levels = 0;
107
108 if (planes & PIPE_MASK_Z)
109 sctx->dbcb_depth_copy_enabled = true;
110 if (planes & PIPE_MASK_S)
111 sctx->dbcb_stencil_copy_enabled = true;
112 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
113
114 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
115
116 sctx->decompression_enabled = true;
117
118 while (level_mask) {
119 unsigned level = u_bit_scan(&level_mask);
120
121 /* The smaller the mipmap level, the less layers there are
122 * as far as 3D textures are concerned. */
123 max_layer = util_max_layer(&src->buffer.b.b, level);
124 checked_last_layer = MIN2(last_layer, max_layer);
125
126 surf_tmpl.u.tex.level = level;
127
128 for (layer = first_layer; layer <= checked_last_layer; layer++) {
129 struct pipe_surface *zsurf, *cbsurf;
130
131 surf_tmpl.format = src->buffer.b.b.format;
132 surf_tmpl.u.tex.first_layer = layer;
133 surf_tmpl.u.tex.last_layer = layer;
134
135 zsurf = sctx->b.create_surface(&sctx->b, &src->buffer.b.b, &surf_tmpl);
136
137 surf_tmpl.format = dst->buffer.b.b.format;
138 cbsurf = sctx->b.create_surface(&sctx->b, &dst->buffer.b.b, &surf_tmpl);
139
140 for (sample = first_sample; sample <= last_sample; sample++) {
141 if (sample != sctx->dbcb_copy_sample) {
142 sctx->dbcb_copy_sample = sample;
143 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
144 }
145
146 si_blitter_begin(sctx, SI_DECOMPRESS);
147 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
148 sctx->custom_dsa_flush, 1.0f);
149 si_blitter_end(sctx);
150 }
151
152 pipe_surface_reference(&zsurf, NULL);
153 pipe_surface_reference(&cbsurf, NULL);
154 }
155
156 if (first_layer == 0 && last_layer >= max_layer &&
157 first_sample == 0 && last_sample >= u_max_sample(&src->buffer.b.b))
158 fully_copied_levels |= 1u << level;
159 }
160
161 sctx->decompression_enabled = false;
162 sctx->dbcb_depth_copy_enabled = false;
163 sctx->dbcb_stencil_copy_enabled = false;
164 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
165
166 return fully_copied_levels;
167 }
168
169 void si_blit_decompress_depth(struct pipe_context *ctx,
170 struct r600_texture *texture,
171 struct r600_texture *staging,
172 unsigned first_level, unsigned last_level,
173 unsigned first_layer, unsigned last_layer,
174 unsigned first_sample, unsigned last_sample)
175 {
176 const struct util_format_description *desc;
177 unsigned planes = 0;
178
179 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
180
181 desc = util_format_description(staging->buffer.b.b.format);
182
183 if (util_format_has_depth(desc))
184 planes |= PIPE_MASK_Z;
185 if (util_format_has_stencil(desc))
186 planes |= PIPE_MASK_S;
187
188 si_blit_dbcb_copy(
189 (struct si_context *)ctx, texture, staging, planes,
190 u_bit_consecutive(first_level, last_level - first_level + 1),
191 first_layer, last_layer, first_sample, last_sample);
192 }
193
194 /* Helper function for si_blit_decompress_zs_in_place.
195 */
196 static void
197 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
198 struct r600_texture *texture,
199 unsigned planes, unsigned level_mask,
200 unsigned first_layer, unsigned last_layer)
201 {
202 struct pipe_surface *zsurf, surf_tmpl = {{0}};
203 unsigned layer, max_layer, checked_last_layer;
204 unsigned fully_decompressed_mask = 0;
205
206 if (!level_mask)
207 return;
208
209 if (planes & PIPE_MASK_S)
210 sctx->db_flush_stencil_inplace = true;
211 if (planes & PIPE_MASK_Z)
212 sctx->db_flush_depth_inplace = true;
213 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
214
215 surf_tmpl.format = texture->buffer.b.b.format;
216
217 sctx->decompression_enabled = true;
218
219 while (level_mask) {
220 unsigned level = u_bit_scan(&level_mask);
221
222 surf_tmpl.u.tex.level = level;
223
224 /* The smaller the mipmap level, the less layers there are
225 * as far as 3D textures are concerned. */
226 max_layer = util_max_layer(&texture->buffer.b.b, level);
227 checked_last_layer = MIN2(last_layer, max_layer);
228
229 for (layer = first_layer; layer <= checked_last_layer; layer++) {
230 surf_tmpl.u.tex.first_layer = layer;
231 surf_tmpl.u.tex.last_layer = layer;
232
233 zsurf = sctx->b.create_surface(&sctx->b, &texture->buffer.b.b, &surf_tmpl);
234
235 si_blitter_begin(sctx, SI_DECOMPRESS);
236 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
237 sctx->custom_dsa_flush,
238 1.0f);
239 si_blitter_end(sctx);
240
241 pipe_surface_reference(&zsurf, NULL);
242 }
243
244 /* The texture will always be dirty if some layers aren't flushed.
245 * I don't think this case occurs often though. */
246 if (first_layer == 0 && last_layer >= max_layer) {
247 fully_decompressed_mask |= 1u << level;
248 }
249 }
250
251 if (planes & PIPE_MASK_Z)
252 texture->dirty_level_mask &= ~fully_decompressed_mask;
253 if (planes & PIPE_MASK_S)
254 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
255
256 sctx->decompression_enabled = false;
257 sctx->db_flush_depth_inplace = false;
258 sctx->db_flush_stencil_inplace = false;
259 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
260 }
261
262 /* Helper function of si_flush_depth_texture: decompress the given levels
263 * of Z and/or S planes in place.
264 */
265 static void
266 si_blit_decompress_zs_in_place(struct si_context *sctx,
267 struct r600_texture *texture,
268 unsigned levels_z, unsigned levels_s,
269 unsigned first_layer, unsigned last_layer)
270 {
271 unsigned both = levels_z & levels_s;
272
273 /* First, do combined Z & S decompresses for levels that need it. */
274 if (both) {
275 si_blit_decompress_zs_planes_in_place(
276 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
277 both,
278 first_layer, last_layer);
279 levels_z &= ~both;
280 levels_s &= ~both;
281 }
282
283 /* Now do separate Z and S decompresses. */
284 if (levels_z) {
285 si_blit_decompress_zs_planes_in_place(
286 sctx, texture, PIPE_MASK_Z,
287 levels_z,
288 first_layer, last_layer);
289 }
290
291 if (levels_s) {
292 si_blit_decompress_zs_planes_in_place(
293 sctx, texture, PIPE_MASK_S,
294 levels_s,
295 first_layer, last_layer);
296 }
297 }
298
299 static void
300 si_decompress_depth(struct si_context *sctx,
301 struct r600_texture *tex,
302 unsigned required_planes,
303 unsigned first_level, unsigned last_level,
304 unsigned first_layer, unsigned last_layer)
305 {
306 unsigned inplace_planes = 0;
307 unsigned copy_planes = 0;
308 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
309 unsigned levels_z = 0;
310 unsigned levels_s = 0;
311
312 if (required_planes & PIPE_MASK_Z) {
313 levels_z = level_mask & tex->dirty_level_mask;
314
315 if (levels_z) {
316 if (si_can_sample_zs(tex, false))
317 inplace_planes |= PIPE_MASK_Z;
318 else
319 copy_planes |= PIPE_MASK_Z;
320 }
321 }
322 if (required_planes & PIPE_MASK_S) {
323 levels_s = level_mask & tex->stencil_dirty_level_mask;
324
325 if (levels_s) {
326 if (si_can_sample_zs(tex, true))
327 inplace_planes |= PIPE_MASK_S;
328 else
329 copy_planes |= PIPE_MASK_S;
330 }
331 }
332
333 if (unlikely(sctx->log))
334 u_log_printf(sctx->log,
335 "\n------------------------------------------------\n"
336 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
337 first_level, last_level, levels_z, levels_s);
338
339 /* We may have to allocate the flushed texture here when called from
340 * si_decompress_subresource.
341 */
342 if (copy_planes &&
343 (tex->flushed_depth_texture ||
344 si_init_flushed_depth_texture(&sctx->b, &tex->buffer.b.b, NULL))) {
345 struct r600_texture *dst = tex->flushed_depth_texture;
346 unsigned fully_copied_levels;
347 unsigned levels = 0;
348
349 assert(tex->flushed_depth_texture);
350
351 if (util_format_is_depth_and_stencil(dst->buffer.b.b.format))
352 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
353
354 if (copy_planes & PIPE_MASK_Z) {
355 levels |= levels_z;
356 levels_z = 0;
357 }
358 if (copy_planes & PIPE_MASK_S) {
359 levels |= levels_s;
360 levels_s = 0;
361 }
362
363 fully_copied_levels = si_blit_dbcb_copy(
364 sctx, tex, dst, copy_planes, levels,
365 first_layer, last_layer,
366 0, u_max_sample(&tex->buffer.b.b));
367
368 if (copy_planes & PIPE_MASK_Z)
369 tex->dirty_level_mask &= ~fully_copied_levels;
370 if (copy_planes & PIPE_MASK_S)
371 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
372 }
373
374 if (inplace_planes) {
375 bool has_htile = si_htile_enabled(tex, first_level);
376 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
377
378 /* Don't decompress if there is no HTILE or when HTILE is
379 * TC-compatible. */
380 if (has_htile && !tc_compat_htile) {
381 si_blit_decompress_zs_in_place(
382 sctx, tex,
383 levels_z, levels_s,
384 first_layer, last_layer);
385 } else {
386 /* This is only a cache flush.
387 *
388 * Only clear the mask that we are flushing, because
389 * si_make_DB_shader_coherent() treats different levels
390 * and depth and stencil differently.
391 */
392 if (inplace_planes & PIPE_MASK_Z)
393 tex->dirty_level_mask &= ~levels_z;
394 if (inplace_planes & PIPE_MASK_S)
395 tex->stencil_dirty_level_mask &= ~levels_s;
396 }
397
398 /* Only in-place decompression needs to flush DB caches, or
399 * when we don't decompress but TC-compatible planes are dirty.
400 */
401 si_make_DB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
402 inplace_planes & PIPE_MASK_S,
403 tc_compat_htile);
404 }
405 /* set_framebuffer_state takes care of coherency for single-sample.
406 * The DB->CB copy uses CB for the final writes.
407 */
408 if (copy_planes && tex->buffer.b.b.nr_samples > 1)
409 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
410 false);
411 }
412
413 static void
414 si_decompress_sampler_depth_textures(struct si_context *sctx,
415 struct si_samplers *textures)
416 {
417 unsigned i;
418 unsigned mask = textures->needs_depth_decompress_mask;
419
420 while (mask) {
421 struct pipe_sampler_view *view;
422 struct si_sampler_view *sview;
423 struct r600_texture *tex;
424
425 i = u_bit_scan(&mask);
426
427 view = textures->views[i];
428 assert(view);
429 sview = (struct si_sampler_view*)view;
430
431 tex = (struct r600_texture *)view->texture;
432 assert(tex->db_compatible);
433
434 si_decompress_depth(sctx, tex,
435 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
436 view->u.tex.first_level, view->u.tex.last_level,
437 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
438 }
439 }
440
441 static void si_blit_decompress_color(struct si_context *sctx,
442 struct r600_texture *rtex,
443 unsigned first_level, unsigned last_level,
444 unsigned first_layer, unsigned last_layer,
445 bool need_dcc_decompress)
446 {
447 void* custom_blend;
448 unsigned layer, checked_last_layer, max_layer;
449 unsigned level_mask =
450 u_bit_consecutive(first_level, last_level - first_level + 1);
451
452 if (!need_dcc_decompress)
453 level_mask &= rtex->dirty_level_mask;
454 if (!level_mask)
455 return;
456
457 if (unlikely(sctx->log))
458 u_log_printf(sctx->log,
459 "\n------------------------------------------------\n"
460 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
461 first_level, last_level, level_mask);
462
463 if (need_dcc_decompress) {
464 custom_blend = sctx->custom_blend_dcc_decompress;
465
466 assert(rtex->dcc_offset);
467
468 /* disable levels without DCC */
469 for (int i = first_level; i <= last_level; i++) {
470 if (!vi_dcc_enabled(rtex, i))
471 level_mask &= ~(1 << i);
472 }
473 } else if (rtex->fmask.size) {
474 custom_blend = sctx->custom_blend_fmask_decompress;
475 } else {
476 custom_blend = sctx->custom_blend_eliminate_fastclear;
477 }
478
479 sctx->decompression_enabled = true;
480
481 while (level_mask) {
482 unsigned level = u_bit_scan(&level_mask);
483
484 /* The smaller the mipmap level, the less layers there are
485 * as far as 3D textures are concerned. */
486 max_layer = util_max_layer(&rtex->buffer.b.b, level);
487 checked_last_layer = MIN2(last_layer, max_layer);
488
489 for (layer = first_layer; layer <= checked_last_layer; layer++) {
490 struct pipe_surface *cbsurf, surf_tmpl;
491
492 surf_tmpl.format = rtex->buffer.b.b.format;
493 surf_tmpl.u.tex.level = level;
494 surf_tmpl.u.tex.first_layer = layer;
495 surf_tmpl.u.tex.last_layer = layer;
496 cbsurf = sctx->b.create_surface(&sctx->b, &rtex->buffer.b.b, &surf_tmpl);
497
498 /* Required before and after FMASK and DCC_DECOMPRESS. */
499 if (custom_blend == sctx->custom_blend_fmask_decompress ||
500 custom_blend == sctx->custom_blend_dcc_decompress)
501 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
502
503 si_blitter_begin(sctx, SI_DECOMPRESS);
504 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
505 si_blitter_end(sctx);
506
507 if (custom_blend == sctx->custom_blend_fmask_decompress ||
508 custom_blend == sctx->custom_blend_dcc_decompress)
509 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
510
511 pipe_surface_reference(&cbsurf, NULL);
512 }
513
514 /* The texture will always be dirty if some layers aren't flushed.
515 * I don't think this case occurs often though. */
516 if (first_layer == 0 && last_layer >= max_layer) {
517 rtex->dirty_level_mask &= ~(1 << level);
518 }
519 }
520
521 sctx->decompression_enabled = false;
522 si_make_CB_shader_coherent(sctx, rtex->buffer.b.b.nr_samples,
523 vi_dcc_enabled(rtex, first_level));
524 }
525
526 static void
527 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
528 unsigned first_level, unsigned last_level)
529 {
530 /* CMASK or DCC can be discarded and we can still end up here. */
531 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
532 return;
533
534 si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
535 util_max_layer(&tex->buffer.b.b, first_level),
536 false);
537 }
538
539 static void
540 si_decompress_sampler_color_textures(struct si_context *sctx,
541 struct si_samplers *textures)
542 {
543 unsigned i;
544 unsigned mask = textures->needs_color_decompress_mask;
545
546 while (mask) {
547 struct pipe_sampler_view *view;
548 struct r600_texture *tex;
549
550 i = u_bit_scan(&mask);
551
552 view = textures->views[i];
553 assert(view);
554
555 tex = (struct r600_texture *)view->texture;
556
557 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
558 view->u.tex.last_level);
559 }
560 }
561
562 static void
563 si_decompress_image_color_textures(struct si_context *sctx,
564 struct si_images *images)
565 {
566 unsigned i;
567 unsigned mask = images->needs_color_decompress_mask;
568
569 while (mask) {
570 const struct pipe_image_view *view;
571 struct r600_texture *tex;
572
573 i = u_bit_scan(&mask);
574
575 view = &images->views[i];
576 assert(view->resource->target != PIPE_BUFFER);
577
578 tex = (struct r600_texture *)view->resource;
579
580 si_decompress_color_texture(sctx, tex, view->u.tex.level,
581 view->u.tex.level);
582 }
583 }
584
585 static void si_check_render_feedback_texture(struct si_context *sctx,
586 struct r600_texture *tex,
587 unsigned first_level,
588 unsigned last_level,
589 unsigned first_layer,
590 unsigned last_layer)
591 {
592 bool render_feedback = false;
593
594 if (!tex->dcc_offset)
595 return;
596
597 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
598 struct r600_surface * surf;
599
600 if (!sctx->framebuffer.state.cbufs[j])
601 continue;
602
603 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
604
605 if (tex == (struct r600_texture *)surf->base.texture &&
606 surf->base.u.tex.level >= first_level &&
607 surf->base.u.tex.level <= last_level &&
608 surf->base.u.tex.first_layer <= last_layer &&
609 surf->base.u.tex.last_layer >= first_layer) {
610 render_feedback = true;
611 break;
612 }
613 }
614
615 if (render_feedback)
616 si_texture_disable_dcc(sctx, tex);
617 }
618
619 static void si_check_render_feedback_textures(struct si_context *sctx,
620 struct si_samplers *textures)
621 {
622 uint32_t mask = textures->enabled_mask;
623
624 while (mask) {
625 const struct pipe_sampler_view *view;
626 struct r600_texture *tex;
627
628 unsigned i = u_bit_scan(&mask);
629
630 view = textures->views[i];
631 if(view->texture->target == PIPE_BUFFER)
632 continue;
633
634 tex = (struct r600_texture *)view->texture;
635
636 si_check_render_feedback_texture(sctx, tex,
637 view->u.tex.first_level,
638 view->u.tex.last_level,
639 view->u.tex.first_layer,
640 view->u.tex.last_layer);
641 }
642 }
643
644 static void si_check_render_feedback_images(struct si_context *sctx,
645 struct si_images *images)
646 {
647 uint32_t mask = images->enabled_mask;
648
649 while (mask) {
650 const struct pipe_image_view *view;
651 struct r600_texture *tex;
652
653 unsigned i = u_bit_scan(&mask);
654
655 view = &images->views[i];
656 if (view->resource->target == PIPE_BUFFER)
657 continue;
658
659 tex = (struct r600_texture *)view->resource;
660
661 si_check_render_feedback_texture(sctx, tex,
662 view->u.tex.level,
663 view->u.tex.level,
664 view->u.tex.first_layer,
665 view->u.tex.last_layer);
666 }
667 }
668
669 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
670 {
671 util_dynarray_foreach(&sctx->resident_tex_handles,
672 struct si_texture_handle *, tex_handle) {
673 struct pipe_sampler_view *view;
674 struct r600_texture *tex;
675
676 view = (*tex_handle)->view;
677 if (view->texture->target == PIPE_BUFFER)
678 continue;
679
680 tex = (struct r600_texture *)view->texture;
681
682 si_check_render_feedback_texture(sctx, tex,
683 view->u.tex.first_level,
684 view->u.tex.last_level,
685 view->u.tex.first_layer,
686 view->u.tex.last_layer);
687 }
688 }
689
690 static void si_check_render_feedback_resident_images(struct si_context *sctx)
691 {
692 util_dynarray_foreach(&sctx->resident_img_handles,
693 struct si_image_handle *, img_handle) {
694 struct pipe_image_view *view;
695 struct r600_texture *tex;
696
697 view = &(*img_handle)->view;
698 if (view->resource->target == PIPE_BUFFER)
699 continue;
700
701 tex = (struct r600_texture *)view->resource;
702
703 si_check_render_feedback_texture(sctx, tex,
704 view->u.tex.level,
705 view->u.tex.level,
706 view->u.tex.first_layer,
707 view->u.tex.last_layer);
708 }
709 }
710
711 static void si_check_render_feedback(struct si_context *sctx)
712 {
713 if (!sctx->need_check_render_feedback)
714 return;
715
716 /* There is no render feedback if color writes are disabled.
717 * (e.g. a pixel shader with image stores)
718 */
719 if (!si_get_total_colormask(sctx))
720 return;
721
722 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
723 si_check_render_feedback_images(sctx, &sctx->images[i]);
724 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
725 }
726
727 si_check_render_feedback_resident_images(sctx);
728 si_check_render_feedback_resident_textures(sctx);
729
730 sctx->need_check_render_feedback = false;
731 }
732
733 static void si_decompress_resident_textures(struct si_context *sctx)
734 {
735 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
736 struct si_texture_handle *, tex_handle) {
737 struct pipe_sampler_view *view = (*tex_handle)->view;
738 struct r600_texture *tex = (struct r600_texture *)view->texture;
739
740 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
741 view->u.tex.last_level);
742 }
743
744 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
745 struct si_texture_handle *, tex_handle) {
746 struct pipe_sampler_view *view = (*tex_handle)->view;
747 struct si_sampler_view *sview = (struct si_sampler_view *)view;
748 struct r600_texture *tex = (struct r600_texture *)view->texture;
749
750 si_decompress_depth(sctx, tex,
751 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
752 view->u.tex.first_level, view->u.tex.last_level,
753 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
754 }
755 }
756
757 static void si_decompress_resident_images(struct si_context *sctx)
758 {
759 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
760 struct si_image_handle *, img_handle) {
761 struct pipe_image_view *view = &(*img_handle)->view;
762 struct r600_texture *tex = (struct r600_texture *)view->resource;
763
764 si_decompress_color_texture(sctx, tex, view->u.tex.level,
765 view->u.tex.level);
766 }
767 }
768
769 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
770 {
771 unsigned compressed_colortex_counter, mask;
772
773 if (sctx->blitter->running)
774 return;
775
776 /* Update the compressed_colortex_mask if necessary. */
777 compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter);
778 if (compressed_colortex_counter != sctx->last_compressed_colortex_counter) {
779 sctx->last_compressed_colortex_counter = compressed_colortex_counter;
780 si_update_needs_color_decompress_masks(sctx);
781 }
782
783 /* Decompress color & depth textures if needed. */
784 mask = sctx->shader_needs_decompress_mask & shader_mask;
785 while (mask) {
786 unsigned i = u_bit_scan(&mask);
787
788 if (sctx->samplers[i].needs_depth_decompress_mask) {
789 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
790 }
791 if (sctx->samplers[i].needs_color_decompress_mask) {
792 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
793 }
794 if (sctx->images[i].needs_color_decompress_mask) {
795 si_decompress_image_color_textures(sctx, &sctx->images[i]);
796 }
797 }
798
799 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
800 if (sctx->uses_bindless_samplers)
801 si_decompress_resident_textures(sctx);
802 if (sctx->uses_bindless_images)
803 si_decompress_resident_images(sctx);
804
805 if (sctx->ps_uses_fbfetch) {
806 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
807 si_decompress_color_texture(sctx,
808 (struct r600_texture*)cb0->texture,
809 cb0->u.tex.first_layer,
810 cb0->u.tex.last_layer);
811 }
812
813 si_check_render_feedback(sctx);
814 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
815 if (sctx->cs_shader_state.program->uses_bindless_samplers)
816 si_decompress_resident_textures(sctx);
817 if (sctx->cs_shader_state.program->uses_bindless_images)
818 si_decompress_resident_images(sctx);
819 }
820 }
821
822 /* Helper for decompressing a portion of a color or depth resource before
823 * blitting if any decompression is needed.
824 * The driver doesn't decompress resources automatically while u_blitter is
825 * rendering. */
826 static void si_decompress_subresource(struct pipe_context *ctx,
827 struct pipe_resource *tex,
828 unsigned planes, unsigned level,
829 unsigned first_layer, unsigned last_layer)
830 {
831 struct si_context *sctx = (struct si_context *)ctx;
832 struct r600_texture *rtex = (struct r600_texture*)tex;
833
834 if (rtex->db_compatible) {
835 planes &= PIPE_MASK_Z | PIPE_MASK_S;
836
837 if (!rtex->surface.has_stencil)
838 planes &= ~PIPE_MASK_S;
839
840 /* If we've rendered into the framebuffer and it's a blitting
841 * source, make sure the decompression pass is invoked
842 * by dirtying the framebuffer.
843 */
844 if (sctx->framebuffer.state.zsbuf &&
845 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
846 sctx->framebuffer.state.zsbuf->texture == tex)
847 si_update_fb_dirtiness_after_rendering(sctx);
848
849 si_decompress_depth(sctx, rtex, planes,
850 level, level,
851 first_layer, last_layer);
852 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
853 /* If we've rendered into the framebuffer and it's a blitting
854 * source, make sure the decompression pass is invoked
855 * by dirtying the framebuffer.
856 */
857 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
858 if (sctx->framebuffer.state.cbufs[i] &&
859 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
860 sctx->framebuffer.state.cbufs[i]->texture == tex) {
861 si_update_fb_dirtiness_after_rendering(sctx);
862 break;
863 }
864 }
865
866 si_blit_decompress_color(sctx, rtex, level, level,
867 first_layer, last_layer, false);
868 }
869 }
870
871 struct texture_orig_info {
872 unsigned format;
873 unsigned width0;
874 unsigned height0;
875 unsigned npix_x;
876 unsigned npix_y;
877 unsigned npix0_x;
878 unsigned npix0_y;
879 };
880
881 void si_resource_copy_region(struct pipe_context *ctx,
882 struct pipe_resource *dst,
883 unsigned dst_level,
884 unsigned dstx, unsigned dsty, unsigned dstz,
885 struct pipe_resource *src,
886 unsigned src_level,
887 const struct pipe_box *src_box)
888 {
889 struct si_context *sctx = (struct si_context *)ctx;
890 struct r600_texture *rsrc = (struct r600_texture*)src;
891 struct pipe_surface *dst_view, dst_templ;
892 struct pipe_sampler_view src_templ, *src_view;
893 unsigned dst_width, dst_height, src_width0, src_height0;
894 unsigned dst_width0, dst_height0, src_force_level = 0;
895 struct pipe_box sbox, dstbox;
896
897 /* Handle buffers first. */
898 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
899 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
900 return;
901 }
902
903 assert(u_max_sample(dst) == u_max_sample(src));
904
905 /* The driver doesn't decompress resources automatically while
906 * u_blitter is rendering. */
907 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
908 src_box->z, src_box->z + src_box->depth - 1);
909
910 dst_width = u_minify(dst->width0, dst_level);
911 dst_height = u_minify(dst->height0, dst_level);
912 dst_width0 = dst->width0;
913 dst_height0 = dst->height0;
914 src_width0 = src->width0;
915 src_height0 = src->height0;
916
917 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
918 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
919
920 if (util_format_is_compressed(src->format) ||
921 util_format_is_compressed(dst->format)) {
922 unsigned blocksize = rsrc->surface.bpe;
923
924 if (blocksize == 8)
925 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
926 else
927 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
928 dst_templ.format = src_templ.format;
929
930 dst_width = util_format_get_nblocksx(dst->format, dst_width);
931 dst_height = util_format_get_nblocksy(dst->format, dst_height);
932 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
933 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
934 src_width0 = util_format_get_nblocksx(src->format, src_width0);
935 src_height0 = util_format_get_nblocksy(src->format, src_height0);
936
937 dstx = util_format_get_nblocksx(dst->format, dstx);
938 dsty = util_format_get_nblocksy(dst->format, dsty);
939
940 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
941 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
942 sbox.z = src_box->z;
943 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
944 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
945 sbox.depth = src_box->depth;
946 src_box = &sbox;
947
948 src_force_level = src_level;
949 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
950 if (util_format_is_subsampled_422(src->format)) {
951 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
952 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
953
954 dst_width = util_format_get_nblocksx(dst->format, dst_width);
955 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
956 src_width0 = util_format_get_nblocksx(src->format, src_width0);
957
958 dstx = util_format_get_nblocksx(dst->format, dstx);
959
960 sbox = *src_box;
961 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
962 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
963 src_box = &sbox;
964 } else {
965 unsigned blocksize = rsrc->surface.bpe;
966
967 switch (blocksize) {
968 case 1:
969 dst_templ.format = PIPE_FORMAT_R8_UNORM;
970 src_templ.format = PIPE_FORMAT_R8_UNORM;
971 break;
972 case 2:
973 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
974 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
975 break;
976 case 4:
977 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
978 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
979 break;
980 case 8:
981 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
982 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
983 break;
984 case 16:
985 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
986 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
987 break;
988 default:
989 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
990 util_format_short_name(src->format), blocksize);
991 assert(0);
992 }
993 }
994 }
995
996 /* SNORM8 blitting has precision issues on some chips. Use the SINT
997 * equivalent instead, which doesn't force DCC decompression.
998 * Note that some chips avoid this issue by using SDMA.
999 */
1000 if (util_format_is_snorm8(dst_templ.format)) {
1001 switch (dst_templ.format) {
1002 case PIPE_FORMAT_R8_SNORM:
1003 dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
1004 break;
1005 case PIPE_FORMAT_R8G8_SNORM:
1006 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
1007 break;
1008 case PIPE_FORMAT_R8G8B8X8_SNORM:
1009 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
1010 break;
1011 case PIPE_FORMAT_R8G8B8A8_SNORM:
1012 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1013 case PIPE_FORMAT_A8B8G8R8_SNORM:
1014 case PIPE_FORMAT_X8B8G8R8_SNORM:
1015 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
1016 break;
1017 case PIPE_FORMAT_A8_SNORM:
1018 dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
1019 break;
1020 case PIPE_FORMAT_L8_SNORM:
1021 dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
1022 break;
1023 case PIPE_FORMAT_L8A8_SNORM:
1024 dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
1025 break;
1026 case PIPE_FORMAT_I8_SNORM:
1027 dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
1028 break;
1029 default:; /* fall through */
1030 }
1031 }
1032
1033 vi_disable_dcc_if_incompatible_format(sctx, dst, dst_level,
1034 dst_templ.format);
1035 vi_disable_dcc_if_incompatible_format(sctx, src, src_level,
1036 src_templ.format);
1037
1038 /* Initialize the surface. */
1039 dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
1040 dst_width0, dst_height0,
1041 dst_width, dst_height);
1042
1043 /* Initialize the sampler view. */
1044 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1045 src_width0, src_height0,
1046 src_force_level);
1047
1048 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1049 abs(src_box->depth), &dstbox);
1050
1051 /* Copy. */
1052 si_blitter_begin(sctx, SI_COPY);
1053 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1054 src_view, src_box, src_width0, src_height0,
1055 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1056 false);
1057 si_blitter_end(sctx);
1058
1059 pipe_surface_reference(&dst_view, NULL);
1060 pipe_sampler_view_reference(&src_view, NULL);
1061 }
1062
1063 static void si_do_CB_resolve(struct si_context *sctx,
1064 const struct pipe_blit_info *info,
1065 struct pipe_resource *dst,
1066 unsigned dst_level, unsigned dst_z,
1067 enum pipe_format format)
1068 {
1069 /* Required before and after CB_RESOLVE. */
1070 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1071
1072 si_blitter_begin(sctx, SI_COLOR_RESOLVE |
1073 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1074 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1075 info->src.resource, info->src.box.z,
1076 ~0, sctx->custom_blend_resolve,
1077 format);
1078 si_blitter_end(sctx);
1079
1080 /* Flush caches for possible texturing. */
1081 si_make_CB_shader_coherent(sctx, 1, false);
1082 }
1083
1084 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1085 const struct pipe_blit_info *info)
1086 {
1087 struct si_context *sctx = (struct si_context*)ctx;
1088 struct r600_texture *src = (struct r600_texture*)info->src.resource;
1089 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
1090 MAYBE_UNUSED struct r600_texture *rtmp;
1091 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1092 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1093 enum pipe_format format = info->src.format;
1094 struct pipe_resource *tmp, templ;
1095 struct pipe_blit_info blit;
1096
1097 /* Check basic requirements for hw resolve. */
1098 if (!(info->src.resource->nr_samples > 1 &&
1099 info->dst.resource->nr_samples <= 1 &&
1100 !util_format_is_pure_integer(format) &&
1101 !util_format_is_depth_or_stencil(format) &&
1102 util_max_layer(info->src.resource, 0) == 0))
1103 return false;
1104
1105 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1106 * the format is R16G16. Use R16A16, which does work.
1107 */
1108 if (format == PIPE_FORMAT_R16G16_UNORM)
1109 format = PIPE_FORMAT_R16A16_UNORM;
1110 if (format == PIPE_FORMAT_R16G16_SNORM)
1111 format = PIPE_FORMAT_R16A16_SNORM;
1112
1113 /* Check the remaining requirements for hw resolve. */
1114 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1115 !info->scissor_enable &&
1116 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1117 util_is_format_compatible(util_format_description(info->src.format),
1118 util_format_description(info->dst.format)) &&
1119 dst_width == info->src.resource->width0 &&
1120 dst_height == info->src.resource->height0 &&
1121 info->dst.box.x == 0 &&
1122 info->dst.box.y == 0 &&
1123 info->dst.box.width == dst_width &&
1124 info->dst.box.height == dst_height &&
1125 info->dst.box.depth == 1 &&
1126 info->src.box.x == 0 &&
1127 info->src.box.y == 0 &&
1128 info->src.box.width == dst_width &&
1129 info->src.box.height == dst_height &&
1130 info->src.box.depth == 1 &&
1131 !dst->surface.is_linear &&
1132 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1133 /* Check the last constraint. */
1134 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1135 /* The next fast clear will switch to this mode to
1136 * get direct hw resolve next time if the mode is
1137 * different now.
1138 */
1139 src->last_msaa_resolve_target_micro_mode =
1140 dst->surface.micro_tile_mode;
1141 goto resolve_to_temp;
1142 }
1143
1144 /* Resolving into a surface with DCC is unsupported. Since
1145 * it's being overwritten anyway, clear it to uncompressed.
1146 * This is still the fastest codepath even with this clear.
1147 */
1148 if (vi_dcc_enabled(dst, info->dst.level)) {
1149 /* TODO: Implement per-level DCC clears for GFX9. */
1150 if (sctx->chip_class >= GFX9 &&
1151 info->dst.resource->last_level != 0)
1152 goto resolve_to_temp;
1153
1154 vi_dcc_clear_level(sctx, dst, info->dst.level,
1155 0xFFFFFFFF);
1156 dst->dirty_level_mask &= ~(1 << info->dst.level);
1157 }
1158
1159 /* Resolve directly from src to dst. */
1160 si_do_CB_resolve(sctx, info, info->dst.resource,
1161 info->dst.level, info->dst.box.z, format);
1162 return true;
1163 }
1164
1165 resolve_to_temp:
1166 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1167 * a temporary texture and blit.
1168 */
1169 memset(&templ, 0, sizeof(templ));
1170 templ.target = PIPE_TEXTURE_2D;
1171 templ.format = info->src.resource->format;
1172 templ.width0 = info->src.resource->width0;
1173 templ.height0 = info->src.resource->height0;
1174 templ.depth0 = 1;
1175 templ.array_size = 1;
1176 templ.usage = PIPE_USAGE_DEFAULT;
1177 templ.flags = SI_RESOURCE_FLAG_FORCE_TILING |
1178 SI_RESOURCE_FLAG_DISABLE_DCC;
1179
1180 /* The src and dst microtile modes must be the same. */
1181 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1182 templ.bind = PIPE_BIND_SCANOUT;
1183 else
1184 templ.bind = 0;
1185
1186 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1187 if (!tmp)
1188 return false;
1189 rtmp = (struct r600_texture*)tmp;
1190
1191 assert(!rtmp->surface.is_linear);
1192 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1193
1194 /* resolve */
1195 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1196
1197 /* blit */
1198 blit = *info;
1199 blit.src.resource = tmp;
1200 blit.src.box.z = 0;
1201
1202 si_blitter_begin(sctx, SI_BLIT |
1203 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1204 util_blitter_blit(sctx->blitter, &blit);
1205 si_blitter_end(sctx);
1206
1207 pipe_resource_reference(&tmp, NULL);
1208 return true;
1209 }
1210
1211 static void si_blit(struct pipe_context *ctx,
1212 const struct pipe_blit_info *info)
1213 {
1214 struct si_context *sctx = (struct si_context*)ctx;
1215 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1216
1217 if (do_hardware_msaa_resolve(ctx, info)) {
1218 return;
1219 }
1220
1221 /* Using SDMA for copying to a linear texture in GTT is much faster.
1222 * This improves DRI PRIME performance.
1223 *
1224 * resource_copy_region can't do this yet, because dma_copy calls it
1225 * on failure (recursion).
1226 */
1227 if (rdst->surface.is_linear &&
1228 sctx->dma_copy &&
1229 util_can_blit_via_copy_region(info, false)) {
1230 sctx->dma_copy(ctx, info->dst.resource, info->dst.level,
1231 info->dst.box.x, info->dst.box.y,
1232 info->dst.box.z,
1233 info->src.resource, info->src.level,
1234 &info->src.box);
1235 return;
1236 }
1237
1238 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1239
1240 /* The driver doesn't decompress resources automatically while
1241 * u_blitter is rendering. */
1242 vi_disable_dcc_if_incompatible_format(sctx, info->src.resource,
1243 info->src.level,
1244 info->src.format);
1245 vi_disable_dcc_if_incompatible_format(sctx, info->dst.resource,
1246 info->dst.level,
1247 info->dst.format);
1248 si_decompress_subresource(ctx, info->src.resource, info->mask,
1249 info->src.level,
1250 info->src.box.z,
1251 info->src.box.z + info->src.box.depth - 1);
1252
1253 if (sctx->screen->debug_flags & DBG(FORCE_DMA) &&
1254 util_try_blit_via_copy_region(ctx, info))
1255 return;
1256
1257 si_blitter_begin(sctx, SI_BLIT |
1258 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1259 util_blitter_blit(sctx->blitter, info);
1260 si_blitter_end(sctx);
1261 }
1262
1263 static boolean si_generate_mipmap(struct pipe_context *ctx,
1264 struct pipe_resource *tex,
1265 enum pipe_format format,
1266 unsigned base_level, unsigned last_level,
1267 unsigned first_layer, unsigned last_layer)
1268 {
1269 struct si_context *sctx = (struct si_context*)ctx;
1270 struct r600_texture *rtex = (struct r600_texture *)tex;
1271
1272 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1273 return false;
1274
1275 /* The driver doesn't decompress resources automatically while
1276 * u_blitter is rendering. */
1277 vi_disable_dcc_if_incompatible_format(sctx, tex, base_level,
1278 format);
1279 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1280 base_level, first_layer, last_layer);
1281
1282 /* Clear dirty_level_mask for the levels that will be overwritten. */
1283 assert(base_level < last_level);
1284 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1285 last_level - base_level);
1286
1287 sctx->generate_mipmap_for_depth = rtex->is_depth;
1288
1289 si_blitter_begin(sctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1290 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1291 base_level, last_level,
1292 first_layer, last_layer);
1293 si_blitter_end(sctx);
1294
1295 sctx->generate_mipmap_for_depth = false;
1296 return true;
1297 }
1298
1299 static void si_flush_resource(struct pipe_context *ctx,
1300 struct pipe_resource *res)
1301 {
1302 struct si_context *sctx = (struct si_context*)ctx;
1303 struct r600_texture *rtex = (struct r600_texture*)res;
1304
1305 assert(res->target != PIPE_BUFFER);
1306 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1307
1308 /* st/dri calls flush twice per frame (not a bug), this prevents double
1309 * decompression. */
1310 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1311 return;
1312
1313 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1314 si_blit_decompress_color(sctx, rtex, 0, res->last_level,
1315 0, util_max_layer(res, 0),
1316 rtex->dcc_separate_buffer != NULL);
1317 }
1318
1319 /* Always do the analysis even if DCC is disabled at the moment. */
1320 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1321 rtex->separate_dcc_dirty = false;
1322 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1323 }
1324 }
1325
1326 void si_decompress_dcc(struct si_context *sctx, struct r600_texture *rtex)
1327 {
1328 if (!rtex->dcc_offset)
1329 return;
1330
1331 si_blit_decompress_color(sctx, rtex, 0, rtex->buffer.b.b.last_level,
1332 0, util_max_layer(&rtex->buffer.b.b, 0),
1333 true);
1334 }
1335
1336 void si_init_blit_functions(struct si_context *sctx)
1337 {
1338 sctx->b.resource_copy_region = si_resource_copy_region;
1339 sctx->b.blit = si_blit;
1340 sctx->b.flush_resource = si_flush_resource;
1341 sctx->b.generate_mipmap = si_generate_mipmap;
1342 }