projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: remove r600_pipe_common::blit_decompress_depth
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_log.h"
28 #include "util/u_surface.h"
29
30 enum {
31 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
32 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
33
34 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
35 SI_SAVE_FRAGMENT_STATE,
36
37 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
38 SI_DISABLE_RENDER_COND,
39
40 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
41 };
42
43 void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
44 {
45 struct si_context *sctx = (struct si_context *)ctx;
46
47 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
48 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
49 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
50 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
51 util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets,
52 (struct pipe_stream_output_target**)sctx->streamout.targets);
53 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
54
55 if (op & SI_SAVE_FRAGMENT_STATE) {
56 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
57 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
58 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
59 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
60 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
61 util_blitter_save_scissor(sctx->blitter, &sctx->scissors.states[0]);
62 }
63
64 if (op & SI_SAVE_FRAMEBUFFER)
65 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
66
67 if (op & SI_SAVE_TEXTURES) {
68 util_blitter_save_fragment_sampler_states(
69 sctx->blitter, 2,
70 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
71
72 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
73 sctx->samplers[PIPE_SHADER_FRAGMENT].views);
74 }
75
76 if (op & SI_DISABLE_RENDER_COND)
77 sctx->b.render_cond_force_off = true;
78 }
79
80 void si_blitter_end(struct pipe_context *ctx)
81 {
82 struct si_context *sctx = (struct si_context *)ctx;
83
84 sctx->b.render_cond_force_off = false;
85
86 /* Restore shader pointers because the VS blit shader changed all
87 * non-global VS user SGPRs. */
88 sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX);
89 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
90 si_mark_atom_dirty(sctx, &sctx->shader_pointers.atom);
91 }
92
93 static unsigned u_max_sample(struct pipe_resource *r)
94 {
95 return r->nr_samples ? r->nr_samples - 1 : 0;
96 }
97
98 static unsigned
99 si_blit_dbcb_copy(struct si_context *sctx,
100 struct r600_texture *src,
101 struct r600_texture *dst,
102 unsigned planes, unsigned level_mask,
103 unsigned first_layer, unsigned last_layer,
104 unsigned first_sample, unsigned last_sample)
105 {
106 struct pipe_surface surf_tmpl = {{0}};
107 unsigned layer, sample, checked_last_layer, max_layer;
108 unsigned fully_copied_levels = 0;
109
110 if (planes & PIPE_MASK_Z)
111 sctx->dbcb_depth_copy_enabled = true;
112 if (planes & PIPE_MASK_S)
113 sctx->dbcb_stencil_copy_enabled = true;
114 si_mark_atom_dirty(sctx, &sctx->db_render_state);
115
116 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
117
118 sctx->decompression_enabled = true;
119
120 while (level_mask) {
121 unsigned level = u_bit_scan(&level_mask);
122
123 /* The smaller the mipmap level, the less layers there are
124 * as far as 3D textures are concerned. */
125 max_layer = util_max_layer(&src->resource.b.b, level);
126 checked_last_layer = MIN2(last_layer, max_layer);
127
128 surf_tmpl.u.tex.level = level;
129
130 for (layer = first_layer; layer <= checked_last_layer; layer++) {
131 struct pipe_surface *zsurf, *cbsurf;
132
133 surf_tmpl.format = src->resource.b.b.format;
134 surf_tmpl.u.tex.first_layer = layer;
135 surf_tmpl.u.tex.last_layer = layer;
136
137 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
138
139 surf_tmpl.format = dst->resource.b.b.format;
140 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
141
142 for (sample = first_sample; sample <= last_sample; sample++) {
143 if (sample != sctx->dbcb_copy_sample) {
144 sctx->dbcb_copy_sample = sample;
145 si_mark_atom_dirty(sctx, &sctx->db_render_state);
146 }
147
148 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
149 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
150 sctx->custom_dsa_flush, 1.0f);
151 si_blitter_end(&sctx->b.b);
152 }
153
154 pipe_surface_reference(&zsurf, NULL);
155 pipe_surface_reference(&cbsurf, NULL);
156 }
157
158 if (first_layer == 0 && last_layer >= max_layer &&
159 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
160 fully_copied_levels |= 1u << level;
161 }
162
163 sctx->decompression_enabled = false;
164 sctx->dbcb_depth_copy_enabled = false;
165 sctx->dbcb_stencil_copy_enabled = false;
166 si_mark_atom_dirty(sctx, &sctx->db_render_state);
167
168 return fully_copied_levels;
169 }
170
171 void si_blit_decompress_depth(struct pipe_context *ctx,
172 struct r600_texture *texture,
173 struct r600_texture *staging,
174 unsigned first_level, unsigned last_level,
175 unsigned first_layer, unsigned last_layer,
176 unsigned first_sample, unsigned last_sample)
177 {
178 const struct util_format_description *desc;
179 unsigned planes = 0;
180
181 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
182
183 desc = util_format_description(staging->resource.b.b.format);
184
185 if (util_format_has_depth(desc))
186 planes |= PIPE_MASK_Z;
187 if (util_format_has_stencil(desc))
188 planes |= PIPE_MASK_S;
189
190 si_blit_dbcb_copy(
191 (struct si_context *)ctx, texture, staging, planes,
192 u_bit_consecutive(first_level, last_level - first_level + 1),
193 first_layer, last_layer, first_sample, last_sample);
194 }
195
196 /* Helper function for si_blit_decompress_zs_in_place.
197 */
198 static void
199 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
200 struct r600_texture *texture,
201 unsigned planes, unsigned level_mask,
202 unsigned first_layer, unsigned last_layer)
203 {
204 struct pipe_surface *zsurf, surf_tmpl = {{0}};
205 unsigned layer, max_layer, checked_last_layer;
206 unsigned fully_decompressed_mask = 0;
207
208 if (!level_mask)
209 return;
210
211 if (planes & PIPE_MASK_S)
212 sctx->db_flush_stencil_inplace = true;
213 if (planes & PIPE_MASK_Z)
214 sctx->db_flush_depth_inplace = true;
215 si_mark_atom_dirty(sctx, &sctx->db_render_state);
216
217 surf_tmpl.format = texture->resource.b.b.format;
218
219 sctx->decompression_enabled = true;
220
221 while (level_mask) {
222 unsigned level = u_bit_scan(&level_mask);
223
224 surf_tmpl.u.tex.level = level;
225
226 /* The smaller the mipmap level, the less layers there are
227 * as far as 3D textures are concerned. */
228 max_layer = util_max_layer(&texture->resource.b.b, level);
229 checked_last_layer = MIN2(last_layer, max_layer);
230
231 for (layer = first_layer; layer <= checked_last_layer; layer++) {
232 surf_tmpl.u.tex.first_layer = layer;
233 surf_tmpl.u.tex.last_layer = layer;
234
235 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
236
237 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
238 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
239 sctx->custom_dsa_flush,
240 1.0f);
241 si_blitter_end(&sctx->b.b);
242
243 pipe_surface_reference(&zsurf, NULL);
244 }
245
246 /* The texture will always be dirty if some layers aren't flushed.
247 * I don't think this case occurs often though. */
248 if (first_layer == 0 && last_layer >= max_layer) {
249 fully_decompressed_mask |= 1u << level;
250 }
251 }
252
253 if (planes & PIPE_MASK_Z)
254 texture->dirty_level_mask &= ~fully_decompressed_mask;
255 if (planes & PIPE_MASK_S)
256 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
257
258 sctx->decompression_enabled = false;
259 sctx->db_flush_depth_inplace = false;
260 sctx->db_flush_stencil_inplace = false;
261 si_mark_atom_dirty(sctx, &sctx->db_render_state);
262 }
263
264 /* Helper function of si_flush_depth_texture: decompress the given levels
265 * of Z and/or S planes in place.
266 */
267 static void
268 si_blit_decompress_zs_in_place(struct si_context *sctx,
269 struct r600_texture *texture,
270 unsigned levels_z, unsigned levels_s,
271 unsigned first_layer, unsigned last_layer)
272 {
273 unsigned both = levels_z & levels_s;
274
275 /* First, do combined Z & S decompresses for levels that need it. */
276 if (both) {
277 si_blit_decompress_zs_planes_in_place(
278 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
279 both,
280 first_layer, last_layer);
281 levels_z &= ~both;
282 levels_s &= ~both;
283 }
284
285 /* Now do separate Z and S decompresses. */
286 if (levels_z) {
287 si_blit_decompress_zs_planes_in_place(
288 sctx, texture, PIPE_MASK_Z,
289 levels_z,
290 first_layer, last_layer);
291 }
292
293 if (levels_s) {
294 si_blit_decompress_zs_planes_in_place(
295 sctx, texture, PIPE_MASK_S,
296 levels_s,
297 first_layer, last_layer);
298 }
299 }
300
301 static void
302 si_decompress_depth(struct si_context *sctx,
303 struct r600_texture *tex,
304 unsigned required_planes,
305 unsigned first_level, unsigned last_level,
306 unsigned first_layer, unsigned last_layer)
307 {
308 unsigned inplace_planes = 0;
309 unsigned copy_planes = 0;
310 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
311 unsigned levels_z = 0;
312 unsigned levels_s = 0;
313
314 if (required_planes & PIPE_MASK_Z) {
315 levels_z = level_mask & tex->dirty_level_mask;
316
317 if (levels_z) {
318 if (si_can_sample_zs(tex, false))
319 inplace_planes |= PIPE_MASK_Z;
320 else
321 copy_planes |= PIPE_MASK_Z;
322 }
323 }
324 if (required_planes & PIPE_MASK_S) {
325 levels_s = level_mask & tex->stencil_dirty_level_mask;
326
327 if (levels_s) {
328 if (si_can_sample_zs(tex, true))
329 inplace_planes |= PIPE_MASK_S;
330 else
331 copy_planes |= PIPE_MASK_S;
332 }
333 }
334
335 if (unlikely(sctx->b.log))
336 u_log_printf(sctx->b.log,
337 "\n------------------------------------------------\n"
338 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
339 first_level, last_level, levels_z, levels_s);
340
341 /* We may have to allocate the flushed texture here when called from
342 * si_decompress_subresource.
343 */
344 if (copy_planes &&
345 (tex->flushed_depth_texture ||
346 si_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
347 struct r600_texture *dst = tex->flushed_depth_texture;
348 unsigned fully_copied_levels;
349 unsigned levels = 0;
350
351 assert(tex->flushed_depth_texture);
352
353 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
354 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
355
356 if (copy_planes & PIPE_MASK_Z) {
357 levels |= levels_z;
358 levels_z = 0;
359 }
360 if (copy_planes & PIPE_MASK_S) {
361 levels |= levels_s;
362 levels_s = 0;
363 }
364
365 fully_copied_levels = si_blit_dbcb_copy(
366 sctx, tex, dst, copy_planes, levels,
367 first_layer, last_layer,
368 0, u_max_sample(&tex->resource.b.b));
369
370 if (copy_planes & PIPE_MASK_Z)
371 tex->dirty_level_mask &= ~fully_copied_levels;
372 if (copy_planes & PIPE_MASK_S)
373 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
374 }
375
376 if (inplace_planes) {
377 bool has_htile = si_htile_enabled(tex, first_level);
378 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
379
380 /* Don't decompress if there is no HTILE or when HTILE is
381 * TC-compatible. */
382 if (has_htile && !tc_compat_htile) {
383 si_blit_decompress_zs_in_place(
384 sctx, tex,
385 levels_z, levels_s,
386 first_layer, last_layer);
387 } else {
388 /* This is only a cache flush.
389 *
390 * Only clear the mask that we are flushing, because
391 * si_make_DB_shader_coherent() treats different levels
392 * and depth and stencil differently.
393 */
394 if (inplace_planes & PIPE_MASK_Z)
395 tex->dirty_level_mask &= ~levels_z;
396 if (inplace_planes & PIPE_MASK_S)
397 tex->stencil_dirty_level_mask &= ~levels_s;
398 }
399
400 /* Only in-place decompression needs to flush DB caches, or
401 * when we don't decompress but TC-compatible planes are dirty.
402 */
403 si_make_DB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
404 inplace_planes & PIPE_MASK_S,
405 tc_compat_htile);
406 }
407 /* set_framebuffer_state takes care of coherency for single-sample.
408 * The DB->CB copy uses CB for the final writes.
409 */
410 if (copy_planes && tex->resource.b.b.nr_samples > 1)
411 si_make_CB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
412 false);
413 }
414
415 static void
416 si_decompress_sampler_depth_textures(struct si_context *sctx,
417 struct si_samplers *textures)
418 {
419 unsigned i;
420 unsigned mask = textures->needs_depth_decompress_mask;
421
422 while (mask) {
423 struct pipe_sampler_view *view;
424 struct si_sampler_view *sview;
425 struct r600_texture *tex;
426
427 i = u_bit_scan(&mask);
428
429 view = textures->views[i];
430 assert(view);
431 sview = (struct si_sampler_view*)view;
432
433 tex = (struct r600_texture *)view->texture;
434 assert(tex->db_compatible);
435
436 si_decompress_depth(sctx, tex,
437 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
438 view->u.tex.first_level, view->u.tex.last_level,
439 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
440 }
441 }
442
443 static void si_blit_decompress_color(struct pipe_context *ctx,
444 struct r600_texture *rtex,
445 unsigned first_level, unsigned last_level,
446 unsigned first_layer, unsigned last_layer,
447 bool need_dcc_decompress)
448 {
449 struct si_context *sctx = (struct si_context *)ctx;
450 void* custom_blend;
451 unsigned layer, checked_last_layer, max_layer;
452 unsigned level_mask =
453 u_bit_consecutive(first_level, last_level - first_level + 1);
454
455 if (!need_dcc_decompress)
456 level_mask &= rtex->dirty_level_mask;
457 if (!level_mask)
458 return;
459
460 if (unlikely(sctx->b.log))
461 u_log_printf(sctx->b.log,
462 "\n------------------------------------------------\n"
463 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
464 first_level, last_level, level_mask);
465
466 if (need_dcc_decompress) {
467 custom_blend = sctx->custom_blend_dcc_decompress;
468
469 assert(rtex->dcc_offset);
470
471 /* disable levels without DCC */
472 for (int i = first_level; i <= last_level; i++) {
473 if (!vi_dcc_enabled(rtex, i))
474 level_mask &= ~(1 << i);
475 }
476 } else if (rtex->fmask.size) {
477 custom_blend = sctx->custom_blend_fmask_decompress;
478 } else {
479 custom_blend = sctx->custom_blend_eliminate_fastclear;
480 }
481
482 sctx->decompression_enabled = true;
483
484 while (level_mask) {
485 unsigned level = u_bit_scan(&level_mask);
486
487 /* The smaller the mipmap level, the less layers there are
488 * as far as 3D textures are concerned. */
489 max_layer = util_max_layer(&rtex->resource.b.b, level);
490 checked_last_layer = MIN2(last_layer, max_layer);
491
492 for (layer = first_layer; layer <= checked_last_layer; layer++) {
493 struct pipe_surface *cbsurf, surf_tmpl;
494
495 surf_tmpl.format = rtex->resource.b.b.format;
496 surf_tmpl.u.tex.level = level;
497 surf_tmpl.u.tex.first_layer = layer;
498 surf_tmpl.u.tex.last_layer = layer;
499 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
500
501 /* Required before and after FMASK and DCC_DECOMPRESS. */
502 if (custom_blend == sctx->custom_blend_fmask_decompress ||
503 custom_blend == sctx->custom_blend_dcc_decompress)
504 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
505
506 si_blitter_begin(ctx, SI_DECOMPRESS);
507 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
508 si_blitter_end(ctx);
509
510 if (custom_blend == sctx->custom_blend_fmask_decompress ||
511 custom_blend == sctx->custom_blend_dcc_decompress)
512 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
513
514 pipe_surface_reference(&cbsurf, NULL);
515 }
516
517 /* The texture will always be dirty if some layers aren't flushed.
518 * I don't think this case occurs often though. */
519 if (first_layer == 0 && last_layer >= max_layer) {
520 rtex->dirty_level_mask &= ~(1 << level);
521 }
522 }
523
524 sctx->decompression_enabled = false;
525 si_make_CB_shader_coherent(sctx, rtex->resource.b.b.nr_samples,
526 vi_dcc_enabled(rtex, first_level));
527 }
528
529 static void
530 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
531 unsigned first_level, unsigned last_level)
532 {
533 /* CMASK or DCC can be discarded and we can still end up here. */
534 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
535 return;
536
537 si_blit_decompress_color(&sctx->b.b, tex, first_level, last_level, 0,
538 util_max_layer(&tex->resource.b.b, first_level),
539 false);
540 }
541
542 static void
543 si_decompress_sampler_color_textures(struct si_context *sctx,
544 struct si_samplers *textures)
545 {
546 unsigned i;
547 unsigned mask = textures->needs_color_decompress_mask;
548
549 while (mask) {
550 struct pipe_sampler_view *view;
551 struct r600_texture *tex;
552
553 i = u_bit_scan(&mask);
554
555 view = textures->views[i];
556 assert(view);
557
558 tex = (struct r600_texture *)view->texture;
559
560 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
561 view->u.tex.last_level);
562 }
563 }
564
565 static void
566 si_decompress_image_color_textures(struct si_context *sctx,
567 struct si_images *images)
568 {
569 unsigned i;
570 unsigned mask = images->needs_color_decompress_mask;
571
572 while (mask) {
573 const struct pipe_image_view *view;
574 struct r600_texture *tex;
575
576 i = u_bit_scan(&mask);
577
578 view = &images->views[i];
579 assert(view->resource->target != PIPE_BUFFER);
580
581 tex = (struct r600_texture *)view->resource;
582
583 si_decompress_color_texture(sctx, tex, view->u.tex.level,
584 view->u.tex.level);
585 }
586 }
587
588 static void si_check_render_feedback_texture(struct si_context *sctx,
589 struct r600_texture *tex,
590 unsigned first_level,
591 unsigned last_level,
592 unsigned first_layer,
593 unsigned last_layer)
594 {
595 bool render_feedback = false;
596
597 if (!tex->dcc_offset)
598 return;
599
600 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
601 struct r600_surface * surf;
602
603 if (!sctx->framebuffer.state.cbufs[j])
604 continue;
605
606 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
607
608 if (tex == (struct r600_texture *)surf->base.texture &&
609 surf->base.u.tex.level >= first_level &&
610 surf->base.u.tex.level <= last_level &&
611 surf->base.u.tex.first_layer <= last_layer &&
612 surf->base.u.tex.last_layer >= first_layer) {
613 render_feedback = true;
614 break;
615 }
616 }
617
618 if (render_feedback)
619 si_texture_disable_dcc(&sctx->b, tex);
620 }
621
622 static void si_check_render_feedback_textures(struct si_context *sctx,
623 struct si_samplers *textures)
624 {
625 uint32_t mask = textures->enabled_mask;
626
627 while (mask) {
628 const struct pipe_sampler_view *view;
629 struct r600_texture *tex;
630
631 unsigned i = u_bit_scan(&mask);
632
633 view = textures->views[i];
634 if(view->texture->target == PIPE_BUFFER)
635 continue;
636
637 tex = (struct r600_texture *)view->texture;
638
639 si_check_render_feedback_texture(sctx, tex,
640 view->u.tex.first_level,
641 view->u.tex.last_level,
642 view->u.tex.first_layer,
643 view->u.tex.last_layer);
644 }
645 }
646
647 static void si_check_render_feedback_images(struct si_context *sctx,
648 struct si_images *images)
649 {
650 uint32_t mask = images->enabled_mask;
651
652 while (mask) {
653 const struct pipe_image_view *view;
654 struct r600_texture *tex;
655
656 unsigned i = u_bit_scan(&mask);
657
658 view = &images->views[i];
659 if (view->resource->target == PIPE_BUFFER)
660 continue;
661
662 tex = (struct r600_texture *)view->resource;
663
664 si_check_render_feedback_texture(sctx, tex,
665 view->u.tex.level,
666 view->u.tex.level,
667 view->u.tex.first_layer,
668 view->u.tex.last_layer);
669 }
670 }
671
672 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
673 {
674 util_dynarray_foreach(&sctx->resident_tex_handles,
675 struct si_texture_handle *, tex_handle) {
676 struct pipe_sampler_view *view;
677 struct r600_texture *tex;
678
679 view = (*tex_handle)->view;
680 if (view->texture->target == PIPE_BUFFER)
681 continue;
682
683 tex = (struct r600_texture *)view->texture;
684
685 si_check_render_feedback_texture(sctx, tex,
686 view->u.tex.first_level,
687 view->u.tex.last_level,
688 view->u.tex.first_layer,
689 view->u.tex.last_layer);
690 }
691 }
692
693 static void si_check_render_feedback_resident_images(struct si_context *sctx)
694 {
695 util_dynarray_foreach(&sctx->resident_img_handles,
696 struct si_image_handle *, img_handle) {
697 struct pipe_image_view *view;
698 struct r600_texture *tex;
699
700 view = &(*img_handle)->view;
701 if (view->resource->target == PIPE_BUFFER)
702 continue;
703
704 tex = (struct r600_texture *)view->resource;
705
706 si_check_render_feedback_texture(sctx, tex,
707 view->u.tex.level,
708 view->u.tex.level,
709 view->u.tex.first_layer,
710 view->u.tex.last_layer);
711 }
712 }
713
714 static void si_check_render_feedback(struct si_context *sctx)
715 {
716 /* There is no render feedback if color writes are disabled.
717 * (e.g. a pixel shader with image stores)
718 */
719 if (!si_get_total_colormask(sctx))
720 return;
721
722 if (!sctx->need_check_render_feedback)
723 return;
724
725 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
726 si_check_render_feedback_images(sctx, &sctx->images[i]);
727 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
728 }
729
730 si_check_render_feedback_resident_images(sctx);
731 si_check_render_feedback_resident_textures(sctx);
732
733 sctx->need_check_render_feedback = false;
734 }
735
736 static void si_decompress_resident_textures(struct si_context *sctx)
737 {
738 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
739 struct si_texture_handle *, tex_handle) {
740 struct pipe_sampler_view *view = (*tex_handle)->view;
741 struct r600_texture *tex = (struct r600_texture *)view->texture;
742
743 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
744 view->u.tex.last_level);
745 }
746
747 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
748 struct si_texture_handle *, tex_handle) {
749 struct pipe_sampler_view *view = (*tex_handle)->view;
750 struct si_sampler_view *sview = (struct si_sampler_view *)view;
751 struct r600_texture *tex = (struct r600_texture *)view->texture;
752
753 si_decompress_depth(sctx, tex,
754 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
755 view->u.tex.first_level, view->u.tex.last_level,
756 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
757 }
758 }
759
760 static void si_decompress_resident_images(struct si_context *sctx)
761 {
762 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
763 struct si_image_handle *, img_handle) {
764 struct pipe_image_view *view = &(*img_handle)->view;
765 struct r600_texture *tex = (struct r600_texture *)view->resource;
766
767 si_decompress_color_texture(sctx, tex, view->u.tex.level,
768 view->u.tex.level);
769 }
770 }
771
772 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
773 {
774 unsigned compressed_colortex_counter, mask;
775
776 if (sctx->blitter->running)
777 return;
778
779 /* Update the compressed_colortex_mask if necessary. */
780 compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter);
781 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
782 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
783 si_update_needs_color_decompress_masks(sctx);
784 }
785
786 /* Decompress color & depth textures if needed. */
787 mask = sctx->shader_needs_decompress_mask & shader_mask;
788 while (mask) {
789 unsigned i = u_bit_scan(&mask);
790
791 if (sctx->samplers[i].needs_depth_decompress_mask) {
792 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
793 }
794 if (sctx->samplers[i].needs_color_decompress_mask) {
795 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
796 }
797 if (sctx->images[i].needs_color_decompress_mask) {
798 si_decompress_image_color_textures(sctx, &sctx->images[i]);
799 }
800 }
801
802 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
803 if (sctx->uses_bindless_samplers)
804 si_decompress_resident_textures(sctx);
805 if (sctx->uses_bindless_images)
806 si_decompress_resident_images(sctx);
807 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
808 if (sctx->cs_shader_state.program->uses_bindless_samplers)
809 si_decompress_resident_textures(sctx);
810 if (sctx->cs_shader_state.program->uses_bindless_images)
811 si_decompress_resident_images(sctx);
812 }
813
814 if (sctx->ps_uses_fbfetch) {
815 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
816 si_decompress_color_texture(sctx,
817 (struct r600_texture*)cb0->texture,
818 cb0->u.tex.first_layer,
819 cb0->u.tex.last_layer);
820 }
821
822 si_check_render_feedback(sctx);
823 }
824
825 /* Helper for decompressing a portion of a color or depth resource before
826 * blitting if any decompression is needed.
827 * The driver doesn't decompress resources automatically while u_blitter is
828 * rendering. */
829 static void si_decompress_subresource(struct pipe_context *ctx,
830 struct pipe_resource *tex,
831 unsigned planes, unsigned level,
832 unsigned first_layer, unsigned last_layer)
833 {
834 struct si_context *sctx = (struct si_context *)ctx;
835 struct r600_texture *rtex = (struct r600_texture*)tex;
836
837 if (rtex->db_compatible) {
838 planes &= PIPE_MASK_Z | PIPE_MASK_S;
839
840 if (!rtex->surface.has_stencil)
841 planes &= ~PIPE_MASK_S;
842
843 /* If we've rendered into the framebuffer and it's a blitting
844 * source, make sure the decompression pass is invoked
845 * by dirtying the framebuffer.
846 */
847 if (sctx->framebuffer.state.zsbuf &&
848 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
849 sctx->framebuffer.state.zsbuf->texture == tex)
850 si_update_fb_dirtiness_after_rendering(sctx);
851
852 si_decompress_depth(sctx, rtex, planes,
853 level, level,
854 first_layer, last_layer);
855 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
856 /* If we've rendered into the framebuffer and it's a blitting
857 * source, make sure the decompression pass is invoked
858 * by dirtying the framebuffer.
859 */
860 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
861 if (sctx->framebuffer.state.cbufs[i] &&
862 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
863 sctx->framebuffer.state.cbufs[i]->texture == tex) {
864 si_update_fb_dirtiness_after_rendering(sctx);
865 break;
866 }
867 }
868
869 si_blit_decompress_color(ctx, rtex, level, level,
870 first_layer, last_layer, false);
871 }
872 }
873
874 struct texture_orig_info {
875 unsigned format;
876 unsigned width0;
877 unsigned height0;
878 unsigned npix_x;
879 unsigned npix_y;
880 unsigned npix0_x;
881 unsigned npix0_y;
882 };
883
884 void si_resource_copy_region(struct pipe_context *ctx,
885 struct pipe_resource *dst,
886 unsigned dst_level,
887 unsigned dstx, unsigned dsty, unsigned dstz,
888 struct pipe_resource *src,
889 unsigned src_level,
890 const struct pipe_box *src_box)
891 {
892 struct si_context *sctx = (struct si_context *)ctx;
893 struct r600_texture *rsrc = (struct r600_texture*)src;
894 struct pipe_surface *dst_view, dst_templ;
895 struct pipe_sampler_view src_templ, *src_view;
896 unsigned dst_width, dst_height, src_width0, src_height0;
897 unsigned dst_width0, dst_height0, src_force_level = 0;
898 struct pipe_box sbox, dstbox;
899
900 /* Handle buffers first. */
901 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
902 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
903 return;
904 }
905
906 assert(u_max_sample(dst) == u_max_sample(src));
907
908 /* The driver doesn't decompress resources automatically while
909 * u_blitter is rendering. */
910 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
911 src_box->z, src_box->z + src_box->depth - 1);
912
913 dst_width = u_minify(dst->width0, dst_level);
914 dst_height = u_minify(dst->height0, dst_level);
915 dst_width0 = dst->width0;
916 dst_height0 = dst->height0;
917 src_width0 = src->width0;
918 src_height0 = src->height0;
919
920 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
921 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
922
923 if (util_format_is_compressed(src->format) ||
924 util_format_is_compressed(dst->format)) {
925 unsigned blocksize = rsrc->surface.bpe;
926
927 if (blocksize == 8)
928 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
929 else
930 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
931 dst_templ.format = src_templ.format;
932
933 dst_width = util_format_get_nblocksx(dst->format, dst_width);
934 dst_height = util_format_get_nblocksy(dst->format, dst_height);
935 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
936 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
937 src_width0 = util_format_get_nblocksx(src->format, src_width0);
938 src_height0 = util_format_get_nblocksy(src->format, src_height0);
939
940 dstx = util_format_get_nblocksx(dst->format, dstx);
941 dsty = util_format_get_nblocksy(dst->format, dsty);
942
943 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
944 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
945 sbox.z = src_box->z;
946 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
947 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
948 sbox.depth = src_box->depth;
949 src_box = &sbox;
950
951 src_force_level = src_level;
952 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
953 if (util_format_is_subsampled_422(src->format)) {
954 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
955 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
956
957 dst_width = util_format_get_nblocksx(dst->format, dst_width);
958 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
959 src_width0 = util_format_get_nblocksx(src->format, src_width0);
960
961 dstx = util_format_get_nblocksx(dst->format, dstx);
962
963 sbox = *src_box;
964 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
965 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
966 src_box = &sbox;
967 } else {
968 unsigned blocksize = rsrc->surface.bpe;
969
970 switch (blocksize) {
971 case 1:
972 dst_templ.format = PIPE_FORMAT_R8_UNORM;
973 src_templ.format = PIPE_FORMAT_R8_UNORM;
974 break;
975 case 2:
976 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
977 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
978 break;
979 case 4:
980 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
981 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
982 break;
983 case 8:
984 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
985 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
986 break;
987 case 16:
988 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
989 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
990 break;
991 default:
992 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
993 util_format_short_name(src->format), blocksize);
994 assert(0);
995 }
996 }
997 }
998
999 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1000 * equivalent instead, which doesn't force DCC decompression.
1001 * Note that some chips avoid this issue by using SDMA.
1002 */
1003 if (util_format_is_snorm8(dst_templ.format)) {
1004 switch (dst_templ.format) {
1005 case PIPE_FORMAT_R8_SNORM:
1006 dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
1007 break;
1008 case PIPE_FORMAT_R8G8_SNORM:
1009 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
1010 break;
1011 case PIPE_FORMAT_R8G8B8X8_SNORM:
1012 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
1013 break;
1014 case PIPE_FORMAT_R8G8B8A8_SNORM:
1015 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1016 case PIPE_FORMAT_A8B8G8R8_SNORM:
1017 case PIPE_FORMAT_X8B8G8R8_SNORM:
1018 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
1019 break;
1020 case PIPE_FORMAT_A8_SNORM:
1021 dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
1022 break;
1023 case PIPE_FORMAT_L8_SNORM:
1024 dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
1025 break;
1026 case PIPE_FORMAT_L8A8_SNORM:
1027 dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
1028 break;
1029 case PIPE_FORMAT_I8_SNORM:
1030 dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
1031 break;
1032 default:; /* fall through */
1033 }
1034 }
1035
1036 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
1037 dst_templ.format);
1038 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
1039 src_templ.format);
1040
1041 /* Initialize the surface. */
1042 dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
1043 dst_width0, dst_height0,
1044 dst_width, dst_height);
1045
1046 /* Initialize the sampler view. */
1047 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1048 src_width0, src_height0,
1049 src_force_level);
1050
1051 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1052 abs(src_box->depth), &dstbox);
1053
1054 /* Copy. */
1055 si_blitter_begin(ctx, SI_COPY);
1056 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1057 src_view, src_box, src_width0, src_height0,
1058 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1059 false);
1060 si_blitter_end(ctx);
1061
1062 pipe_surface_reference(&dst_view, NULL);
1063 pipe_sampler_view_reference(&src_view, NULL);
1064 }
1065
1066 static void si_do_CB_resolve(struct si_context *sctx,
1067 const struct pipe_blit_info *info,
1068 struct pipe_resource *dst,
1069 unsigned dst_level, unsigned dst_z,
1070 enum pipe_format format)
1071 {
1072 /* Required before and after CB_RESOLVE. */
1073 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1074
1075 si_blitter_begin(&sctx->b.b, SI_COLOR_RESOLVE |
1076 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1077 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1078 info->src.resource, info->src.box.z,
1079 ~0, sctx->custom_blend_resolve,
1080 format);
1081 si_blitter_end(&sctx->b.b);
1082
1083 /* Flush caches for possible texturing. */
1084 si_make_CB_shader_coherent(sctx, 1, false);
1085 }
1086
1087 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1088 const struct pipe_blit_info *info)
1089 {
1090 struct si_context *sctx = (struct si_context*)ctx;
1091 struct r600_texture *src = (struct r600_texture*)info->src.resource;
1092 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
1093 MAYBE_UNUSED struct r600_texture *rtmp;
1094 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1095 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1096 enum pipe_format format = info->src.format;
1097 struct pipe_resource *tmp, templ;
1098 struct pipe_blit_info blit;
1099
1100 /* Check basic requirements for hw resolve. */
1101 if (!(info->src.resource->nr_samples > 1 &&
1102 info->dst.resource->nr_samples <= 1 &&
1103 !util_format_is_pure_integer(format) &&
1104 !util_format_is_depth_or_stencil(format) &&
1105 util_max_layer(info->src.resource, 0) == 0))
1106 return false;
1107
1108 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1109 * the format is R16G16. Use R16A16, which does work.
1110 */
1111 if (format == PIPE_FORMAT_R16G16_UNORM)
1112 format = PIPE_FORMAT_R16A16_UNORM;
1113 if (format == PIPE_FORMAT_R16G16_SNORM)
1114 format = PIPE_FORMAT_R16A16_SNORM;
1115
1116 /* Check the remaining requirements for hw resolve. */
1117 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1118 !info->scissor_enable &&
1119 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1120 util_is_format_compatible(util_format_description(info->src.format),
1121 util_format_description(info->dst.format)) &&
1122 dst_width == info->src.resource->width0 &&
1123 dst_height == info->src.resource->height0 &&
1124 info->dst.box.x == 0 &&
1125 info->dst.box.y == 0 &&
1126 info->dst.box.width == dst_width &&
1127 info->dst.box.height == dst_height &&
1128 info->dst.box.depth == 1 &&
1129 info->src.box.x == 0 &&
1130 info->src.box.y == 0 &&
1131 info->src.box.width == dst_width &&
1132 info->src.box.height == dst_height &&
1133 info->src.box.depth == 1 &&
1134 !dst->surface.is_linear &&
1135 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1136 /* Check the last constraint. */
1137 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1138 /* The next fast clear will switch to this mode to
1139 * get direct hw resolve next time if the mode is
1140 * different now.
1141 */
1142 src->last_msaa_resolve_target_micro_mode =
1143 dst->surface.micro_tile_mode;
1144 goto resolve_to_temp;
1145 }
1146
1147 /* Resolving into a surface with DCC is unsupported. Since
1148 * it's being overwritten anyway, clear it to uncompressed.
1149 * This is still the fastest codepath even with this clear.
1150 */
1151 if (vi_dcc_enabled(dst, info->dst.level)) {
1152 /* TODO: Implement per-level DCC clears for GFX9. */
1153 if (sctx->b.chip_class >= GFX9 &&
1154 info->dst.resource->last_level != 0)
1155 goto resolve_to_temp;
1156
1157 vi_dcc_clear_level(sctx, dst, info->dst.level,
1158 0xFFFFFFFF);
1159 dst->dirty_level_mask &= ~(1 << info->dst.level);
1160 }
1161
1162 /* Resolve directly from src to dst. */
1163 si_do_CB_resolve(sctx, info, info->dst.resource,
1164 info->dst.level, info->dst.box.z, format);
1165 return true;
1166 }
1167
1168 resolve_to_temp:
1169 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1170 * a temporary texture and blit.
1171 */
1172 memset(&templ, 0, sizeof(templ));
1173 templ.target = PIPE_TEXTURE_2D;
1174 templ.format = info->src.resource->format;
1175 templ.width0 = info->src.resource->width0;
1176 templ.height0 = info->src.resource->height0;
1177 templ.depth0 = 1;
1178 templ.array_size = 1;
1179 templ.usage = PIPE_USAGE_DEFAULT;
1180 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1181 R600_RESOURCE_FLAG_DISABLE_DCC;
1182
1183 /* The src and dst microtile modes must be the same. */
1184 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1185 templ.bind = PIPE_BIND_SCANOUT;
1186 else
1187 templ.bind = 0;
1188
1189 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1190 if (!tmp)
1191 return false;
1192 rtmp = (struct r600_texture*)tmp;
1193
1194 assert(!rtmp->surface.is_linear);
1195 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1196
1197 /* resolve */
1198 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1199
1200 /* blit */
1201 blit = *info;
1202 blit.src.resource = tmp;
1203 blit.src.box.z = 0;
1204
1205 si_blitter_begin(ctx, SI_BLIT |
1206 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1207 util_blitter_blit(sctx->blitter, &blit);
1208 si_blitter_end(ctx);
1209
1210 pipe_resource_reference(&tmp, NULL);
1211 return true;
1212 }
1213
1214 static void si_blit(struct pipe_context *ctx,
1215 const struct pipe_blit_info *info)
1216 {
1217 struct si_context *sctx = (struct si_context*)ctx;
1218 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1219
1220 if (do_hardware_msaa_resolve(ctx, info)) {
1221 return;
1222 }
1223
1224 /* Using SDMA for copying to a linear texture in GTT is much faster.
1225 * This improves DRI PRIME performance.
1226 *
1227 * resource_copy_region can't do this yet, because dma_copy calls it
1228 * on failure (recursion).
1229 */
1230 if (rdst->surface.is_linear &&
1231 sctx->b.dma_copy &&
1232 util_can_blit_via_copy_region(info, false)) {
1233 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1234 info->dst.box.x, info->dst.box.y,
1235 info->dst.box.z,
1236 info->src.resource, info->src.level,
1237 &info->src.box);
1238 return;
1239 }
1240
1241 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1242
1243 /* The driver doesn't decompress resources automatically while
1244 * u_blitter is rendering. */
1245 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1246 info->src.level,
1247 info->src.format);
1248 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1249 info->dst.level,
1250 info->dst.format);
1251 si_decompress_subresource(ctx, info->src.resource, info->mask,
1252 info->src.level,
1253 info->src.box.z,
1254 info->src.box.z + info->src.box.depth - 1);
1255
1256 if (sctx->screen->debug_flags & DBG(FORCE_DMA) &&
1257 util_try_blit_via_copy_region(ctx, info))
1258 return;
1259
1260 si_blitter_begin(ctx, SI_BLIT |
1261 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1262 util_blitter_blit(sctx->blitter, info);
1263 si_blitter_end(ctx);
1264 }
1265
1266 static boolean si_generate_mipmap(struct pipe_context *ctx,
1267 struct pipe_resource *tex,
1268 enum pipe_format format,
1269 unsigned base_level, unsigned last_level,
1270 unsigned first_layer, unsigned last_layer)
1271 {
1272 struct si_context *sctx = (struct si_context*)ctx;
1273 struct r600_texture *rtex = (struct r600_texture *)tex;
1274
1275 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1276 return false;
1277
1278 /* The driver doesn't decompress resources automatically while
1279 * u_blitter is rendering. */
1280 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1281 format);
1282 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1283 base_level, first_layer, last_layer);
1284
1285 /* Clear dirty_level_mask for the levels that will be overwritten. */
1286 assert(base_level < last_level);
1287 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1288 last_level - base_level);
1289
1290 sctx->generate_mipmap_for_depth = rtex->is_depth;
1291
1292 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1293 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1294 base_level, last_level,
1295 first_layer, last_layer);
1296 si_blitter_end(ctx);
1297
1298 sctx->generate_mipmap_for_depth = false;
1299 return true;
1300 }
1301
1302 static void si_flush_resource(struct pipe_context *ctx,
1303 struct pipe_resource *res)
1304 {
1305 struct r600_texture *rtex = (struct r600_texture*)res;
1306
1307 assert(res->target != PIPE_BUFFER);
1308 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1309
1310 /* st/dri calls flush twice per frame (not a bug), this prevents double
1311 * decompression. */
1312 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1313 return;
1314
1315 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1316 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1317 0, util_max_layer(res, 0),
1318 rtex->dcc_separate_buffer != NULL);
1319 }
1320
1321 /* Always do the analysis even if DCC is disabled at the moment. */
1322 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1323 rtex->separate_dcc_dirty = false;
1324 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1325 }
1326 }
1327
1328 void si_decompress_dcc(struct pipe_context *ctx, struct r600_texture *rtex)
1329 {
1330 if (!rtex->dcc_offset)
1331 return;
1332
1333 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1334 0, util_max_layer(&rtex->resource.b.b, 0),
1335 true);
1336 }
1337
1338 void si_init_blit_functions(struct si_context *sctx)
1339 {
1340 sctx->b.b.resource_copy_region = si_resource_copy_region;
1341 sctx->b.b.blit = si_blit;
1342 sctx->b.b.flush_resource = si_flush_resource;
1343 sctx->b.b.generate_mipmap = si_generate_mipmap;
1344 }