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radeonsi: move SI and CIK+ SDMA code into 1 common function for cleanups
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_compute.h"
28 #include "util/format/u_format.h"
29 #include "util/u_log.h"
30 #include "util/u_surface.h"
31
32 enum {
33 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
34 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
35
36 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
37 SI_SAVE_FRAGMENT_STATE,
38
39 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
40 SI_DISABLE_RENDER_COND,
41
42 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
43 };
44
45 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op)
46 {
47 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
48 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
49 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
50 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
51 util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets,
52 (struct pipe_stream_output_target**)sctx->streamout.targets);
53 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
54
55 if (op & SI_SAVE_FRAGMENT_STATE) {
56 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
57 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
58 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
59 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
60 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask);
61 util_blitter_save_scissor(sctx->blitter, &sctx->scissors[0]);
62 util_blitter_save_window_rectangles(sctx->blitter,
63 sctx->window_rectangles_include,
64 sctx->num_window_rectangles,
65 sctx->window_rectangles);
66 }
67
68 if (op & SI_SAVE_FRAMEBUFFER)
69 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
70
71 if (op & SI_SAVE_TEXTURES) {
72 util_blitter_save_fragment_sampler_states(
73 sctx->blitter, 2,
74 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
75
76 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
77 sctx->samplers[PIPE_SHADER_FRAGMENT].views);
78 }
79
80 if (op & SI_DISABLE_RENDER_COND)
81 sctx->render_cond_force_off = true;
82
83 if (sctx->screen->dpbb_allowed) {
84 sctx->dpbb_force_off = true;
85 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
86 }
87 }
88
89 void si_blitter_end(struct si_context *sctx)
90 {
91 if (sctx->screen->dpbb_allowed) {
92 sctx->dpbb_force_off = false;
93 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
94 }
95
96 sctx->render_cond_force_off = false;
97
98 /* Restore shader pointers because the VS blit shader changed all
99 * non-global VS user SGPRs. */
100 sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX);
101 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
102 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers);
103 }
104
105 static unsigned u_max_sample(struct pipe_resource *r)
106 {
107 return r->nr_samples ? r->nr_samples - 1 : 0;
108 }
109
110 static unsigned
111 si_blit_dbcb_copy(struct si_context *sctx,
112 struct si_texture *src,
113 struct si_texture *dst,
114 unsigned planes, unsigned level_mask,
115 unsigned first_layer, unsigned last_layer,
116 unsigned first_sample, unsigned last_sample)
117 {
118 struct pipe_surface surf_tmpl = {{0}};
119 unsigned layer, sample, checked_last_layer, max_layer;
120 unsigned fully_copied_levels = 0;
121
122 if (planes & PIPE_MASK_Z)
123 sctx->dbcb_depth_copy_enabled = true;
124 if (planes & PIPE_MASK_S)
125 sctx->dbcb_stencil_copy_enabled = true;
126 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
127
128 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
129
130 sctx->decompression_enabled = true;
131
132 while (level_mask) {
133 unsigned level = u_bit_scan(&level_mask);
134
135 /* The smaller the mipmap level, the less layers there are
136 * as far as 3D textures are concerned. */
137 max_layer = util_max_layer(&src->buffer.b.b, level);
138 checked_last_layer = MIN2(last_layer, max_layer);
139
140 surf_tmpl.u.tex.level = level;
141
142 for (layer = first_layer; layer <= checked_last_layer; layer++) {
143 struct pipe_surface *zsurf, *cbsurf;
144
145 surf_tmpl.format = src->buffer.b.b.format;
146 surf_tmpl.u.tex.first_layer = layer;
147 surf_tmpl.u.tex.last_layer = layer;
148
149 zsurf = sctx->b.create_surface(&sctx->b, &src->buffer.b.b, &surf_tmpl);
150
151 surf_tmpl.format = dst->buffer.b.b.format;
152 cbsurf = sctx->b.create_surface(&sctx->b, &dst->buffer.b.b, &surf_tmpl);
153
154 for (sample = first_sample; sample <= last_sample; sample++) {
155 if (sample != sctx->dbcb_copy_sample) {
156 sctx->dbcb_copy_sample = sample;
157 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
158 }
159
160 si_blitter_begin(sctx, SI_DECOMPRESS);
161 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
162 sctx->custom_dsa_flush, 1.0f);
163 si_blitter_end(sctx);
164 }
165
166 pipe_surface_reference(&zsurf, NULL);
167 pipe_surface_reference(&cbsurf, NULL);
168 }
169
170 if (first_layer == 0 && last_layer >= max_layer &&
171 first_sample == 0 && last_sample >= u_max_sample(&src->buffer.b.b))
172 fully_copied_levels |= 1u << level;
173 }
174
175 sctx->decompression_enabled = false;
176 sctx->dbcb_depth_copy_enabled = false;
177 sctx->dbcb_stencil_copy_enabled = false;
178 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
179
180 return fully_copied_levels;
181 }
182
183 /* Helper function for si_blit_decompress_zs_in_place.
184 */
185 static void
186 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
187 struct si_texture *texture,
188 unsigned planes, unsigned level_mask,
189 unsigned first_layer, unsigned last_layer)
190 {
191 struct pipe_surface *zsurf, surf_tmpl = {{0}};
192 unsigned layer, max_layer, checked_last_layer;
193 unsigned fully_decompressed_mask = 0;
194
195 if (!level_mask)
196 return;
197
198 if (planes & PIPE_MASK_S)
199 sctx->db_flush_stencil_inplace = true;
200 if (planes & PIPE_MASK_Z)
201 sctx->db_flush_depth_inplace = true;
202 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
203
204 surf_tmpl.format = texture->buffer.b.b.format;
205
206 sctx->decompression_enabled = true;
207
208 while (level_mask) {
209 unsigned level = u_bit_scan(&level_mask);
210
211 surf_tmpl.u.tex.level = level;
212
213 /* The smaller the mipmap level, the less layers there are
214 * as far as 3D textures are concerned. */
215 max_layer = util_max_layer(&texture->buffer.b.b, level);
216 checked_last_layer = MIN2(last_layer, max_layer);
217
218 for (layer = first_layer; layer <= checked_last_layer; layer++) {
219 surf_tmpl.u.tex.first_layer = layer;
220 surf_tmpl.u.tex.last_layer = layer;
221
222 zsurf = sctx->b.create_surface(&sctx->b, &texture->buffer.b.b, &surf_tmpl);
223
224 si_blitter_begin(sctx, SI_DECOMPRESS);
225 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
226 sctx->custom_dsa_flush,
227 1.0f);
228 si_blitter_end(sctx);
229
230 pipe_surface_reference(&zsurf, NULL);
231 }
232
233 /* The texture will always be dirty if some layers aren't flushed.
234 * I don't think this case occurs often though. */
235 if (first_layer == 0 && last_layer >= max_layer) {
236 fully_decompressed_mask |= 1u << level;
237 }
238 }
239
240 if (planes & PIPE_MASK_Z)
241 texture->dirty_level_mask &= ~fully_decompressed_mask;
242 if (planes & PIPE_MASK_S)
243 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
244
245 sctx->decompression_enabled = false;
246 sctx->db_flush_depth_inplace = false;
247 sctx->db_flush_stencil_inplace = false;
248 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
249 }
250
251 /* Helper function of si_flush_depth_texture: decompress the given levels
252 * of Z and/or S planes in place.
253 */
254 static void
255 si_blit_decompress_zs_in_place(struct si_context *sctx,
256 struct si_texture *texture,
257 unsigned levels_z, unsigned levels_s,
258 unsigned first_layer, unsigned last_layer)
259 {
260 unsigned both = levels_z & levels_s;
261
262 /* First, do combined Z & S decompresses for levels that need it. */
263 if (both) {
264 si_blit_decompress_zs_planes_in_place(
265 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
266 both,
267 first_layer, last_layer);
268 levels_z &= ~both;
269 levels_s &= ~both;
270 }
271
272 /* Now do separate Z and S decompresses. */
273 if (levels_z) {
274 si_blit_decompress_zs_planes_in_place(
275 sctx, texture, PIPE_MASK_Z,
276 levels_z,
277 first_layer, last_layer);
278 }
279
280 if (levels_s) {
281 si_blit_decompress_zs_planes_in_place(
282 sctx, texture, PIPE_MASK_S,
283 levels_s,
284 first_layer, last_layer);
285 }
286 }
287
288 static void
289 si_decompress_depth(struct si_context *sctx,
290 struct si_texture *tex,
291 unsigned required_planes,
292 unsigned first_level, unsigned last_level,
293 unsigned first_layer, unsigned last_layer)
294 {
295 unsigned inplace_planes = 0;
296 unsigned copy_planes = 0;
297 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
298 unsigned levels_z = 0;
299 unsigned levels_s = 0;
300
301 if (required_planes & PIPE_MASK_Z) {
302 levels_z = level_mask & tex->dirty_level_mask;
303
304 if (levels_z) {
305 if (si_can_sample_zs(tex, false))
306 inplace_planes |= PIPE_MASK_Z;
307 else
308 copy_planes |= PIPE_MASK_Z;
309 }
310 }
311 if (required_planes & PIPE_MASK_S) {
312 levels_s = level_mask & tex->stencil_dirty_level_mask;
313
314 if (levels_s) {
315 if (si_can_sample_zs(tex, true))
316 inplace_planes |= PIPE_MASK_S;
317 else
318 copy_planes |= PIPE_MASK_S;
319 }
320 }
321
322 if (unlikely(sctx->log))
323 u_log_printf(sctx->log,
324 "\n------------------------------------------------\n"
325 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
326 first_level, last_level, levels_z, levels_s);
327
328 /* We may have to allocate the flushed texture here when called from
329 * si_decompress_subresource.
330 */
331 if (copy_planes &&
332 (tex->flushed_depth_texture ||
333 si_init_flushed_depth_texture(&sctx->b, &tex->buffer.b.b))) {
334 struct si_texture *dst = tex->flushed_depth_texture;
335 unsigned fully_copied_levels;
336 unsigned levels = 0;
337
338 assert(tex->flushed_depth_texture);
339
340 if (util_format_is_depth_and_stencil(dst->buffer.b.b.format))
341 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
342
343 if (copy_planes & PIPE_MASK_Z) {
344 levels |= levels_z;
345 levels_z = 0;
346 }
347 if (copy_planes & PIPE_MASK_S) {
348 levels |= levels_s;
349 levels_s = 0;
350 }
351
352 fully_copied_levels = si_blit_dbcb_copy(
353 sctx, tex, dst, copy_planes, levels,
354 first_layer, last_layer,
355 0, u_max_sample(&tex->buffer.b.b));
356
357 if (copy_planes & PIPE_MASK_Z)
358 tex->dirty_level_mask &= ~fully_copied_levels;
359 if (copy_planes & PIPE_MASK_S)
360 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
361 }
362
363 if (inplace_planes) {
364 bool has_htile = si_htile_enabled(tex, first_level, inplace_planes);
365 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level,
366 inplace_planes);
367
368 /* Don't decompress if there is no HTILE or when HTILE is
369 * TC-compatible. */
370 if (has_htile && !tc_compat_htile) {
371 si_blit_decompress_zs_in_place(
372 sctx, tex,
373 levels_z, levels_s,
374 first_layer, last_layer);
375 } else {
376 /* This is only a cache flush.
377 *
378 * Only clear the mask that we are flushing, because
379 * si_make_DB_shader_coherent() treats different levels
380 * and depth and stencil differently.
381 */
382 if (inplace_planes & PIPE_MASK_Z)
383 tex->dirty_level_mask &= ~levels_z;
384 if (inplace_planes & PIPE_MASK_S)
385 tex->stencil_dirty_level_mask &= ~levels_s;
386 }
387
388 /* Only in-place decompression needs to flush DB caches, or
389 * when we don't decompress but TC-compatible planes are dirty.
390 */
391 si_make_DB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
392 inplace_planes & PIPE_MASK_S,
393 tc_compat_htile);
394 }
395 /* set_framebuffer_state takes care of coherency for single-sample.
396 * The DB->CB copy uses CB for the final writes.
397 */
398 if (copy_planes && tex->buffer.b.b.nr_samples > 1)
399 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
400 false, true /* no DCC */);
401 }
402
403 static void
404 si_decompress_sampler_depth_textures(struct si_context *sctx,
405 struct si_samplers *textures)
406 {
407 unsigned i;
408 unsigned mask = textures->needs_depth_decompress_mask;
409
410 while (mask) {
411 struct pipe_sampler_view *view;
412 struct si_sampler_view *sview;
413 struct si_texture *tex;
414
415 i = u_bit_scan(&mask);
416
417 view = textures->views[i];
418 assert(view);
419 sview = (struct si_sampler_view*)view;
420
421 tex = (struct si_texture *)view->texture;
422 assert(tex->db_compatible);
423
424 si_decompress_depth(sctx, tex,
425 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
426 view->u.tex.first_level, view->u.tex.last_level,
427 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
428 }
429 }
430
431 static void si_blit_decompress_color(struct si_context *sctx,
432 struct si_texture *tex,
433 unsigned first_level, unsigned last_level,
434 unsigned first_layer, unsigned last_layer,
435 bool need_dcc_decompress,
436 bool need_fmask_expand)
437 {
438 void* custom_blend;
439 unsigned layer, checked_last_layer, max_layer;
440 unsigned level_mask =
441 u_bit_consecutive(first_level, last_level - first_level + 1);
442
443 if (!need_dcc_decompress)
444 level_mask &= tex->dirty_level_mask;
445 if (!level_mask)
446 return;
447
448 if (unlikely(sctx->log))
449 u_log_printf(sctx->log,
450 "\n------------------------------------------------\n"
451 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
452 first_level, last_level, level_mask);
453
454 if (need_dcc_decompress) {
455 custom_blend = sctx->custom_blend_dcc_decompress;
456
457 assert(tex->surface.dcc_offset);
458
459 /* disable levels without DCC */
460 for (int i = first_level; i <= last_level; i++) {
461 if (!vi_dcc_enabled(tex, i))
462 level_mask &= ~(1 << i);
463 }
464 } else if (tex->surface.fmask_size) {
465 custom_blend = sctx->custom_blend_fmask_decompress;
466 } else {
467 custom_blend = sctx->custom_blend_eliminate_fastclear;
468 }
469
470 sctx->decompression_enabled = true;
471
472 while (level_mask) {
473 unsigned level = u_bit_scan(&level_mask);
474
475 /* The smaller the mipmap level, the less layers there are
476 * as far as 3D textures are concerned. */
477 max_layer = util_max_layer(&tex->buffer.b.b, level);
478 checked_last_layer = MIN2(last_layer, max_layer);
479
480 for (layer = first_layer; layer <= checked_last_layer; layer++) {
481 struct pipe_surface *cbsurf, surf_tmpl;
482
483 surf_tmpl.format = tex->buffer.b.b.format;
484 surf_tmpl.u.tex.level = level;
485 surf_tmpl.u.tex.first_layer = layer;
486 surf_tmpl.u.tex.last_layer = layer;
487 cbsurf = sctx->b.create_surface(&sctx->b, &tex->buffer.b.b, &surf_tmpl);
488
489 /* Required before and after FMASK and DCC_DECOMPRESS. */
490 if (custom_blend == sctx->custom_blend_fmask_decompress ||
491 custom_blend == sctx->custom_blend_dcc_decompress)
492 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
493
494 si_blitter_begin(sctx, SI_DECOMPRESS);
495 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
496 si_blitter_end(sctx);
497
498 if (custom_blend == sctx->custom_blend_fmask_decompress ||
499 custom_blend == sctx->custom_blend_dcc_decompress)
500 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
501
502 pipe_surface_reference(&cbsurf, NULL);
503 }
504
505 /* The texture will always be dirty if some layers aren't flushed.
506 * I don't think this case occurs often though. */
507 if (first_layer == 0 && last_layer >= max_layer) {
508 tex->dirty_level_mask &= ~(1 << level);
509 }
510 }
511
512 sctx->decompression_enabled = false;
513 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
514 vi_dcc_enabled(tex, first_level),
515 tex->surface.u.gfx9.dcc.pipe_aligned);
516
517 if (need_fmask_expand && tex->surface.fmask_offset && tex->fmask_is_not_identity) {
518 si_compute_expand_fmask(&sctx->b, &tex->buffer.b.b);
519 tex->fmask_is_not_identity = false;
520 }
521 }
522
523 static void
524 si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex,
525 unsigned first_level, unsigned last_level,
526 bool need_fmask_expand)
527 {
528 /* CMASK or DCC can be discarded and we can still end up here. */
529 if (!tex->cmask_buffer && !tex->surface.fmask_size && !tex->surface.dcc_offset)
530 return;
531
532 si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
533 util_max_layer(&tex->buffer.b.b, first_level),
534 false, need_fmask_expand);
535 }
536
537 static void
538 si_decompress_sampler_color_textures(struct si_context *sctx,
539 struct si_samplers *textures)
540 {
541 unsigned i;
542 unsigned mask = textures->needs_color_decompress_mask;
543
544 while (mask) {
545 struct pipe_sampler_view *view;
546 struct si_texture *tex;
547
548 i = u_bit_scan(&mask);
549
550 view = textures->views[i];
551 assert(view);
552
553 tex = (struct si_texture *)view->texture;
554
555 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
556 view->u.tex.last_level, false);
557 }
558 }
559
560 static void
561 si_decompress_image_color_textures(struct si_context *sctx,
562 struct si_images *images)
563 {
564 unsigned i;
565 unsigned mask = images->needs_color_decompress_mask;
566
567 while (mask) {
568 const struct pipe_image_view *view;
569 struct si_texture *tex;
570
571 i = u_bit_scan(&mask);
572
573 view = &images->views[i];
574 assert(view->resource->target != PIPE_BUFFER);
575
576 tex = (struct si_texture *)view->resource;
577
578 si_decompress_color_texture(sctx, tex, view->u.tex.level,
579 view->u.tex.level,
580 view->access & PIPE_IMAGE_ACCESS_WRITE);
581 }
582 }
583
584 static void si_check_render_feedback_texture(struct si_context *sctx,
585 struct si_texture *tex,
586 unsigned first_level,
587 unsigned last_level,
588 unsigned first_layer,
589 unsigned last_layer)
590 {
591 bool render_feedback = false;
592
593 if (!tex->surface.dcc_offset)
594 return;
595
596 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
597 struct si_surface * surf;
598
599 if (!sctx->framebuffer.state.cbufs[j])
600 continue;
601
602 surf = (struct si_surface*)sctx->framebuffer.state.cbufs[j];
603
604 if (tex == (struct si_texture *)surf->base.texture &&
605 surf->base.u.tex.level >= first_level &&
606 surf->base.u.tex.level <= last_level &&
607 surf->base.u.tex.first_layer <= last_layer &&
608 surf->base.u.tex.last_layer >= first_layer) {
609 render_feedback = true;
610 break;
611 }
612 }
613
614 if (render_feedback)
615 si_texture_disable_dcc(sctx, tex);
616 }
617
618 static void si_check_render_feedback_textures(struct si_context *sctx,
619 struct si_samplers *textures)
620 {
621 uint32_t mask = textures->enabled_mask;
622
623 while (mask) {
624 const struct pipe_sampler_view *view;
625 struct si_texture *tex;
626
627 unsigned i = u_bit_scan(&mask);
628
629 view = textures->views[i];
630 if(view->texture->target == PIPE_BUFFER)
631 continue;
632
633 tex = (struct si_texture *)view->texture;
634
635 si_check_render_feedback_texture(sctx, tex,
636 view->u.tex.first_level,
637 view->u.tex.last_level,
638 view->u.tex.first_layer,
639 view->u.tex.last_layer);
640 }
641 }
642
643 static void si_check_render_feedback_images(struct si_context *sctx,
644 struct si_images *images)
645 {
646 uint32_t mask = images->enabled_mask;
647
648 while (mask) {
649 const struct pipe_image_view *view;
650 struct si_texture *tex;
651
652 unsigned i = u_bit_scan(&mask);
653
654 view = &images->views[i];
655 if (view->resource->target == PIPE_BUFFER)
656 continue;
657
658 tex = (struct si_texture *)view->resource;
659
660 si_check_render_feedback_texture(sctx, tex,
661 view->u.tex.level,
662 view->u.tex.level,
663 view->u.tex.first_layer,
664 view->u.tex.last_layer);
665 }
666 }
667
668 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
669 {
670 util_dynarray_foreach(&sctx->resident_tex_handles,
671 struct si_texture_handle *, tex_handle) {
672 struct pipe_sampler_view *view;
673 struct si_texture *tex;
674
675 view = (*tex_handle)->view;
676 if (view->texture->target == PIPE_BUFFER)
677 continue;
678
679 tex = (struct si_texture *)view->texture;
680
681 si_check_render_feedback_texture(sctx, tex,
682 view->u.tex.first_level,
683 view->u.tex.last_level,
684 view->u.tex.first_layer,
685 view->u.tex.last_layer);
686 }
687 }
688
689 static void si_check_render_feedback_resident_images(struct si_context *sctx)
690 {
691 util_dynarray_foreach(&sctx->resident_img_handles,
692 struct si_image_handle *, img_handle) {
693 struct pipe_image_view *view;
694 struct si_texture *tex;
695
696 view = &(*img_handle)->view;
697 if (view->resource->target == PIPE_BUFFER)
698 continue;
699
700 tex = (struct si_texture *)view->resource;
701
702 si_check_render_feedback_texture(sctx, tex,
703 view->u.tex.level,
704 view->u.tex.level,
705 view->u.tex.first_layer,
706 view->u.tex.last_layer);
707 }
708 }
709
710 static void si_check_render_feedback(struct si_context *sctx)
711 {
712 if (!sctx->need_check_render_feedback)
713 return;
714
715 /* There is no render feedback if color writes are disabled.
716 * (e.g. a pixel shader with image stores)
717 */
718 if (!si_get_total_colormask(sctx))
719 return;
720
721 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
722 si_check_render_feedback_images(sctx, &sctx->images[i]);
723 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
724 }
725
726 si_check_render_feedback_resident_images(sctx);
727 si_check_render_feedback_resident_textures(sctx);
728
729 sctx->need_check_render_feedback = false;
730 }
731
732 static void si_decompress_resident_textures(struct si_context *sctx)
733 {
734 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
735 struct si_texture_handle *, tex_handle) {
736 struct pipe_sampler_view *view = (*tex_handle)->view;
737 struct si_texture *tex = (struct si_texture *)view->texture;
738
739 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
740 view->u.tex.last_level, false);
741 }
742
743 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
744 struct si_texture_handle *, tex_handle) {
745 struct pipe_sampler_view *view = (*tex_handle)->view;
746 struct si_sampler_view *sview = (struct si_sampler_view *)view;
747 struct si_texture *tex = (struct si_texture *)view->texture;
748
749 si_decompress_depth(sctx, tex,
750 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
751 view->u.tex.first_level, view->u.tex.last_level,
752 0, util_max_layer(&tex->buffer.b.b, view->u.tex.first_level));
753 }
754 }
755
756 static void si_decompress_resident_images(struct si_context *sctx)
757 {
758 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
759 struct si_image_handle *, img_handle) {
760 struct pipe_image_view *view = &(*img_handle)->view;
761 struct si_texture *tex = (struct si_texture *)view->resource;
762
763 si_decompress_color_texture(sctx, tex, view->u.tex.level,
764 view->u.tex.level,
765 view->access & PIPE_IMAGE_ACCESS_WRITE);
766 }
767 }
768
769 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
770 {
771 unsigned compressed_colortex_counter, mask;
772
773 if (sctx->blitter->running)
774 return;
775
776 /* Update the compressed_colortex_mask if necessary. */
777 compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter);
778 if (compressed_colortex_counter != sctx->last_compressed_colortex_counter) {
779 sctx->last_compressed_colortex_counter = compressed_colortex_counter;
780 si_update_needs_color_decompress_masks(sctx);
781 }
782
783 /* Decompress color & depth textures if needed. */
784 mask = sctx->shader_needs_decompress_mask & shader_mask;
785 while (mask) {
786 unsigned i = u_bit_scan(&mask);
787
788 if (sctx->samplers[i].needs_depth_decompress_mask) {
789 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
790 }
791 if (sctx->samplers[i].needs_color_decompress_mask) {
792 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
793 }
794 if (sctx->images[i].needs_color_decompress_mask) {
795 si_decompress_image_color_textures(sctx, &sctx->images[i]);
796 }
797 }
798
799 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
800 if (sctx->uses_bindless_samplers)
801 si_decompress_resident_textures(sctx);
802 if (sctx->uses_bindless_images)
803 si_decompress_resident_images(sctx);
804
805 if (sctx->ps_uses_fbfetch) {
806 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
807 si_decompress_color_texture(sctx,
808 (struct si_texture*)cb0->texture,
809 cb0->u.tex.first_layer,
810 cb0->u.tex.last_layer, false);
811 }
812
813 si_check_render_feedback(sctx);
814 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
815 if (sctx->cs_shader_state.program->sel.info.uses_bindless_samplers)
816 si_decompress_resident_textures(sctx);
817 if (sctx->cs_shader_state.program->sel.info.uses_bindless_images)
818 si_decompress_resident_images(sctx);
819 }
820 }
821
822 /* Helper for decompressing a portion of a color or depth resource before
823 * blitting if any decompression is needed.
824 * The driver doesn't decompress resources automatically while u_blitter is
825 * rendering. */
826 static void si_decompress_subresource(struct pipe_context *ctx,
827 struct pipe_resource *tex,
828 unsigned planes, unsigned level,
829 unsigned first_layer, unsigned last_layer)
830 {
831 struct si_context *sctx = (struct si_context *)ctx;
832 struct si_texture *stex = (struct si_texture*)tex;
833
834 if (stex->db_compatible) {
835 planes &= PIPE_MASK_Z | PIPE_MASK_S;
836
837 if (!stex->surface.has_stencil)
838 planes &= ~PIPE_MASK_S;
839
840 /* If we've rendered into the framebuffer and it's a blitting
841 * source, make sure the decompression pass is invoked
842 * by dirtying the framebuffer.
843 */
844 if (sctx->framebuffer.state.zsbuf &&
845 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
846 sctx->framebuffer.state.zsbuf->texture == tex)
847 si_update_fb_dirtiness_after_rendering(sctx);
848
849 si_decompress_depth(sctx, stex, planes,
850 level, level,
851 first_layer, last_layer);
852 } else if (stex->surface.fmask_size || stex->cmask_buffer || stex->surface.dcc_offset) {
853 /* If we've rendered into the framebuffer and it's a blitting
854 * source, make sure the decompression pass is invoked
855 * by dirtying the framebuffer.
856 */
857 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
858 if (sctx->framebuffer.state.cbufs[i] &&
859 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
860 sctx->framebuffer.state.cbufs[i]->texture == tex) {
861 si_update_fb_dirtiness_after_rendering(sctx);
862 break;
863 }
864 }
865
866 si_blit_decompress_color(sctx, stex, level, level,
867 first_layer, last_layer, false, false);
868 }
869 }
870
871 struct texture_orig_info {
872 unsigned format;
873 unsigned width0;
874 unsigned height0;
875 unsigned npix_x;
876 unsigned npix_y;
877 unsigned npix0_x;
878 unsigned npix0_y;
879 };
880
881 void si_resource_copy_region(struct pipe_context *ctx,
882 struct pipe_resource *dst,
883 unsigned dst_level,
884 unsigned dstx, unsigned dsty, unsigned dstz,
885 struct pipe_resource *src,
886 unsigned src_level,
887 const struct pipe_box *src_box)
888 {
889 struct si_context *sctx = (struct si_context *)ctx;
890 struct si_texture *ssrc = (struct si_texture*)src;
891 struct si_texture *sdst = (struct si_texture*)dst;
892 struct pipe_surface *dst_view, dst_templ;
893 struct pipe_sampler_view src_templ, *src_view;
894 unsigned dst_width, dst_height, src_width0, src_height0;
895 unsigned dst_width0, dst_height0, src_force_level = 0;
896 struct pipe_box sbox, dstbox;
897
898 /* Handle buffers first. */
899 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
900 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
901 return;
902 }
903
904 if (!util_format_is_compressed(src->format) &&
905 !util_format_is_compressed(dst->format) &&
906 !util_format_is_depth_or_stencil(src->format) &&
907 src->nr_samples <= 1 &&
908 !sdst->surface.dcc_offset &&
909 !(dst->target != src->target &&
910 (src->target == PIPE_TEXTURE_1D_ARRAY || dst->target == PIPE_TEXTURE_1D_ARRAY))) {
911 si_compute_copy_image(sctx, dst, dst_level, src, src_level, dstx, dsty, dstz, src_box);
912 return;
913 }
914
915 assert(u_max_sample(dst) == u_max_sample(src));
916
917 /* The driver doesn't decompress resources automatically while
918 * u_blitter is rendering. */
919 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
920 src_box->z, src_box->z + src_box->depth - 1);
921
922 dst_width = u_minify(dst->width0, dst_level);
923 dst_height = u_minify(dst->height0, dst_level);
924 dst_width0 = dst->width0;
925 dst_height0 = dst->height0;
926 src_width0 = src->width0;
927 src_height0 = src->height0;
928
929 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
930 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
931
932 if (util_format_is_compressed(src->format) ||
933 util_format_is_compressed(dst->format)) {
934 unsigned blocksize = ssrc->surface.bpe;
935
936 if (blocksize == 8)
937 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
938 else
939 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
940 dst_templ.format = src_templ.format;
941
942 dst_width = util_format_get_nblocksx(dst->format, dst_width);
943 dst_height = util_format_get_nblocksy(dst->format, dst_height);
944 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
945 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
946 src_width0 = util_format_get_nblocksx(src->format, src_width0);
947 src_height0 = util_format_get_nblocksy(src->format, src_height0);
948
949 dstx = util_format_get_nblocksx(dst->format, dstx);
950 dsty = util_format_get_nblocksy(dst->format, dsty);
951
952 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
953 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
954 sbox.z = src_box->z;
955 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
956 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
957 sbox.depth = src_box->depth;
958 src_box = &sbox;
959
960 src_force_level = src_level;
961 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
962 if (util_format_is_subsampled_422(src->format)) {
963 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
964 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
965
966 dst_width = util_format_get_nblocksx(dst->format, dst_width);
967 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
968 src_width0 = util_format_get_nblocksx(src->format, src_width0);
969
970 dstx = util_format_get_nblocksx(dst->format, dstx);
971
972 sbox = *src_box;
973 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
974 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
975 src_box = &sbox;
976 } else {
977 unsigned blocksize = ssrc->surface.bpe;
978
979 switch (blocksize) {
980 case 1:
981 dst_templ.format = PIPE_FORMAT_R8_UNORM;
982 src_templ.format = PIPE_FORMAT_R8_UNORM;
983 break;
984 case 2:
985 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
986 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
987 break;
988 case 4:
989 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
990 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
991 break;
992 case 8:
993 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
994 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
995 break;
996 case 16:
997 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
998 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
999 break;
1000 default:
1001 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1002 util_format_short_name(src->format), blocksize);
1003 assert(0);
1004 }
1005 }
1006 }
1007
1008 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1009 * equivalent instead, which doesn't force DCC decompression.
1010 * Note that some chips avoid this issue by using SDMA.
1011 */
1012 if (util_format_is_snorm8(dst_templ.format)) {
1013 dst_templ.format = src_templ.format =
1014 util_format_snorm8_to_sint8(dst_templ.format);
1015 }
1016
1017 vi_disable_dcc_if_incompatible_format(sctx, dst, dst_level,
1018 dst_templ.format);
1019 vi_disable_dcc_if_incompatible_format(sctx, src, src_level,
1020 src_templ.format);
1021
1022 /* Initialize the surface. */
1023 dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
1024 dst_width0, dst_height0,
1025 dst_width, dst_height);
1026
1027 /* Initialize the sampler view. */
1028 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1029 src_width0, src_height0,
1030 src_force_level);
1031
1032 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1033 abs(src_box->depth), &dstbox);
1034
1035 /* Copy. */
1036 si_blitter_begin(sctx, SI_COPY);
1037 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1038 src_view, src_box, src_width0, src_height0,
1039 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1040 false);
1041 si_blitter_end(sctx);
1042
1043 pipe_surface_reference(&dst_view, NULL);
1044 pipe_sampler_view_reference(&src_view, NULL);
1045 }
1046
1047 static void si_do_CB_resolve(struct si_context *sctx,
1048 const struct pipe_blit_info *info,
1049 struct pipe_resource *dst,
1050 unsigned dst_level, unsigned dst_z,
1051 enum pipe_format format)
1052 {
1053 /* Required before and after CB_RESOLVE. */
1054 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1055
1056 si_blitter_begin(sctx, SI_COLOR_RESOLVE |
1057 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1058 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1059 info->src.resource, info->src.box.z,
1060 ~0, sctx->custom_blend_resolve,
1061 format);
1062 si_blitter_end(sctx);
1063
1064 /* Flush caches for possible texturing. */
1065 si_make_CB_shader_coherent(sctx, 1, false, true /* no DCC */);
1066 }
1067
1068 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1069 const struct pipe_blit_info *info)
1070 {
1071 struct si_context *sctx = (struct si_context*)ctx;
1072 struct si_texture *src = (struct si_texture*)info->src.resource;
1073 struct si_texture *dst = (struct si_texture*)info->dst.resource;
1074 ASSERTED struct si_texture *stmp;
1075 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1076 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1077 enum pipe_format format = info->src.format;
1078 struct pipe_resource *tmp, templ;
1079 struct pipe_blit_info blit;
1080
1081 /* Check basic requirements for hw resolve. */
1082 if (!(info->src.resource->nr_samples > 1 &&
1083 info->dst.resource->nr_samples <= 1 &&
1084 !util_format_is_pure_integer(format) &&
1085 !util_format_is_depth_or_stencil(format) &&
1086 util_max_layer(info->src.resource, 0) == 0))
1087 return false;
1088
1089 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1090 * the format is R16G16. Use R16A16, which does work.
1091 */
1092 if (format == PIPE_FORMAT_R16G16_UNORM)
1093 format = PIPE_FORMAT_R16A16_UNORM;
1094 if (format == PIPE_FORMAT_R16G16_SNORM)
1095 format = PIPE_FORMAT_R16A16_SNORM;
1096
1097 /* Check the remaining requirements for hw resolve. */
1098 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1099 !info->scissor_enable &&
1100 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1101 util_is_format_compatible(util_format_description(info->src.format),
1102 util_format_description(info->dst.format)) &&
1103 dst_width == info->src.resource->width0 &&
1104 dst_height == info->src.resource->height0 &&
1105 info->dst.box.x == 0 &&
1106 info->dst.box.y == 0 &&
1107 info->dst.box.width == dst_width &&
1108 info->dst.box.height == dst_height &&
1109 info->dst.box.depth == 1 &&
1110 info->src.box.x == 0 &&
1111 info->src.box.y == 0 &&
1112 info->src.box.width == dst_width &&
1113 info->src.box.height == dst_height &&
1114 info->src.box.depth == 1 &&
1115 !dst->surface.is_linear &&
1116 (!dst->cmask_buffer || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1117 /* Check the last constraint. */
1118 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1119 /* The next fast clear will switch to this mode to
1120 * get direct hw resolve next time if the mode is
1121 * different now.
1122 *
1123 * TODO-GFX10: This does not work in GFX10 because MSAA
1124 * is restricted to 64KB_R_X and 64KB_Z_X swizzle modes.
1125 * In some cases we could change the swizzle of the
1126 * destination texture instead, but the more general
1127 * solution is to implement compute shader resolve.
1128 */
1129 src->last_msaa_resolve_target_micro_mode =
1130 dst->surface.micro_tile_mode;
1131 goto resolve_to_temp;
1132 }
1133
1134 /* Resolving into a surface with DCC is unsupported. Since
1135 * it's being overwritten anyway, clear it to uncompressed.
1136 * This is still the fastest codepath even with this clear.
1137 */
1138 if (vi_dcc_enabled(dst, info->dst.level)) {
1139 if (!vi_dcc_clear_level(sctx, dst, info->dst.level,
1140 DCC_UNCOMPRESSED))
1141 goto resolve_to_temp;
1142
1143 dst->dirty_level_mask &= ~(1 << info->dst.level);
1144 }
1145
1146 /* Resolve directly from src to dst. */
1147 si_do_CB_resolve(sctx, info, info->dst.resource,
1148 info->dst.level, info->dst.box.z, format);
1149 return true;
1150 }
1151
1152 resolve_to_temp:
1153 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1154 * a temporary texture and blit.
1155 */
1156 memset(&templ, 0, sizeof(templ));
1157 templ.target = PIPE_TEXTURE_2D;
1158 templ.format = info->src.resource->format;
1159 templ.width0 = info->src.resource->width0;
1160 templ.height0 = info->src.resource->height0;
1161 templ.depth0 = 1;
1162 templ.array_size = 1;
1163 templ.usage = PIPE_USAGE_DEFAULT;
1164 templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING |
1165 SI_RESOURCE_FLAG_DISABLE_DCC;
1166
1167 /* The src and dst microtile modes must be the same. */
1168 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1169 templ.bind = PIPE_BIND_SCANOUT;
1170 else
1171 templ.bind = 0;
1172
1173 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1174 if (!tmp)
1175 return false;
1176 stmp = (struct si_texture*)tmp;
1177
1178 assert(!stmp->surface.is_linear);
1179 assert(src->surface.micro_tile_mode == stmp->surface.micro_tile_mode);
1180
1181 /* resolve */
1182 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1183
1184 /* blit */
1185 blit = *info;
1186 blit.src.resource = tmp;
1187 blit.src.box.z = 0;
1188
1189 si_blitter_begin(sctx, SI_BLIT |
1190 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1191 util_blitter_blit(sctx->blitter, &blit);
1192 si_blitter_end(sctx);
1193
1194 pipe_resource_reference(&tmp, NULL);
1195 return true;
1196 }
1197
1198 static void si_blit(struct pipe_context *ctx,
1199 const struct pipe_blit_info *info)
1200 {
1201 struct si_context *sctx = (struct si_context*)ctx;
1202 struct si_texture *dst = (struct si_texture *)info->dst.resource;
1203
1204 if (do_hardware_msaa_resolve(ctx, info)) {
1205 return;
1206 }
1207
1208 /* Using SDMA for copying to a linear texture in GTT is much faster.
1209 * This improves DRI PRIME performance.
1210 *
1211 * resource_copy_region can't do this yet, because dma_copy calls it
1212 * on failure (recursion).
1213 */
1214 if (dst->surface.is_linear &&
1215 util_can_blit_via_copy_region(info, false)) {
1216 sctx->dma_copy(ctx, info->dst.resource, info->dst.level,
1217 info->dst.box.x, info->dst.box.y,
1218 info->dst.box.z,
1219 info->src.resource, info->src.level,
1220 &info->src.box);
1221 return;
1222 }
1223
1224 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1225
1226 /* The driver doesn't decompress resources automatically while
1227 * u_blitter is rendering. */
1228 vi_disable_dcc_if_incompatible_format(sctx, info->src.resource,
1229 info->src.level,
1230 info->src.format);
1231 vi_disable_dcc_if_incompatible_format(sctx, info->dst.resource,
1232 info->dst.level,
1233 info->dst.format);
1234 si_decompress_subresource(ctx, info->src.resource, PIPE_MASK_RGBAZS,
1235 info->src.level,
1236 info->src.box.z,
1237 info->src.box.z + info->src.box.depth - 1);
1238
1239 if (sctx->screen->debug_flags & DBG(FORCE_SDMA) &&
1240 util_try_blit_via_copy_region(ctx, info))
1241 return;
1242
1243 si_blitter_begin(sctx, SI_BLIT |
1244 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1245 util_blitter_blit(sctx->blitter, info);
1246 si_blitter_end(sctx);
1247 }
1248
1249 static bool si_generate_mipmap(struct pipe_context *ctx,
1250 struct pipe_resource *tex,
1251 enum pipe_format format,
1252 unsigned base_level, unsigned last_level,
1253 unsigned first_layer, unsigned last_layer)
1254 {
1255 struct si_context *sctx = (struct si_context*)ctx;
1256 struct si_texture *stex = (struct si_texture *)tex;
1257
1258 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1259 return false;
1260
1261 /* The driver doesn't decompress resources automatically while
1262 * u_blitter is rendering. */
1263 vi_disable_dcc_if_incompatible_format(sctx, tex, base_level,
1264 format);
1265 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1266 base_level, first_layer, last_layer);
1267
1268 /* Clear dirty_level_mask for the levels that will be overwritten. */
1269 assert(base_level < last_level);
1270 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1271 last_level - base_level);
1272
1273 sctx->generate_mipmap_for_depth = stex->is_depth;
1274
1275 si_blitter_begin(sctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1276 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1277 base_level, last_level,
1278 first_layer, last_layer);
1279 si_blitter_end(sctx);
1280
1281 sctx->generate_mipmap_for_depth = false;
1282 return true;
1283 }
1284
1285 static void si_flush_resource(struct pipe_context *ctx,
1286 struct pipe_resource *res)
1287 {
1288 struct si_context *sctx = (struct si_context*)ctx;
1289 struct si_texture *tex = (struct si_texture*)res;
1290
1291 assert(res->target != PIPE_BUFFER);
1292 assert(!tex->dcc_separate_buffer || tex->dcc_gather_statistics);
1293
1294 /* st/dri calls flush twice per frame (not a bug), this prevents double
1295 * decompression. */
1296 if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
1297 return;
1298
1299 if (!tex->is_depth && (tex->cmask_buffer || tex->surface.dcc_offset)) {
1300 si_blit_decompress_color(sctx, tex, 0, res->last_level,
1301 0, util_max_layer(res, 0),
1302 tex->dcc_separate_buffer != NULL, false);
1303
1304 if (tex->surface.display_dcc_offset && tex->displayable_dcc_dirty) {
1305 si_retile_dcc(sctx, tex);
1306 tex->displayable_dcc_dirty = false;
1307 }
1308 }
1309
1310 /* Always do the analysis even if DCC is disabled at the moment. */
1311 if (tex->dcc_gather_statistics) {
1312 bool separate_dcc_dirty = tex->separate_dcc_dirty;
1313
1314 /* If the color buffer hasn't been unbound and fast clear hasn't
1315 * been used, separate_dcc_dirty is false, but there may have been
1316 * new rendering. Check if the color buffer is bound and assume
1317 * it's dirty.
1318 *
1319 * Note that DRI2 never unbinds window colorbuffers, which means
1320 * the DCC pipeline statistics query would never be re-set and would
1321 * keep adding new results until all free memory is exhausted if we
1322 * didn't do this.
1323 */
1324 if (!separate_dcc_dirty) {
1325 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
1326 if (sctx->framebuffer.state.cbufs[i] &&
1327 sctx->framebuffer.state.cbufs[i]->texture == res) {
1328 separate_dcc_dirty = true;
1329 break;
1330 }
1331 }
1332 }
1333
1334 if (separate_dcc_dirty) {
1335 tex->separate_dcc_dirty = false;
1336 vi_separate_dcc_process_and_reset_stats(ctx, tex);
1337 }
1338 }
1339 }
1340
1341 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
1342 {
1343 /* If graphics is disabled, we can't decompress DCC, but it shouldn't
1344 * be compressed either. The caller should simply discard it.
1345 */
1346 if (!tex->surface.dcc_offset || !sctx->has_graphics)
1347 return;
1348
1349 si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level,
1350 0, util_max_layer(&tex->buffer.b.b, 0),
1351 true, false);
1352 }
1353
1354 void si_init_blit_functions(struct si_context *sctx)
1355 {
1356 sctx->b.resource_copy_region = si_resource_copy_region;
1357
1358 if (sctx->has_graphics) {
1359 sctx->b.blit = si_blit;
1360 sctx->b.flush_resource = si_flush_resource;
1361 sctx->b.generate_mipmap = si_generate_mipmap;
1362 }
1363 }