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radeonsi: remove wrappers si_decompress_xx_textures
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_log.h"
28 #include "util/u_surface.h"
29
30 enum si_blitter_op /* bitmask */
31 {
32 SI_SAVE_TEXTURES = 1,
33 SI_SAVE_FRAMEBUFFER = 2,
34 SI_SAVE_FRAGMENT_STATE = 4,
35 SI_DISABLE_RENDER_COND = 8,
36
37 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
38
39 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
40
41 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
42 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
43
44 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
45 SI_SAVE_FRAGMENT_STATE,
46
47 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
48 SI_DISABLE_RENDER_COND,
49
50 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
51 };
52
53 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
54 {
55 struct si_context *sctx = (struct si_context *)ctx;
56
57 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
58 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
59 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
60 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
61 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
62 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
63 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
64 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
65 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
66
67 if (op & SI_SAVE_FRAGMENT_STATE) {
68 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
69 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
70 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
71 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
72 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
73 util_blitter_save_viewport(sctx->blitter, &sctx->viewports.states[0]);
74 util_blitter_save_scissor(sctx->blitter, &sctx->scissors.states[0]);
75 }
76
77 if (op & SI_SAVE_FRAMEBUFFER)
78 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
79
80 if (op & SI_SAVE_TEXTURES) {
81 util_blitter_save_fragment_sampler_states(
82 sctx->blitter, 2,
83 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
84
85 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
86 sctx->samplers[PIPE_SHADER_FRAGMENT].views);
87 }
88
89 if (op & SI_DISABLE_RENDER_COND)
90 sctx->b.render_cond_force_off = true;
91 }
92
93 static void si_blitter_end(struct pipe_context *ctx)
94 {
95 struct si_context *sctx = (struct si_context *)ctx;
96
97 sctx->b.render_cond_force_off = false;
98 }
99
100 static unsigned u_max_sample(struct pipe_resource *r)
101 {
102 return r->nr_samples ? r->nr_samples - 1 : 0;
103 }
104
105 static unsigned
106 si_blit_dbcb_copy(struct si_context *sctx,
107 struct r600_texture *src,
108 struct r600_texture *dst,
109 unsigned planes, unsigned level_mask,
110 unsigned first_layer, unsigned last_layer,
111 unsigned first_sample, unsigned last_sample)
112 {
113 struct pipe_surface surf_tmpl = {{0}};
114 unsigned layer, sample, checked_last_layer, max_layer;
115 unsigned fully_copied_levels = 0;
116
117 if (planes & PIPE_MASK_Z)
118 sctx->dbcb_depth_copy_enabled = true;
119 if (planes & PIPE_MASK_S)
120 sctx->dbcb_stencil_copy_enabled = true;
121 si_mark_atom_dirty(sctx, &sctx->db_render_state);
122
123 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
124
125 sctx->decompression_enabled = true;
126
127 while (level_mask) {
128 unsigned level = u_bit_scan(&level_mask);
129
130 /* The smaller the mipmap level, the less layers there are
131 * as far as 3D textures are concerned. */
132 max_layer = util_max_layer(&src->resource.b.b, level);
133 checked_last_layer = MIN2(last_layer, max_layer);
134
135 surf_tmpl.u.tex.level = level;
136
137 for (layer = first_layer; layer <= checked_last_layer; layer++) {
138 struct pipe_surface *zsurf, *cbsurf;
139
140 surf_tmpl.format = src->resource.b.b.format;
141 surf_tmpl.u.tex.first_layer = layer;
142 surf_tmpl.u.tex.last_layer = layer;
143
144 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
145
146 surf_tmpl.format = dst->resource.b.b.format;
147 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
148
149 for (sample = first_sample; sample <= last_sample; sample++) {
150 if (sample != sctx->dbcb_copy_sample) {
151 sctx->dbcb_copy_sample = sample;
152 si_mark_atom_dirty(sctx, &sctx->db_render_state);
153 }
154
155 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
156 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
157 sctx->custom_dsa_flush, 1.0f);
158 si_blitter_end(&sctx->b.b);
159 }
160
161 pipe_surface_reference(&zsurf, NULL);
162 pipe_surface_reference(&cbsurf, NULL);
163 }
164
165 if (first_layer == 0 && last_layer >= max_layer &&
166 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
167 fully_copied_levels |= 1u << level;
168 }
169
170 sctx->decompression_enabled = false;
171 sctx->dbcb_depth_copy_enabled = false;
172 sctx->dbcb_stencil_copy_enabled = false;
173 si_mark_atom_dirty(sctx, &sctx->db_render_state);
174
175 return fully_copied_levels;
176 }
177
178 static void si_blit_decompress_depth(struct pipe_context *ctx,
179 struct r600_texture *texture,
180 struct r600_texture *staging,
181 unsigned first_level, unsigned last_level,
182 unsigned first_layer, unsigned last_layer,
183 unsigned first_sample, unsigned last_sample)
184 {
185 const struct util_format_description *desc;
186 unsigned planes = 0;
187
188 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
189
190 desc = util_format_description(staging->resource.b.b.format);
191
192 if (util_format_has_depth(desc))
193 planes |= PIPE_MASK_Z;
194 if (util_format_has_stencil(desc))
195 planes |= PIPE_MASK_S;
196
197 si_blit_dbcb_copy(
198 (struct si_context *)ctx, texture, staging, planes,
199 u_bit_consecutive(first_level, last_level - first_level + 1),
200 first_layer, last_layer, first_sample, last_sample);
201 }
202
203 /* Helper function for si_blit_decompress_zs_in_place.
204 */
205 static void
206 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
207 struct r600_texture *texture,
208 unsigned planes, unsigned level_mask,
209 unsigned first_layer, unsigned last_layer)
210 {
211 struct pipe_surface *zsurf, surf_tmpl = {{0}};
212 unsigned layer, max_layer, checked_last_layer;
213 unsigned fully_decompressed_mask = 0;
214
215 if (!level_mask)
216 return;
217
218 if (planes & PIPE_MASK_S)
219 sctx->db_flush_stencil_inplace = true;
220 if (planes & PIPE_MASK_Z)
221 sctx->db_flush_depth_inplace = true;
222 si_mark_atom_dirty(sctx, &sctx->db_render_state);
223
224 surf_tmpl.format = texture->resource.b.b.format;
225
226 sctx->decompression_enabled = true;
227
228 while (level_mask) {
229 unsigned level = u_bit_scan(&level_mask);
230
231 surf_tmpl.u.tex.level = level;
232
233 /* The smaller the mipmap level, the less layers there are
234 * as far as 3D textures are concerned. */
235 max_layer = util_max_layer(&texture->resource.b.b, level);
236 checked_last_layer = MIN2(last_layer, max_layer);
237
238 for (layer = first_layer; layer <= checked_last_layer; layer++) {
239 surf_tmpl.u.tex.first_layer = layer;
240 surf_tmpl.u.tex.last_layer = layer;
241
242 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
243
244 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
245 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
246 sctx->custom_dsa_flush,
247 1.0f);
248 si_blitter_end(&sctx->b.b);
249
250 pipe_surface_reference(&zsurf, NULL);
251 }
252
253 /* The texture will always be dirty if some layers aren't flushed.
254 * I don't think this case occurs often though. */
255 if (first_layer == 0 && last_layer >= max_layer) {
256 fully_decompressed_mask |= 1u << level;
257 }
258 }
259
260 if (planes & PIPE_MASK_Z)
261 texture->dirty_level_mask &= ~fully_decompressed_mask;
262 if (planes & PIPE_MASK_S)
263 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
264
265 sctx->decompression_enabled = false;
266 sctx->db_flush_depth_inplace = false;
267 sctx->db_flush_stencil_inplace = false;
268 si_mark_atom_dirty(sctx, &sctx->db_render_state);
269 }
270
271 /* Helper function of si_flush_depth_texture: decompress the given levels
272 * of Z and/or S planes in place.
273 */
274 static void
275 si_blit_decompress_zs_in_place(struct si_context *sctx,
276 struct r600_texture *texture,
277 unsigned levels_z, unsigned levels_s,
278 unsigned first_layer, unsigned last_layer)
279 {
280 unsigned both = levels_z & levels_s;
281
282 /* First, do combined Z & S decompresses for levels that need it. */
283 if (both) {
284 si_blit_decompress_zs_planes_in_place(
285 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
286 both,
287 first_layer, last_layer);
288 levels_z &= ~both;
289 levels_s &= ~both;
290 }
291
292 /* Now do separate Z and S decompresses. */
293 if (levels_z) {
294 si_blit_decompress_zs_planes_in_place(
295 sctx, texture, PIPE_MASK_Z,
296 levels_z,
297 first_layer, last_layer);
298 }
299
300 if (levels_s) {
301 si_blit_decompress_zs_planes_in_place(
302 sctx, texture, PIPE_MASK_S,
303 levels_s,
304 first_layer, last_layer);
305 }
306 }
307
308 static void
309 si_decompress_depth(struct si_context *sctx,
310 struct r600_texture *tex,
311 unsigned required_planes,
312 unsigned first_level, unsigned last_level,
313 unsigned first_layer, unsigned last_layer)
314 {
315 unsigned inplace_planes = 0;
316 unsigned copy_planes = 0;
317 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
318 unsigned levels_z = 0;
319 unsigned levels_s = 0;
320
321 if (required_planes & PIPE_MASK_Z) {
322 levels_z = level_mask & tex->dirty_level_mask;
323
324 if (levels_z) {
325 if (r600_can_sample_zs(tex, false))
326 inplace_planes |= PIPE_MASK_Z;
327 else
328 copy_planes |= PIPE_MASK_Z;
329 }
330 }
331 if (required_planes & PIPE_MASK_S) {
332 levels_s = level_mask & tex->stencil_dirty_level_mask;
333
334 if (levels_s) {
335 if (r600_can_sample_zs(tex, true))
336 inplace_planes |= PIPE_MASK_S;
337 else
338 copy_planes |= PIPE_MASK_S;
339 }
340 }
341
342 if (unlikely(sctx->b.log))
343 u_log_printf(sctx->b.log,
344 "\n------------------------------------------------\n"
345 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n",
346 first_level, last_level, levels_z, levels_s);
347
348 /* We may have to allocate the flushed texture here when called from
349 * si_decompress_subresource.
350 */
351 if (copy_planes &&
352 (tex->flushed_depth_texture ||
353 si_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
354 struct r600_texture *dst = tex->flushed_depth_texture;
355 unsigned fully_copied_levels;
356 unsigned levels = 0;
357
358 assert(tex->flushed_depth_texture);
359
360 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
361 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
362
363 if (copy_planes & PIPE_MASK_Z) {
364 levels |= levels_z;
365 levels_z = 0;
366 }
367 if (copy_planes & PIPE_MASK_S) {
368 levels |= levels_s;
369 levels_s = 0;
370 }
371
372 fully_copied_levels = si_blit_dbcb_copy(
373 sctx, tex, dst, copy_planes, levels,
374 first_layer, last_layer,
375 0, u_max_sample(&tex->resource.b.b));
376
377 if (copy_planes & PIPE_MASK_Z)
378 tex->dirty_level_mask &= ~fully_copied_levels;
379 if (copy_planes & PIPE_MASK_S)
380 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
381 }
382
383 if (inplace_planes) {
384 bool has_htile = r600_htile_enabled(tex, first_level);
385 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
386
387 /* Don't decompress if there is no HTILE or when HTILE is
388 * TC-compatible. */
389 if (has_htile && !tc_compat_htile) {
390 si_blit_decompress_zs_in_place(
391 sctx, tex,
392 levels_z, levels_s,
393 first_layer, last_layer);
394 } else {
395 /* This is only a cache flush.
396 *
397 * Only clear the mask that we are flushing, because
398 * si_make_DB_shader_coherent() treats different levels
399 * and depth and stencil differently.
400 */
401 if (inplace_planes & PIPE_MASK_Z)
402 tex->dirty_level_mask &= ~levels_z;
403 if (inplace_planes & PIPE_MASK_S)
404 tex->stencil_dirty_level_mask &= ~levels_s;
405 }
406
407 /* Only in-place decompression needs to flush DB caches, or
408 * when we don't decompress but TC-compatible planes are dirty.
409 */
410 si_make_DB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
411 inplace_planes & PIPE_MASK_S,
412 tc_compat_htile);
413 }
414 /* set_framebuffer_state takes care of coherency for single-sample.
415 * The DB->CB copy uses CB for the final writes.
416 */
417 if (copy_planes && tex->resource.b.b.nr_samples > 1)
418 si_make_CB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
419 false);
420 }
421
422 static void
423 si_decompress_sampler_depth_textures(struct si_context *sctx,
424 struct si_samplers *textures)
425 {
426 unsigned i;
427 unsigned mask = textures->needs_depth_decompress_mask;
428
429 while (mask) {
430 struct pipe_sampler_view *view;
431 struct si_sampler_view *sview;
432 struct r600_texture *tex;
433
434 i = u_bit_scan(&mask);
435
436 view = textures->views[i];
437 assert(view);
438 sview = (struct si_sampler_view*)view;
439
440 tex = (struct r600_texture *)view->texture;
441 assert(tex->db_compatible);
442
443 si_decompress_depth(sctx, tex,
444 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
445 view->u.tex.first_level, view->u.tex.last_level,
446 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
447 }
448 }
449
450 static void si_blit_decompress_color(struct pipe_context *ctx,
451 struct r600_texture *rtex,
452 unsigned first_level, unsigned last_level,
453 unsigned first_layer, unsigned last_layer,
454 bool need_dcc_decompress)
455 {
456 struct si_context *sctx = (struct si_context *)ctx;
457 void* custom_blend;
458 unsigned layer, checked_last_layer, max_layer;
459 unsigned level_mask =
460 u_bit_consecutive(first_level, last_level - first_level + 1);
461
462 if (!need_dcc_decompress)
463 level_mask &= rtex->dirty_level_mask;
464 if (!level_mask)
465 return;
466
467 if (unlikely(sctx->b.log))
468 u_log_printf(sctx->b.log,
469 "\n------------------------------------------------\n"
470 "Decompress Color (levels %u - %u, mask 0x%x)\n\n",
471 first_level, last_level, level_mask);
472
473 if (need_dcc_decompress) {
474 custom_blend = sctx->custom_blend_dcc_decompress;
475
476 assert(rtex->dcc_offset);
477
478 /* disable levels without DCC */
479 for (int i = first_level; i <= last_level; i++) {
480 if (!vi_dcc_enabled(rtex, i))
481 level_mask &= ~(1 << i);
482 }
483 } else if (rtex->fmask.size) {
484 custom_blend = sctx->custom_blend_fmask_decompress;
485 } else {
486 custom_blend = sctx->custom_blend_eliminate_fastclear;
487 }
488
489 sctx->decompression_enabled = true;
490
491 while (level_mask) {
492 unsigned level = u_bit_scan(&level_mask);
493
494 /* The smaller the mipmap level, the less layers there are
495 * as far as 3D textures are concerned. */
496 max_layer = util_max_layer(&rtex->resource.b.b, level);
497 checked_last_layer = MIN2(last_layer, max_layer);
498
499 for (layer = first_layer; layer <= checked_last_layer; layer++) {
500 struct pipe_surface *cbsurf, surf_tmpl;
501
502 surf_tmpl.format = rtex->resource.b.b.format;
503 surf_tmpl.u.tex.level = level;
504 surf_tmpl.u.tex.first_layer = layer;
505 surf_tmpl.u.tex.last_layer = layer;
506 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
507
508 /* Required before and after FMASK and DCC_DECOMPRESS. */
509 if (custom_blend == sctx->custom_blend_fmask_decompress ||
510 custom_blend == sctx->custom_blend_dcc_decompress)
511 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
512
513 si_blitter_begin(ctx, SI_DECOMPRESS);
514 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
515 si_blitter_end(ctx);
516
517 if (custom_blend == sctx->custom_blend_fmask_decompress ||
518 custom_blend == sctx->custom_blend_dcc_decompress)
519 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
520
521 pipe_surface_reference(&cbsurf, NULL);
522 }
523
524 /* The texture will always be dirty if some layers aren't flushed.
525 * I don't think this case occurs often though. */
526 if (first_layer == 0 && last_layer >= max_layer) {
527 rtex->dirty_level_mask &= ~(1 << level);
528 }
529 }
530
531 sctx->decompression_enabled = false;
532 si_make_CB_shader_coherent(sctx, rtex->resource.b.b.nr_samples,
533 vi_dcc_enabled(rtex, first_level));
534 }
535
536 static void
537 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
538 unsigned first_level, unsigned last_level)
539 {
540 /* CMASK or DCC can be discarded and we can still end up here. */
541 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
542 return;
543
544 si_blit_decompress_color(&sctx->b.b, tex, first_level, last_level, 0,
545 util_max_layer(&tex->resource.b.b, first_level),
546 false);
547 }
548
549 static void
550 si_decompress_sampler_color_textures(struct si_context *sctx,
551 struct si_samplers *textures)
552 {
553 unsigned i;
554 unsigned mask = textures->needs_color_decompress_mask;
555
556 while (mask) {
557 struct pipe_sampler_view *view;
558 struct r600_texture *tex;
559
560 i = u_bit_scan(&mask);
561
562 view = textures->views[i];
563 assert(view);
564
565 tex = (struct r600_texture *)view->texture;
566
567 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
568 view->u.tex.last_level);
569 }
570 }
571
572 static void
573 si_decompress_image_color_textures(struct si_context *sctx,
574 struct si_images *images)
575 {
576 unsigned i;
577 unsigned mask = images->needs_color_decompress_mask;
578
579 while (mask) {
580 const struct pipe_image_view *view;
581 struct r600_texture *tex;
582
583 i = u_bit_scan(&mask);
584
585 view = &images->views[i];
586 assert(view->resource->target != PIPE_BUFFER);
587
588 tex = (struct r600_texture *)view->resource;
589
590 si_decompress_color_texture(sctx, tex, view->u.tex.level,
591 view->u.tex.level);
592 }
593 }
594
595 static void si_check_render_feedback_texture(struct si_context *sctx,
596 struct r600_texture *tex,
597 unsigned first_level,
598 unsigned last_level,
599 unsigned first_layer,
600 unsigned last_layer)
601 {
602 bool render_feedback = false;
603
604 if (!tex->dcc_offset)
605 return;
606
607 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
608 struct r600_surface * surf;
609
610 if (!sctx->framebuffer.state.cbufs[j])
611 continue;
612
613 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
614
615 if (tex == (struct r600_texture *)surf->base.texture &&
616 surf->base.u.tex.level >= first_level &&
617 surf->base.u.tex.level <= last_level &&
618 surf->base.u.tex.first_layer <= last_layer &&
619 surf->base.u.tex.last_layer >= first_layer) {
620 render_feedback = true;
621 break;
622 }
623 }
624
625 if (render_feedback)
626 si_texture_disable_dcc(&sctx->b, tex);
627 }
628
629 static void si_check_render_feedback_textures(struct si_context *sctx,
630 struct si_samplers *textures)
631 {
632 uint32_t mask = textures->enabled_mask;
633
634 while (mask) {
635 const struct pipe_sampler_view *view;
636 struct r600_texture *tex;
637
638 unsigned i = u_bit_scan(&mask);
639
640 view = textures->views[i];
641 if(view->texture->target == PIPE_BUFFER)
642 continue;
643
644 tex = (struct r600_texture *)view->texture;
645
646 si_check_render_feedback_texture(sctx, tex,
647 view->u.tex.first_level,
648 view->u.tex.last_level,
649 view->u.tex.first_layer,
650 view->u.tex.last_layer);
651 }
652 }
653
654 static void si_check_render_feedback_images(struct si_context *sctx,
655 struct si_images *images)
656 {
657 uint32_t mask = images->enabled_mask;
658
659 while (mask) {
660 const struct pipe_image_view *view;
661 struct r600_texture *tex;
662
663 unsigned i = u_bit_scan(&mask);
664
665 view = &images->views[i];
666 if (view->resource->target == PIPE_BUFFER)
667 continue;
668
669 tex = (struct r600_texture *)view->resource;
670
671 si_check_render_feedback_texture(sctx, tex,
672 view->u.tex.level,
673 view->u.tex.level,
674 view->u.tex.first_layer,
675 view->u.tex.last_layer);
676 }
677 }
678
679 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
680 {
681 util_dynarray_foreach(&sctx->resident_tex_handles,
682 struct si_texture_handle *, tex_handle) {
683 struct pipe_sampler_view *view;
684 struct r600_texture *tex;
685
686 view = (*tex_handle)->view;
687 if (view->texture->target == PIPE_BUFFER)
688 continue;
689
690 tex = (struct r600_texture *)view->texture;
691
692 si_check_render_feedback_texture(sctx, tex,
693 view->u.tex.first_level,
694 view->u.tex.last_level,
695 view->u.tex.first_layer,
696 view->u.tex.last_layer);
697 }
698 }
699
700 static void si_check_render_feedback_resident_images(struct si_context *sctx)
701 {
702 util_dynarray_foreach(&sctx->resident_img_handles,
703 struct si_image_handle *, img_handle) {
704 struct pipe_image_view *view;
705 struct r600_texture *tex;
706
707 view = &(*img_handle)->view;
708 if (view->resource->target == PIPE_BUFFER)
709 continue;
710
711 tex = (struct r600_texture *)view->resource;
712
713 si_check_render_feedback_texture(sctx, tex,
714 view->u.tex.level,
715 view->u.tex.level,
716 view->u.tex.first_layer,
717 view->u.tex.last_layer);
718 }
719 }
720
721 static void si_check_render_feedback(struct si_context *sctx)
722 {
723
724 if (!sctx->need_check_render_feedback)
725 return;
726
727 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
728 si_check_render_feedback_images(sctx, &sctx->images[i]);
729 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
730 }
731
732 si_check_render_feedback_resident_images(sctx);
733 si_check_render_feedback_resident_textures(sctx);
734
735 sctx->need_check_render_feedback = false;
736 }
737
738 static void si_decompress_resident_textures(struct si_context *sctx)
739 {
740 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
741 struct si_texture_handle *, tex_handle) {
742 struct pipe_sampler_view *view = (*tex_handle)->view;
743 struct r600_texture *tex = (struct r600_texture *)view->texture;
744
745 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
746 view->u.tex.last_level);
747 }
748
749 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
750 struct si_texture_handle *, tex_handle) {
751 struct pipe_sampler_view *view = (*tex_handle)->view;
752 struct si_sampler_view *sview = (struct si_sampler_view *)view;
753 struct r600_texture *tex = (struct r600_texture *)view->texture;
754
755 si_decompress_depth(sctx, tex,
756 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
757 view->u.tex.first_level, view->u.tex.last_level,
758 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
759 }
760 }
761
762 static void si_decompress_resident_images(struct si_context *sctx)
763 {
764 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
765 struct si_image_handle *, img_handle) {
766 struct pipe_image_view *view = &(*img_handle)->view;
767 struct r600_texture *tex = (struct r600_texture *)view->resource;
768
769 si_decompress_color_texture(sctx, tex, view->u.tex.level,
770 view->u.tex.level);
771 }
772 }
773
774 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
775 {
776 unsigned compressed_colortex_counter, mask;
777
778 if (sctx->blitter->running)
779 return;
780
781 /* Update the compressed_colortex_mask if necessary. */
782 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
783 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
784 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
785 si_update_needs_color_decompress_masks(sctx);
786 }
787
788 /* Decompress color & depth textures if needed. */
789 mask = sctx->shader_needs_decompress_mask & shader_mask;
790 while (mask) {
791 unsigned i = u_bit_scan(&mask);
792
793 if (sctx->samplers[i].needs_depth_decompress_mask) {
794 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
795 }
796 if (sctx->samplers[i].needs_color_decompress_mask) {
797 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
798 }
799 if (sctx->images[i].needs_color_decompress_mask) {
800 si_decompress_image_color_textures(sctx, &sctx->images[i]);
801 }
802 }
803
804 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
805 if (sctx->uses_bindless_samplers)
806 si_decompress_resident_textures(sctx);
807 if (sctx->uses_bindless_images)
808 si_decompress_resident_images(sctx);
809 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
810 if (sctx->cs_shader_state.program->uses_bindless_samplers)
811 si_decompress_resident_textures(sctx);
812 if (sctx->cs_shader_state.program->uses_bindless_images)
813 si_decompress_resident_images(sctx);
814 }
815
816 si_check_render_feedback(sctx);
817 }
818
819 static void si_clear(struct pipe_context *ctx, unsigned buffers,
820 const union pipe_color_union *color,
821 double depth, unsigned stencil)
822 {
823 struct si_context *sctx = (struct si_context *)ctx;
824 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
825 struct pipe_surface *zsbuf = fb->zsbuf;
826 struct r600_texture *zstex =
827 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
828
829 if (buffers & PIPE_CLEAR_COLOR) {
830 si_do_fast_color_clear(&sctx->b, fb,
831 &sctx->framebuffer.atom, &buffers,
832 &sctx->framebuffer.dirty_cbufs,
833 color);
834 if (!buffers)
835 return; /* all buffers have been fast cleared */
836 }
837
838 if (buffers & PIPE_CLEAR_COLOR) {
839 int i;
840
841 /* These buffers cannot use fast clear, make sure to disable expansion. */
842 for (i = 0; i < fb->nr_cbufs; i++) {
843 struct r600_texture *tex;
844
845 /* If not clearing this buffer, skip. */
846 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
847 continue;
848
849 if (!fb->cbufs[i])
850 continue;
851
852 tex = (struct r600_texture *)fb->cbufs[i]->texture;
853 if (tex->fmask.size == 0)
854 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
855 }
856 }
857
858 if (zstex &&
859 r600_htile_enabled(zstex, zsbuf->u.tex.level) &&
860 zsbuf->u.tex.first_layer == 0 &&
861 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
862 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
863 if (buffers & PIPE_CLEAR_DEPTH &&
864 (!zstex->tc_compatible_htile ||
865 depth == 0 || depth == 1)) {
866 /* Need to disable EXPCLEAR temporarily if clearing
867 * to a new value. */
868 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
869 sctx->db_depth_disable_expclear = true;
870 }
871
872 zstex->depth_clear_value = depth;
873 sctx->framebuffer.dirty_zsbuf = true;
874 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
875 sctx->db_depth_clear = true;
876 si_mark_atom_dirty(sctx, &sctx->db_render_state);
877 }
878
879 /* TC-compatible HTILE only supports stencil clears to 0. */
880 if (buffers & PIPE_CLEAR_STENCIL &&
881 (!zstex->tc_compatible_htile || stencil == 0)) {
882 stencil &= 0xff;
883
884 /* Need to disable EXPCLEAR temporarily if clearing
885 * to a new value. */
886 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
887 sctx->db_stencil_disable_expclear = true;
888 }
889
890 zstex->stencil_clear_value = stencil;
891 sctx->framebuffer.dirty_zsbuf = true;
892 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
893 sctx->db_stencil_clear = true;
894 si_mark_atom_dirty(sctx, &sctx->db_render_state);
895 }
896
897 /* TODO: Find out what's wrong here. Fast depth clear leads to
898 * corruption in ARK: Survival Evolved, but that may just be
899 * a coincidence and the root cause is elsewhere.
900 *
901 * The corruption can be fixed by putting the DB metadata flush
902 * before or after the depth clear. (suprisingly)
903 *
904 * https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
905 *
906 * This hack decreases back-to-back ClearDepth performance.
907 */
908 if (sctx->screen->clear_db_meta_before_clear)
909 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META |
910 SI_CONTEXT_PS_PARTIAL_FLUSH;
911 }
912
913 si_blitter_begin(ctx, SI_CLEAR);
914 util_blitter_clear(sctx->blitter, fb->width, fb->height,
915 util_framebuffer_get_num_layers(fb),
916 buffers, color, depth, stencil);
917 si_blitter_end(ctx);
918
919 if (sctx->db_depth_clear) {
920 sctx->db_depth_clear = false;
921 sctx->db_depth_disable_expclear = false;
922 zstex->depth_cleared = true;
923 si_mark_atom_dirty(sctx, &sctx->db_render_state);
924 }
925
926 if (sctx->db_stencil_clear) {
927 sctx->db_stencil_clear = false;
928 sctx->db_stencil_disable_expclear = false;
929 zstex->stencil_cleared = true;
930 si_mark_atom_dirty(sctx, &sctx->db_render_state);
931 }
932 }
933
934 static void si_clear_render_target(struct pipe_context *ctx,
935 struct pipe_surface *dst,
936 const union pipe_color_union *color,
937 unsigned dstx, unsigned dsty,
938 unsigned width, unsigned height,
939 bool render_condition_enabled)
940 {
941 struct si_context *sctx = (struct si_context *)ctx;
942
943 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
944 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
945 util_blitter_clear_render_target(sctx->blitter, dst, color,
946 dstx, dsty, width, height);
947 si_blitter_end(ctx);
948 }
949
950 static void si_clear_depth_stencil(struct pipe_context *ctx,
951 struct pipe_surface *dst,
952 unsigned clear_flags,
953 double depth,
954 unsigned stencil,
955 unsigned dstx, unsigned dsty,
956 unsigned width, unsigned height,
957 bool render_condition_enabled)
958 {
959 struct si_context *sctx = (struct si_context *)ctx;
960
961 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
962 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
963 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
964 dstx, dsty, width, height);
965 si_blitter_end(ctx);
966 }
967
968 /* Helper for decompressing a portion of a color or depth resource before
969 * blitting if any decompression is needed.
970 * The driver doesn't decompress resources automatically while u_blitter is
971 * rendering. */
972 static void si_decompress_subresource(struct pipe_context *ctx,
973 struct pipe_resource *tex,
974 unsigned planes, unsigned level,
975 unsigned first_layer, unsigned last_layer)
976 {
977 struct si_context *sctx = (struct si_context *)ctx;
978 struct r600_texture *rtex = (struct r600_texture*)tex;
979
980 if (rtex->db_compatible) {
981 planes &= PIPE_MASK_Z | PIPE_MASK_S;
982
983 if (!rtex->surface.has_stencil)
984 planes &= ~PIPE_MASK_S;
985
986 /* If we've rendered into the framebuffer and it's a blitting
987 * source, make sure the decompression pass is invoked
988 * by dirtying the framebuffer.
989 */
990 if (sctx->framebuffer.state.zsbuf &&
991 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
992 sctx->framebuffer.state.zsbuf->texture == tex)
993 si_update_fb_dirtiness_after_rendering(sctx);
994
995 si_decompress_depth(sctx, rtex, planes,
996 level, level,
997 first_layer, last_layer);
998 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
999 /* If we've rendered into the framebuffer and it's a blitting
1000 * source, make sure the decompression pass is invoked
1001 * by dirtying the framebuffer.
1002 */
1003 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
1004 if (sctx->framebuffer.state.cbufs[i] &&
1005 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
1006 sctx->framebuffer.state.cbufs[i]->texture == tex) {
1007 si_update_fb_dirtiness_after_rendering(sctx);
1008 break;
1009 }
1010 }
1011
1012 si_blit_decompress_color(ctx, rtex, level, level,
1013 first_layer, last_layer, false);
1014 }
1015 }
1016
1017 struct texture_orig_info {
1018 unsigned format;
1019 unsigned width0;
1020 unsigned height0;
1021 unsigned npix_x;
1022 unsigned npix_y;
1023 unsigned npix0_x;
1024 unsigned npix0_y;
1025 };
1026
1027 void si_resource_copy_region(struct pipe_context *ctx,
1028 struct pipe_resource *dst,
1029 unsigned dst_level,
1030 unsigned dstx, unsigned dsty, unsigned dstz,
1031 struct pipe_resource *src,
1032 unsigned src_level,
1033 const struct pipe_box *src_box)
1034 {
1035 struct si_context *sctx = (struct si_context *)ctx;
1036 struct r600_texture *rsrc = (struct r600_texture*)src;
1037 struct pipe_surface *dst_view, dst_templ;
1038 struct pipe_sampler_view src_templ, *src_view;
1039 unsigned dst_width, dst_height, src_width0, src_height0;
1040 unsigned dst_width0, dst_height0, src_force_level = 0;
1041 struct pipe_box sbox, dstbox;
1042
1043 /* Handle buffers first. */
1044 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
1045 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
1046 return;
1047 }
1048
1049 assert(u_max_sample(dst) == u_max_sample(src));
1050
1051 /* The driver doesn't decompress resources automatically while
1052 * u_blitter is rendering. */
1053 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
1054 src_box->z, src_box->z + src_box->depth - 1);
1055
1056 dst_width = u_minify(dst->width0, dst_level);
1057 dst_height = u_minify(dst->height0, dst_level);
1058 dst_width0 = dst->width0;
1059 dst_height0 = dst->height0;
1060 src_width0 = src->width0;
1061 src_height0 = src->height0;
1062
1063 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
1064 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
1065
1066 if (util_format_is_compressed(src->format) ||
1067 util_format_is_compressed(dst->format)) {
1068 unsigned blocksize = rsrc->surface.bpe;
1069
1070 if (blocksize == 8)
1071 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
1072 else
1073 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
1074 dst_templ.format = src_templ.format;
1075
1076 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1077 dst_height = util_format_get_nblocksy(dst->format, dst_height);
1078 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1079 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
1080 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1081 src_height0 = util_format_get_nblocksy(src->format, src_height0);
1082
1083 dstx = util_format_get_nblocksx(dst->format, dstx);
1084 dsty = util_format_get_nblocksy(dst->format, dsty);
1085
1086 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1087 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
1088 sbox.z = src_box->z;
1089 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1090 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
1091 sbox.depth = src_box->depth;
1092 src_box = &sbox;
1093
1094 src_force_level = src_level;
1095 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
1096 if (util_format_is_subsampled_422(src->format)) {
1097 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1098 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1099
1100 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1101 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1102 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1103
1104 dstx = util_format_get_nblocksx(dst->format, dstx);
1105
1106 sbox = *src_box;
1107 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1108 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1109 src_box = &sbox;
1110 } else {
1111 unsigned blocksize = rsrc->surface.bpe;
1112
1113 switch (blocksize) {
1114 case 1:
1115 dst_templ.format = PIPE_FORMAT_R8_UNORM;
1116 src_templ.format = PIPE_FORMAT_R8_UNORM;
1117 break;
1118 case 2:
1119 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
1120 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
1121 break;
1122 case 4:
1123 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1124 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1125 break;
1126 case 8:
1127 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1128 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1129 break;
1130 case 16:
1131 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1132 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1133 break;
1134 default:
1135 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1136 util_format_short_name(src->format), blocksize);
1137 assert(0);
1138 }
1139 }
1140 }
1141
1142 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1143 * equivalent instead, which doesn't force DCC decompression.
1144 * Note that some chips avoid this issue by using SDMA.
1145 */
1146 if (util_format_is_snorm8(dst_templ.format)) {
1147 switch (dst_templ.format) {
1148 case PIPE_FORMAT_R8_SNORM:
1149 dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
1150 break;
1151 case PIPE_FORMAT_R8G8_SNORM:
1152 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
1153 break;
1154 case PIPE_FORMAT_R8G8B8X8_SNORM:
1155 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
1156 break;
1157 case PIPE_FORMAT_R8G8B8A8_SNORM:
1158 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1159 case PIPE_FORMAT_A8B8G8R8_SNORM:
1160 case PIPE_FORMAT_X8B8G8R8_SNORM:
1161 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
1162 break;
1163 case PIPE_FORMAT_A8_SNORM:
1164 dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
1165 break;
1166 case PIPE_FORMAT_L8_SNORM:
1167 dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
1168 break;
1169 case PIPE_FORMAT_L8A8_SNORM:
1170 dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
1171 break;
1172 case PIPE_FORMAT_I8_SNORM:
1173 dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
1174 break;
1175 default:; /* fall through */
1176 }
1177 }
1178
1179 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
1180 dst_templ.format);
1181 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
1182 src_templ.format);
1183
1184 /* Initialize the surface. */
1185 dst_view = si_create_surface_custom(ctx, dst, &dst_templ,
1186 dst_width0, dst_height0,
1187 dst_width, dst_height);
1188
1189 /* Initialize the sampler view. */
1190 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1191 src_width0, src_height0,
1192 src_force_level);
1193
1194 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1195 abs(src_box->depth), &dstbox);
1196
1197 /* Copy. */
1198 si_blitter_begin(ctx, SI_COPY);
1199 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1200 src_view, src_box, src_width0, src_height0,
1201 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1202 false);
1203 si_blitter_end(ctx);
1204
1205 pipe_surface_reference(&dst_view, NULL);
1206 pipe_sampler_view_reference(&src_view, NULL);
1207 }
1208
1209 static void si_do_CB_resolve(struct si_context *sctx,
1210 const struct pipe_blit_info *info,
1211 struct pipe_resource *dst,
1212 unsigned dst_level, unsigned dst_z,
1213 enum pipe_format format)
1214 {
1215 /* Required before and after CB_RESOLVE. */
1216 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1217
1218 si_blitter_begin(&sctx->b.b, SI_COLOR_RESOLVE |
1219 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1220 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1221 info->src.resource, info->src.box.z,
1222 ~0, sctx->custom_blend_resolve,
1223 format);
1224 si_blitter_end(&sctx->b.b);
1225
1226 /* Flush caches for possible texturing. */
1227 si_make_CB_shader_coherent(sctx, 1, false);
1228 }
1229
1230 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1231 const struct pipe_blit_info *info)
1232 {
1233 struct si_context *sctx = (struct si_context*)ctx;
1234 struct r600_texture *src = (struct r600_texture*)info->src.resource;
1235 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
1236 MAYBE_UNUSED struct r600_texture *rtmp;
1237 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1238 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1239 enum pipe_format format = info->src.format;
1240 struct pipe_resource *tmp, templ;
1241 struct pipe_blit_info blit;
1242
1243 /* Check basic requirements for hw resolve. */
1244 if (!(info->src.resource->nr_samples > 1 &&
1245 info->dst.resource->nr_samples <= 1 &&
1246 !util_format_is_pure_integer(format) &&
1247 !util_format_is_depth_or_stencil(format) &&
1248 util_max_layer(info->src.resource, 0) == 0))
1249 return false;
1250
1251 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1252 * the format is R16G16. Use R16A16, which does work.
1253 */
1254 if (format == PIPE_FORMAT_R16G16_UNORM)
1255 format = PIPE_FORMAT_R16A16_UNORM;
1256 if (format == PIPE_FORMAT_R16G16_SNORM)
1257 format = PIPE_FORMAT_R16A16_SNORM;
1258
1259 /* Check the remaining requirements for hw resolve. */
1260 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1261 !info->scissor_enable &&
1262 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1263 util_is_format_compatible(util_format_description(info->src.format),
1264 util_format_description(info->dst.format)) &&
1265 dst_width == info->src.resource->width0 &&
1266 dst_height == info->src.resource->height0 &&
1267 info->dst.box.x == 0 &&
1268 info->dst.box.y == 0 &&
1269 info->dst.box.width == dst_width &&
1270 info->dst.box.height == dst_height &&
1271 info->dst.box.depth == 1 &&
1272 info->src.box.x == 0 &&
1273 info->src.box.y == 0 &&
1274 info->src.box.width == dst_width &&
1275 info->src.box.height == dst_height &&
1276 info->src.box.depth == 1 &&
1277 !dst->surface.is_linear &&
1278 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1279 /* Check the last constraint. */
1280 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1281 /* The next fast clear will switch to this mode to
1282 * get direct hw resolve next time if the mode is
1283 * different now.
1284 */
1285 src->last_msaa_resolve_target_micro_mode =
1286 dst->surface.micro_tile_mode;
1287 goto resolve_to_temp;
1288 }
1289
1290 /* Resolving into a surface with DCC is unsupported. Since
1291 * it's being overwritten anyway, clear it to uncompressed.
1292 * This is still the fastest codepath even with this clear.
1293 */
1294 if (vi_dcc_enabled(dst, info->dst.level)) {
1295 /* TODO: Implement per-level DCC clears for GFX9. */
1296 if (sctx->b.chip_class >= GFX9 &&
1297 info->dst.resource->last_level != 0)
1298 goto resolve_to_temp;
1299
1300 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1301 0xFFFFFFFF);
1302 dst->dirty_level_mask &= ~(1 << info->dst.level);
1303 }
1304
1305 /* Resolve directly from src to dst. */
1306 si_do_CB_resolve(sctx, info, info->dst.resource,
1307 info->dst.level, info->dst.box.z, format);
1308 return true;
1309 }
1310
1311 resolve_to_temp:
1312 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1313 * a temporary texture and blit.
1314 */
1315 memset(&templ, 0, sizeof(templ));
1316 templ.target = PIPE_TEXTURE_2D;
1317 templ.format = info->src.resource->format;
1318 templ.width0 = info->src.resource->width0;
1319 templ.height0 = info->src.resource->height0;
1320 templ.depth0 = 1;
1321 templ.array_size = 1;
1322 templ.usage = PIPE_USAGE_DEFAULT;
1323 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1324 R600_RESOURCE_FLAG_DISABLE_DCC;
1325
1326 /* The src and dst microtile modes must be the same. */
1327 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1328 templ.bind = PIPE_BIND_SCANOUT;
1329 else
1330 templ.bind = 0;
1331
1332 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1333 if (!tmp)
1334 return false;
1335 rtmp = (struct r600_texture*)tmp;
1336
1337 assert(!rtmp->surface.is_linear);
1338 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1339
1340 /* resolve */
1341 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1342
1343 /* blit */
1344 blit = *info;
1345 blit.src.resource = tmp;
1346 blit.src.box.z = 0;
1347
1348 si_blitter_begin(ctx, SI_BLIT |
1349 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1350 util_blitter_blit(sctx->blitter, &blit);
1351 si_blitter_end(ctx);
1352
1353 pipe_resource_reference(&tmp, NULL);
1354 return true;
1355 }
1356
1357 static void si_blit(struct pipe_context *ctx,
1358 const struct pipe_blit_info *info)
1359 {
1360 struct si_context *sctx = (struct si_context*)ctx;
1361 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1362
1363 if (do_hardware_msaa_resolve(ctx, info)) {
1364 return;
1365 }
1366
1367 /* Using SDMA for copying to a linear texture in GTT is much faster.
1368 * This improves DRI PRIME performance.
1369 *
1370 * resource_copy_region can't do this yet, because dma_copy calls it
1371 * on failure (recursion).
1372 */
1373 if (rdst->surface.is_linear &&
1374 sctx->b.dma_copy &&
1375 util_can_blit_via_copy_region(info, false)) {
1376 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1377 info->dst.box.x, info->dst.box.y,
1378 info->dst.box.z,
1379 info->src.resource, info->src.level,
1380 &info->src.box);
1381 return;
1382 }
1383
1384 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1385
1386 /* The driver doesn't decompress resources automatically while
1387 * u_blitter is rendering. */
1388 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1389 info->src.level,
1390 info->src.format);
1391 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1392 info->dst.level,
1393 info->dst.format);
1394 si_decompress_subresource(ctx, info->src.resource, info->mask,
1395 info->src.level,
1396 info->src.box.z,
1397 info->src.box.z + info->src.box.depth - 1);
1398
1399 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1400 util_try_blit_via_copy_region(ctx, info))
1401 return;
1402
1403 si_blitter_begin(ctx, SI_BLIT |
1404 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1405 util_blitter_blit(sctx->blitter, info);
1406 si_blitter_end(ctx);
1407 }
1408
1409 static boolean si_generate_mipmap(struct pipe_context *ctx,
1410 struct pipe_resource *tex,
1411 enum pipe_format format,
1412 unsigned base_level, unsigned last_level,
1413 unsigned first_layer, unsigned last_layer)
1414 {
1415 struct si_context *sctx = (struct si_context*)ctx;
1416 struct r600_texture *rtex = (struct r600_texture *)tex;
1417
1418 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1419 return false;
1420
1421 /* The driver doesn't decompress resources automatically while
1422 * u_blitter is rendering. */
1423 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1424 format);
1425 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1426 base_level, first_layer, last_layer);
1427
1428 /* Clear dirty_level_mask for the levels that will be overwritten. */
1429 assert(base_level < last_level);
1430 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1431 last_level - base_level);
1432
1433 sctx->generate_mipmap_for_depth = rtex->is_depth;
1434
1435 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1436 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1437 base_level, last_level,
1438 first_layer, last_layer);
1439 si_blitter_end(ctx);
1440
1441 sctx->generate_mipmap_for_depth = false;
1442 return true;
1443 }
1444
1445 static void si_flush_resource(struct pipe_context *ctx,
1446 struct pipe_resource *res)
1447 {
1448 struct r600_texture *rtex = (struct r600_texture*)res;
1449
1450 assert(res->target != PIPE_BUFFER);
1451 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1452
1453 /* st/dri calls flush twice per frame (not a bug), this prevents double
1454 * decompression. */
1455 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1456 return;
1457
1458 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1459 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1460 0, util_max_layer(res, 0),
1461 rtex->dcc_separate_buffer != NULL);
1462 }
1463
1464 /* Always do the analysis even if DCC is disabled at the moment. */
1465 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1466 rtex->separate_dcc_dirty = false;
1467 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1468 }
1469 }
1470
1471 static void si_decompress_dcc(struct pipe_context *ctx,
1472 struct r600_texture *rtex)
1473 {
1474 if (!rtex->dcc_offset)
1475 return;
1476
1477 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1478 0, util_max_layer(&rtex->resource.b.b, 0),
1479 true);
1480 }
1481
1482 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1483 struct pipe_resource *dst,
1484 unsigned offset, unsigned size,
1485 const void *clear_value_ptr,
1486 int clear_value_size)
1487 {
1488 struct si_context *sctx = (struct si_context*)ctx;
1489 uint32_t dword_value;
1490 unsigned i;
1491
1492 assert(offset % clear_value_size == 0);
1493 assert(size % clear_value_size == 0);
1494
1495 if (clear_value_size > 4) {
1496 const uint32_t *u32 = clear_value_ptr;
1497 bool clear_dword_duplicated = true;
1498
1499 /* See if we can lower large fills to dword fills. */
1500 for (i = 1; i < clear_value_size / 4; i++)
1501 if (u32[0] != u32[i]) {
1502 clear_dword_duplicated = false;
1503 break;
1504 }
1505
1506 if (!clear_dword_duplicated) {
1507 /* Use transform feedback for 64-bit, 96-bit, and
1508 * 128-bit fills.
1509 */
1510 union pipe_color_union clear_value;
1511
1512 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1513 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1514 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1515 size, clear_value_size / 4,
1516 &clear_value);
1517 si_blitter_end(ctx);
1518 return;
1519 }
1520 }
1521
1522 /* Expand the clear value to a dword. */
1523 switch (clear_value_size) {
1524 case 1:
1525 dword_value = *(uint8_t*)clear_value_ptr;
1526 dword_value |= (dword_value << 8) |
1527 (dword_value << 16) |
1528 (dword_value << 24);
1529 break;
1530 case 2:
1531 dword_value = *(uint16_t*)clear_value_ptr;
1532 dword_value |= dword_value << 16;
1533 break;
1534 default:
1535 dword_value = *(uint32_t*)clear_value_ptr;
1536 }
1537
1538 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1539 R600_COHERENCY_SHADER);
1540 }
1541
1542 void si_init_blit_functions(struct si_context *sctx)
1543 {
1544 sctx->b.b.clear = si_clear;
1545 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1546 sctx->b.b.clear_render_target = si_clear_render_target;
1547 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1548 sctx->b.b.resource_copy_region = si_resource_copy_region;
1549 sctx->b.b.blit = si_blit;
1550 sctx->b.b.flush_resource = si_flush_resource;
1551 sctx->b.b.generate_mipmap = si_generate_mipmap;
1552 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1553 sctx->b.decompress_dcc = si_decompress_dcc;
1554 }