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radeonsi: update dirty_level_mask only when flushing or unbinding framebuffer
[mesa.git] / src / gallium / drivers / radeonsi / si_blit.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_surface.h"
28
29 enum si_blitter_op /* bitmask */
30 {
31 SI_SAVE_TEXTURES = 1,
32 SI_SAVE_FRAMEBUFFER = 2,
33 SI_SAVE_FRAGMENT_STATE = 4,
34 SI_DISABLE_RENDER_COND = 8,
35
36 SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
37
38 SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
39
40 SI_COPY = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
41 SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND,
42
43 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES |
44 SI_SAVE_FRAGMENT_STATE,
45
46 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE |
47 SI_DISABLE_RENDER_COND,
48
49 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE
50 };
51
52 static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
53 {
54 struct si_context *sctx = (struct si_context *)ctx;
55
56 util_blitter_save_vertex_buffer_slot(sctx->blitter, sctx->vertex_buffer);
57 util_blitter_save_vertex_elements(sctx->blitter, sctx->vertex_elements);
58 util_blitter_save_vertex_shader(sctx->blitter, sctx->vs_shader.cso);
59 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
60 util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
61 util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
62 util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
63 (struct pipe_stream_output_target**)sctx->b.streamout.targets);
64 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
65
66 if (op & SI_SAVE_FRAGMENT_STATE) {
67 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
68 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa);
69 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
70 util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
71 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
72 util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
73 util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
74 }
75
76 if (op & SI_SAVE_FRAMEBUFFER)
77 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state);
78
79 if (op & SI_SAVE_TEXTURES) {
80 util_blitter_save_fragment_sampler_states(
81 sctx->blitter, 2,
82 (void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
83
84 util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
85 sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
86 }
87
88 if (op & SI_DISABLE_RENDER_COND)
89 sctx->b.render_cond_force_off = true;
90 }
91
92 static void si_blitter_end(struct pipe_context *ctx)
93 {
94 struct si_context *sctx = (struct si_context *)ctx;
95
96 sctx->b.render_cond_force_off = false;
97 }
98
99 static unsigned u_max_sample(struct pipe_resource *r)
100 {
101 return r->nr_samples ? r->nr_samples - 1 : 0;
102 }
103
104 static unsigned
105 si_blit_dbcb_copy(struct si_context *sctx,
106 struct r600_texture *src,
107 struct r600_texture *dst,
108 unsigned planes, unsigned level_mask,
109 unsigned first_layer, unsigned last_layer,
110 unsigned first_sample, unsigned last_sample)
111 {
112 struct pipe_surface surf_tmpl = {{0}};
113 unsigned layer, sample, checked_last_layer, max_layer;
114 unsigned fully_copied_levels = 0;
115
116 if (planes & PIPE_MASK_Z)
117 sctx->dbcb_depth_copy_enabled = true;
118 if (planes & PIPE_MASK_S)
119 sctx->dbcb_stencil_copy_enabled = true;
120 si_mark_atom_dirty(sctx, &sctx->db_render_state);
121
122 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
123
124 sctx->decompression_enabled = true;
125
126 while (level_mask) {
127 unsigned level = u_bit_scan(&level_mask);
128
129 /* The smaller the mipmap level, the less layers there are
130 * as far as 3D textures are concerned. */
131 max_layer = util_max_layer(&src->resource.b.b, level);
132 checked_last_layer = MIN2(last_layer, max_layer);
133
134 surf_tmpl.u.tex.level = level;
135
136 for (layer = first_layer; layer <= checked_last_layer; layer++) {
137 struct pipe_surface *zsurf, *cbsurf;
138
139 surf_tmpl.format = src->resource.b.b.format;
140 surf_tmpl.u.tex.first_layer = layer;
141 surf_tmpl.u.tex.last_layer = layer;
142
143 zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
144
145 surf_tmpl.format = dst->resource.b.b.format;
146 cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
147
148 for (sample = first_sample; sample <= last_sample; sample++) {
149 if (sample != sctx->dbcb_copy_sample) {
150 sctx->dbcb_copy_sample = sample;
151 si_mark_atom_dirty(sctx, &sctx->db_render_state);
152 }
153
154 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
155 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
156 sctx->custom_dsa_flush, 1.0f);
157 si_blitter_end(&sctx->b.b);
158 }
159
160 pipe_surface_reference(&zsurf, NULL);
161 pipe_surface_reference(&cbsurf, NULL);
162 }
163
164 if (first_layer == 0 && last_layer >= max_layer &&
165 first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
166 fully_copied_levels |= 1u << level;
167 }
168
169 sctx->decompression_enabled = false;
170 sctx->dbcb_depth_copy_enabled = false;
171 sctx->dbcb_stencil_copy_enabled = false;
172 si_mark_atom_dirty(sctx, &sctx->db_render_state);
173
174 return fully_copied_levels;
175 }
176
177 static void si_blit_decompress_depth(struct pipe_context *ctx,
178 struct r600_texture *texture,
179 struct r600_texture *staging,
180 unsigned first_level, unsigned last_level,
181 unsigned first_layer, unsigned last_layer,
182 unsigned first_sample, unsigned last_sample)
183 {
184 const struct util_format_description *desc;
185 unsigned planes = 0;
186
187 assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
188
189 desc = util_format_description(staging->resource.b.b.format);
190
191 if (util_format_has_depth(desc))
192 planes |= PIPE_MASK_Z;
193 if (util_format_has_stencil(desc))
194 planes |= PIPE_MASK_S;
195
196 si_blit_dbcb_copy(
197 (struct si_context *)ctx, texture, staging, planes,
198 u_bit_consecutive(first_level, last_level - first_level + 1),
199 first_layer, last_layer, first_sample, last_sample);
200 }
201
202 /* Helper function for si_blit_decompress_zs_in_place.
203 */
204 static void
205 si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
206 struct r600_texture *texture,
207 unsigned planes, unsigned level_mask,
208 unsigned first_layer, unsigned last_layer)
209 {
210 struct pipe_surface *zsurf, surf_tmpl = {{0}};
211 unsigned layer, max_layer, checked_last_layer;
212 unsigned fully_decompressed_mask = 0;
213
214 if (!level_mask)
215 return;
216
217 if (planes & PIPE_MASK_S)
218 sctx->db_flush_stencil_inplace = true;
219 if (planes & PIPE_MASK_Z)
220 sctx->db_flush_depth_inplace = true;
221 si_mark_atom_dirty(sctx, &sctx->db_render_state);
222
223 surf_tmpl.format = texture->resource.b.b.format;
224
225 sctx->decompression_enabled = true;
226
227 while (level_mask) {
228 unsigned level = u_bit_scan(&level_mask);
229
230 surf_tmpl.u.tex.level = level;
231
232 /* The smaller the mipmap level, the less layers there are
233 * as far as 3D textures are concerned. */
234 max_layer = util_max_layer(&texture->resource.b.b, level);
235 checked_last_layer = MIN2(last_layer, max_layer);
236
237 for (layer = first_layer; layer <= checked_last_layer; layer++) {
238 surf_tmpl.u.tex.first_layer = layer;
239 surf_tmpl.u.tex.last_layer = layer;
240
241 zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
242
243 si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
244 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
245 sctx->custom_dsa_flush,
246 1.0f);
247 si_blitter_end(&sctx->b.b);
248
249 pipe_surface_reference(&zsurf, NULL);
250 }
251
252 /* The texture will always be dirty if some layers aren't flushed.
253 * I don't think this case occurs often though. */
254 if (first_layer == 0 && last_layer >= max_layer) {
255 fully_decompressed_mask |= 1u << level;
256 }
257 }
258
259 if (planes & PIPE_MASK_Z)
260 texture->dirty_level_mask &= ~fully_decompressed_mask;
261 if (planes & PIPE_MASK_S)
262 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
263
264 sctx->decompression_enabled = false;
265 sctx->db_flush_depth_inplace = false;
266 sctx->db_flush_stencil_inplace = false;
267 si_mark_atom_dirty(sctx, &sctx->db_render_state);
268 }
269
270 /* Helper function of si_flush_depth_texture: decompress the given levels
271 * of Z and/or S planes in place.
272 */
273 static void
274 si_blit_decompress_zs_in_place(struct si_context *sctx,
275 struct r600_texture *texture,
276 unsigned levels_z, unsigned levels_s,
277 unsigned first_layer, unsigned last_layer)
278 {
279 unsigned both = levels_z & levels_s;
280
281 /* First, do combined Z & S decompresses for levels that need it. */
282 if (both) {
283 si_blit_decompress_zs_planes_in_place(
284 sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
285 both,
286 first_layer, last_layer);
287 levels_z &= ~both;
288 levels_s &= ~both;
289 }
290
291 /* Now do separate Z and S decompresses. */
292 if (levels_z) {
293 si_blit_decompress_zs_planes_in_place(
294 sctx, texture, PIPE_MASK_Z,
295 levels_z,
296 first_layer, last_layer);
297 }
298
299 if (levels_s) {
300 si_blit_decompress_zs_planes_in_place(
301 sctx, texture, PIPE_MASK_S,
302 levels_s,
303 first_layer, last_layer);
304 }
305 }
306
307 static void
308 si_decompress_depth(struct si_context *sctx,
309 struct r600_texture *tex,
310 unsigned required_planes,
311 unsigned first_level, unsigned last_level,
312 unsigned first_layer, unsigned last_layer)
313 {
314 unsigned inplace_planes = 0;
315 unsigned copy_planes = 0;
316 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1);
317 unsigned levels_z = 0;
318 unsigned levels_s = 0;
319
320 if (required_planes & PIPE_MASK_Z) {
321 levels_z = level_mask & tex->dirty_level_mask;
322
323 if (levels_z) {
324 if (r600_can_sample_zs(tex, false))
325 inplace_planes |= PIPE_MASK_Z;
326 else
327 copy_planes |= PIPE_MASK_Z;
328 }
329 }
330 if (required_planes & PIPE_MASK_S) {
331 levels_s = level_mask & tex->stencil_dirty_level_mask;
332
333 if (levels_s) {
334 if (r600_can_sample_zs(tex, true))
335 inplace_planes |= PIPE_MASK_S;
336 else
337 copy_planes |= PIPE_MASK_S;
338 }
339 }
340
341 /* We may have to allocate the flushed texture here when called from
342 * si_decompress_subresource.
343 */
344 if (copy_planes &&
345 (tex->flushed_depth_texture ||
346 r600_init_flushed_depth_texture(&sctx->b.b, &tex->resource.b.b, NULL))) {
347 struct r600_texture *dst = tex->flushed_depth_texture;
348 unsigned fully_copied_levels;
349 unsigned levels = 0;
350
351 assert(tex->flushed_depth_texture);
352
353 if (util_format_is_depth_and_stencil(dst->resource.b.b.format))
354 copy_planes = PIPE_MASK_Z | PIPE_MASK_S;
355
356 if (copy_planes & PIPE_MASK_Z) {
357 levels |= levels_z;
358 levels_z = 0;
359 }
360 if (copy_planes & PIPE_MASK_S) {
361 levels |= levels_s;
362 levels_s = 0;
363 }
364
365 fully_copied_levels = si_blit_dbcb_copy(
366 sctx, tex, dst, copy_planes, levels,
367 first_layer, last_layer,
368 0, u_max_sample(&tex->resource.b.b));
369
370 if (copy_planes & PIPE_MASK_Z)
371 tex->dirty_level_mask &= ~fully_copied_levels;
372 if (copy_planes & PIPE_MASK_S)
373 tex->stencil_dirty_level_mask &= ~fully_copied_levels;
374 }
375
376 if (inplace_planes) {
377 if (!tex->tc_compatible_htile) {
378 si_blit_decompress_zs_in_place(
379 sctx, tex,
380 levels_z, levels_s,
381 first_layer, last_layer);
382 }
383
384 /* Only in-place decompression needs to flush DB caches, or
385 * when we don't decompress but TC-compatible planes are dirty.
386 */
387 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
388 SI_CONTEXT_INV_GLOBAL_L2 |
389 SI_CONTEXT_INV_VMEM_L1;
390
391 /* If we flush DB caches for TC-compatible depth, the dirty
392 * state becomes 0 for the whole mipmap tree and all planes.
393 * (there is nothing else to flush)
394 */
395 if (tex->tc_compatible_htile) {
396 if (r600_can_sample_zs(tex, false))
397 tex->dirty_level_mask = 0;
398 if (r600_can_sample_zs(tex, true))
399 tex->stencil_dirty_level_mask = 0;
400 }
401 }
402 /* set_framebuffer_state takes care of coherency for single-sample.
403 * The DB->CB copy uses CB for the final writes.
404 */
405 if (copy_planes && tex->resource.b.b.nr_samples > 1) {
406 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
407 SI_CONTEXT_INV_GLOBAL_L2 |
408 SI_CONTEXT_FLUSH_AND_INV_CB;
409 }
410 }
411
412 static void
413 si_decompress_sampler_depth_textures(struct si_context *sctx,
414 struct si_textures_info *textures)
415 {
416 unsigned i;
417 unsigned mask = textures->needs_depth_decompress_mask;
418
419 while (mask) {
420 struct pipe_sampler_view *view;
421 struct si_sampler_view *sview;
422 struct r600_texture *tex;
423
424 i = u_bit_scan(&mask);
425
426 view = textures->views.views[i];
427 assert(view);
428 sview = (struct si_sampler_view*)view;
429
430 tex = (struct r600_texture *)view->texture;
431 assert(tex->db_compatible);
432
433 si_decompress_depth(sctx, tex,
434 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
435 view->u.tex.first_level, view->u.tex.last_level,
436 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
437 }
438 }
439
440 static void si_blit_decompress_color(struct pipe_context *ctx,
441 struct r600_texture *rtex,
442 unsigned first_level, unsigned last_level,
443 unsigned first_layer, unsigned last_layer,
444 bool need_dcc_decompress)
445 {
446 struct si_context *sctx = (struct si_context *)ctx;
447 void* custom_blend;
448 unsigned layer, checked_last_layer, max_layer;
449 unsigned level_mask =
450 u_bit_consecutive(first_level, last_level - first_level + 1);
451
452 if (!need_dcc_decompress)
453 level_mask &= rtex->dirty_level_mask;
454 if (!level_mask)
455 return;
456
457 if (rtex->dcc_offset && need_dcc_decompress) {
458 custom_blend = sctx->custom_blend_dcc_decompress;
459
460 /* disable levels without DCC */
461 for (int i = first_level; i <= last_level; i++) {
462 if (!vi_dcc_enabled(rtex, i))
463 level_mask &= ~(1 << i);
464 }
465 } else if (rtex->fmask.size) {
466 custom_blend = sctx->custom_blend_fmask_decompress;
467 } else {
468 custom_blend = sctx->custom_blend_eliminate_fastclear;
469 }
470
471 sctx->decompression_enabled = true;
472
473 while (level_mask) {
474 unsigned level = u_bit_scan(&level_mask);
475
476 /* The smaller the mipmap level, the less layers there are
477 * as far as 3D textures are concerned. */
478 max_layer = util_max_layer(&rtex->resource.b.b, level);
479 checked_last_layer = MIN2(last_layer, max_layer);
480
481 for (layer = first_layer; layer <= checked_last_layer; layer++) {
482 struct pipe_surface *cbsurf, surf_tmpl;
483
484 surf_tmpl.format = rtex->resource.b.b.format;
485 surf_tmpl.u.tex.level = level;
486 surf_tmpl.u.tex.first_layer = layer;
487 surf_tmpl.u.tex.last_layer = layer;
488 cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
489
490 /* Required before and after FMASK and DCC_DECOMPRESS. */
491 if (custom_blend == sctx->custom_blend_fmask_decompress ||
492 custom_blend == sctx->custom_blend_dcc_decompress)
493 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
494
495 si_blitter_begin(ctx, SI_DECOMPRESS);
496 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
497 si_blitter_end(ctx);
498
499 if (custom_blend == sctx->custom_blend_fmask_decompress ||
500 custom_blend == sctx->custom_blend_dcc_decompress)
501 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
502
503 pipe_surface_reference(&cbsurf, NULL);
504 }
505
506 /* The texture will always be dirty if some layers aren't flushed.
507 * I don't think this case occurs often though. */
508 if (first_layer == 0 && last_layer >= max_layer) {
509 rtex->dirty_level_mask &= ~(1 << level);
510 }
511 }
512
513 sctx->decompression_enabled = false;
514
515 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
516 SI_CONTEXT_INV_GLOBAL_L2 |
517 SI_CONTEXT_INV_VMEM_L1;
518 }
519
520 static void
521 si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
522 unsigned first_level, unsigned last_level)
523 {
524 /* CMASK or DCC can be discarded and we can still end up here. */
525 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
526 return;
527
528 si_blit_decompress_color(&sctx->b.b, tex, first_level, last_level, 0,
529 util_max_layer(&tex->resource.b.b, first_level),
530 false);
531 }
532
533 static void
534 si_decompress_sampler_color_textures(struct si_context *sctx,
535 struct si_textures_info *textures)
536 {
537 unsigned i;
538 unsigned mask = textures->needs_color_decompress_mask;
539
540 while (mask) {
541 struct pipe_sampler_view *view;
542 struct r600_texture *tex;
543
544 i = u_bit_scan(&mask);
545
546 view = textures->views.views[i];
547 assert(view);
548
549 tex = (struct r600_texture *)view->texture;
550
551 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
552 view->u.tex.last_level);
553 }
554 }
555
556 static void
557 si_decompress_image_color_textures(struct si_context *sctx,
558 struct si_images_info *images)
559 {
560 unsigned i;
561 unsigned mask = images->needs_color_decompress_mask;
562
563 while (mask) {
564 const struct pipe_image_view *view;
565 struct r600_texture *tex;
566
567 i = u_bit_scan(&mask);
568
569 view = &images->views[i];
570 assert(view->resource->target != PIPE_BUFFER);
571
572 tex = (struct r600_texture *)view->resource;
573
574 si_decompress_color_texture(sctx, tex, view->u.tex.level,
575 view->u.tex.level);
576 }
577 }
578
579 static void si_check_render_feedback_texture(struct si_context *sctx,
580 struct r600_texture *tex,
581 unsigned first_level,
582 unsigned last_level,
583 unsigned first_layer,
584 unsigned last_layer)
585 {
586 bool render_feedback = false;
587
588 if (!tex->dcc_offset)
589 return;
590
591 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
592 struct r600_surface * surf;
593
594 if (!sctx->framebuffer.state.cbufs[j])
595 continue;
596
597 surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
598
599 if (tex == (struct r600_texture *)surf->base.texture &&
600 surf->base.u.tex.level >= first_level &&
601 surf->base.u.tex.level <= last_level &&
602 surf->base.u.tex.first_layer <= last_layer &&
603 surf->base.u.tex.last_layer >= first_layer) {
604 render_feedback = true;
605 break;
606 }
607 }
608
609 if (render_feedback)
610 r600_texture_disable_dcc(&sctx->b, tex);
611 }
612
613 static void si_check_render_feedback_textures(struct si_context *sctx,
614 struct si_textures_info *textures)
615 {
616 uint32_t mask = textures->views.enabled_mask;
617
618 while (mask) {
619 const struct pipe_sampler_view *view;
620 struct r600_texture *tex;
621
622 unsigned i = u_bit_scan(&mask);
623
624 view = textures->views.views[i];
625 if(view->texture->target == PIPE_BUFFER)
626 continue;
627
628 tex = (struct r600_texture *)view->texture;
629
630 si_check_render_feedback_texture(sctx, tex,
631 view->u.tex.first_level,
632 view->u.tex.last_level,
633 view->u.tex.first_layer,
634 view->u.tex.last_layer);
635 }
636 }
637
638 static void si_check_render_feedback_images(struct si_context *sctx,
639 struct si_images_info *images)
640 {
641 uint32_t mask = images->enabled_mask;
642
643 while (mask) {
644 const struct pipe_image_view *view;
645 struct r600_texture *tex;
646
647 unsigned i = u_bit_scan(&mask);
648
649 view = &images->views[i];
650 if (view->resource->target == PIPE_BUFFER)
651 continue;
652
653 tex = (struct r600_texture *)view->resource;
654
655 si_check_render_feedback_texture(sctx, tex,
656 view->u.tex.level,
657 view->u.tex.level,
658 view->u.tex.first_layer,
659 view->u.tex.last_layer);
660 }
661 }
662
663 static void si_check_render_feedback_resident_textures(struct si_context *sctx)
664 {
665 util_dynarray_foreach(&sctx->resident_tex_handles,
666 struct si_texture_handle *, tex_handle) {
667 struct pipe_sampler_view *view;
668 struct r600_texture *tex;
669
670 view = (*tex_handle)->view;
671 if (view->texture->target == PIPE_BUFFER)
672 continue;
673
674 tex = (struct r600_texture *)view->texture;
675
676 si_check_render_feedback_texture(sctx, tex,
677 view->u.tex.first_level,
678 view->u.tex.last_level,
679 view->u.tex.first_layer,
680 view->u.tex.last_layer);
681 }
682 }
683
684 static void si_check_render_feedback_resident_images(struct si_context *sctx)
685 {
686 util_dynarray_foreach(&sctx->resident_img_handles,
687 struct si_image_handle *, img_handle) {
688 struct pipe_image_view *view;
689 struct r600_texture *tex;
690
691 view = &(*img_handle)->view;
692 if (view->resource->target == PIPE_BUFFER)
693 continue;
694
695 tex = (struct r600_texture *)view->resource;
696
697 si_check_render_feedback_texture(sctx, tex,
698 view->u.tex.level,
699 view->u.tex.level,
700 view->u.tex.first_layer,
701 view->u.tex.last_layer);
702 }
703 }
704
705 static void si_check_render_feedback(struct si_context *sctx)
706 {
707
708 if (!sctx->need_check_render_feedback)
709 return;
710
711 for (int i = 0; i < SI_NUM_SHADERS; ++i) {
712 si_check_render_feedback_images(sctx, &sctx->images[i]);
713 si_check_render_feedback_textures(sctx, &sctx->samplers[i]);
714 }
715
716 si_check_render_feedback_resident_images(sctx);
717 si_check_render_feedback_resident_textures(sctx);
718
719 sctx->need_check_render_feedback = false;
720 }
721
722 static void si_decompress_resident_textures(struct si_context *sctx)
723 {
724 util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
725 struct si_texture_handle *, tex_handle) {
726 struct pipe_sampler_view *view = (*tex_handle)->view;
727 struct r600_texture *tex = (struct r600_texture *)view->texture;
728
729 si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
730 view->u.tex.last_level);
731 }
732
733 util_dynarray_foreach(&sctx->resident_tex_needs_depth_decompress,
734 struct si_texture_handle *, tex_handle) {
735 struct pipe_sampler_view *view = (*tex_handle)->view;
736 struct si_sampler_view *sview = (struct si_sampler_view *)view;
737 struct r600_texture *tex = (struct r600_texture *)view->texture;
738
739 si_decompress_depth(sctx, tex,
740 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
741 view->u.tex.first_level, view->u.tex.last_level,
742 0, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
743 }
744 }
745
746 static void si_decompress_resident_images(struct si_context *sctx)
747 {
748 util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
749 struct si_image_handle *, img_handle) {
750 struct pipe_image_view *view = &(*img_handle)->view;
751 struct r600_texture *tex = (struct r600_texture *)view->resource;
752
753 si_decompress_color_texture(sctx, tex, view->u.tex.level,
754 view->u.tex.level);
755 }
756 }
757
758 static void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
759 {
760 unsigned compressed_colortex_counter, mask;
761
762 if (sctx->blitter->running)
763 return;
764
765 /* Update the compressed_colortex_mask if necessary. */
766 compressed_colortex_counter = p_atomic_read(&sctx->screen->b.compressed_colortex_counter);
767 if (compressed_colortex_counter != sctx->b.last_compressed_colortex_counter) {
768 sctx->b.last_compressed_colortex_counter = compressed_colortex_counter;
769 si_update_needs_color_decompress_masks(sctx);
770 }
771
772 /* Decompress color & depth textures if needed. */
773 mask = sctx->shader_needs_decompress_mask & shader_mask;
774 while (mask) {
775 unsigned i = u_bit_scan(&mask);
776
777 if (sctx->samplers[i].needs_depth_decompress_mask) {
778 si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]);
779 }
780 if (sctx->samplers[i].needs_color_decompress_mask) {
781 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]);
782 }
783 if (sctx->images[i].needs_color_decompress_mask) {
784 si_decompress_image_color_textures(sctx, &sctx->images[i]);
785 }
786 }
787
788 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) {
789 if (sctx->uses_bindless_samplers)
790 si_decompress_resident_textures(sctx);
791 if (sctx->uses_bindless_images)
792 si_decompress_resident_images(sctx);
793 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) {
794 if (sctx->cs_shader_state.program->uses_bindless_samplers)
795 si_decompress_resident_textures(sctx);
796 if (sctx->cs_shader_state.program->uses_bindless_images)
797 si_decompress_resident_images(sctx);
798 }
799
800 si_check_render_feedback(sctx);
801 }
802
803 void si_decompress_graphics_textures(struct si_context *sctx)
804 {
805 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
806 }
807
808 void si_decompress_compute_textures(struct si_context *sctx)
809 {
810 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
811 }
812
813 static void si_clear(struct pipe_context *ctx, unsigned buffers,
814 const union pipe_color_union *color,
815 double depth, unsigned stencil)
816 {
817 struct si_context *sctx = (struct si_context *)ctx;
818 struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
819 struct pipe_surface *zsbuf = fb->zsbuf;
820 struct r600_texture *zstex =
821 zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
822
823 if (buffers & PIPE_CLEAR_COLOR) {
824 evergreen_do_fast_color_clear(&sctx->b, fb,
825 &sctx->framebuffer.atom, &buffers,
826 &sctx->framebuffer.dirty_cbufs,
827 color);
828 if (!buffers)
829 return; /* all buffers have been fast cleared */
830 }
831
832 if (buffers & PIPE_CLEAR_COLOR) {
833 int i;
834
835 /* These buffers cannot use fast clear, make sure to disable expansion. */
836 for (i = 0; i < fb->nr_cbufs; i++) {
837 struct r600_texture *tex;
838
839 /* If not clearing this buffer, skip. */
840 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
841 continue;
842
843 if (!fb->cbufs[i])
844 continue;
845
846 tex = (struct r600_texture *)fb->cbufs[i]->texture;
847 if (tex->fmask.size == 0)
848 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
849 }
850 }
851
852 if (zstex && zstex->htile_offset &&
853 zsbuf->u.tex.level == 0 &&
854 zsbuf->u.tex.first_layer == 0 &&
855 zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
856 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
857 if (buffers & PIPE_CLEAR_DEPTH &&
858 (!zstex->tc_compatible_htile ||
859 depth == 0 || depth == 1)) {
860 /* Need to disable EXPCLEAR temporarily if clearing
861 * to a new value. */
862 if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
863 sctx->db_depth_disable_expclear = true;
864 }
865
866 zstex->depth_clear_value = depth;
867 sctx->framebuffer.dirty_zsbuf = true;
868 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
869 sctx->db_depth_clear = true;
870 si_mark_atom_dirty(sctx, &sctx->db_render_state);
871 }
872
873 /* TC-compatible HTILE only supports stencil clears to 0. */
874 if (buffers & PIPE_CLEAR_STENCIL &&
875 (!zstex->tc_compatible_htile || stencil == 0)) {
876 stencil &= 0xff;
877
878 /* Need to disable EXPCLEAR temporarily if clearing
879 * to a new value. */
880 if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
881 sctx->db_stencil_disable_expclear = true;
882 }
883
884 zstex->stencil_clear_value = stencil;
885 sctx->framebuffer.dirty_zsbuf = true;
886 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
887 sctx->db_stencil_clear = true;
888 si_mark_atom_dirty(sctx, &sctx->db_render_state);
889 }
890 }
891
892 si_blitter_begin(ctx, SI_CLEAR);
893 util_blitter_clear(sctx->blitter, fb->width, fb->height,
894 util_framebuffer_get_num_layers(fb),
895 buffers, color, depth, stencil);
896 si_blitter_end(ctx);
897
898 if (sctx->db_depth_clear) {
899 sctx->db_depth_clear = false;
900 sctx->db_depth_disable_expclear = false;
901 zstex->depth_cleared = true;
902 si_mark_atom_dirty(sctx, &sctx->db_render_state);
903 }
904
905 if (sctx->db_stencil_clear) {
906 sctx->db_stencil_clear = false;
907 sctx->db_stencil_disable_expclear = false;
908 zstex->stencil_cleared = true;
909 si_mark_atom_dirty(sctx, &sctx->db_render_state);
910 }
911 }
912
913 static void si_clear_render_target(struct pipe_context *ctx,
914 struct pipe_surface *dst,
915 const union pipe_color_union *color,
916 unsigned dstx, unsigned dsty,
917 unsigned width, unsigned height,
918 bool render_condition_enabled)
919 {
920 struct si_context *sctx = (struct si_context *)ctx;
921
922 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
923 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
924 util_blitter_clear_render_target(sctx->blitter, dst, color,
925 dstx, dsty, width, height);
926 si_blitter_end(ctx);
927 }
928
929 static void si_clear_depth_stencil(struct pipe_context *ctx,
930 struct pipe_surface *dst,
931 unsigned clear_flags,
932 double depth,
933 unsigned stencil,
934 unsigned dstx, unsigned dsty,
935 unsigned width, unsigned height,
936 bool render_condition_enabled)
937 {
938 struct si_context *sctx = (struct si_context *)ctx;
939
940 si_blitter_begin(ctx, SI_CLEAR_SURFACE |
941 (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
942 util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
943 dstx, dsty, width, height);
944 si_blitter_end(ctx);
945 }
946
947 /* Helper for decompressing a portion of a color or depth resource before
948 * blitting if any decompression is needed.
949 * The driver doesn't decompress resources automatically while u_blitter is
950 * rendering. */
951 static void si_decompress_subresource(struct pipe_context *ctx,
952 struct pipe_resource *tex,
953 unsigned planes, unsigned level,
954 unsigned first_layer, unsigned last_layer)
955 {
956 struct si_context *sctx = (struct si_context *)ctx;
957 struct r600_texture *rtex = (struct r600_texture*)tex;
958
959 if (rtex->db_compatible) {
960 planes &= PIPE_MASK_Z | PIPE_MASK_S;
961
962 if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
963 planes &= ~PIPE_MASK_S;
964
965 /* If we've rendered into the framebuffer and it's a blitting
966 * source, make sure the decompression pass is invoked
967 * by dirtying the framebuffer.
968 */
969 if (sctx->framebuffer.state.zsbuf &&
970 sctx->framebuffer.state.zsbuf->u.tex.level == level &&
971 sctx->framebuffer.state.zsbuf->texture == tex)
972 si_update_fb_dirtiness_after_rendering(sctx);
973
974 si_decompress_depth(sctx, rtex, planes,
975 level, level,
976 first_layer, last_layer);
977 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) {
978 /* If we've rendered into the framebuffer and it's a blitting
979 * source, make sure the decompression pass is invoked
980 * by dirtying the framebuffer.
981 */
982 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
983 if (sctx->framebuffer.state.cbufs[i] &&
984 sctx->framebuffer.state.cbufs[i]->u.tex.level == level &&
985 sctx->framebuffer.state.cbufs[i]->texture == tex) {
986 si_update_fb_dirtiness_after_rendering(sctx);
987 break;
988 }
989 }
990
991 si_blit_decompress_color(ctx, rtex, level, level,
992 first_layer, last_layer, false);
993 }
994 }
995
996 struct texture_orig_info {
997 unsigned format;
998 unsigned width0;
999 unsigned height0;
1000 unsigned npix_x;
1001 unsigned npix_y;
1002 unsigned npix0_x;
1003 unsigned npix0_y;
1004 };
1005
1006 void si_resource_copy_region(struct pipe_context *ctx,
1007 struct pipe_resource *dst,
1008 unsigned dst_level,
1009 unsigned dstx, unsigned dsty, unsigned dstz,
1010 struct pipe_resource *src,
1011 unsigned src_level,
1012 const struct pipe_box *src_box)
1013 {
1014 struct si_context *sctx = (struct si_context *)ctx;
1015 struct r600_texture *rsrc = (struct r600_texture*)src;
1016 struct pipe_surface *dst_view, dst_templ;
1017 struct pipe_sampler_view src_templ, *src_view;
1018 unsigned dst_width, dst_height, src_width0, src_height0;
1019 unsigned dst_width0, dst_height0, src_force_level = 0;
1020 struct pipe_box sbox, dstbox;
1021
1022 /* Handle buffers first. */
1023 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
1024 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, 0);
1025 return;
1026 }
1027
1028 assert(u_max_sample(dst) == u_max_sample(src));
1029
1030 /* The driver doesn't decompress resources automatically while
1031 * u_blitter is rendering. */
1032 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
1033 src_box->z, src_box->z + src_box->depth - 1);
1034
1035 dst_width = u_minify(dst->width0, dst_level);
1036 dst_height = u_minify(dst->height0, dst_level);
1037 dst_width0 = dst->width0;
1038 dst_height0 = dst->height0;
1039 src_width0 = src->width0;
1040 src_height0 = src->height0;
1041
1042 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
1043 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level);
1044
1045 if (util_format_is_compressed(src->format) ||
1046 util_format_is_compressed(dst->format)) {
1047 unsigned blocksize = rsrc->surface.bpe;
1048
1049 if (blocksize == 8)
1050 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
1051 else
1052 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
1053 dst_templ.format = src_templ.format;
1054
1055 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1056 dst_height = util_format_get_nblocksy(dst->format, dst_height);
1057 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1058 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0);
1059 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1060 src_height0 = util_format_get_nblocksy(src->format, src_height0);
1061
1062 dstx = util_format_get_nblocksx(dst->format, dstx);
1063 dsty = util_format_get_nblocksy(dst->format, dsty);
1064
1065 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1066 sbox.y = util_format_get_nblocksy(src->format, src_box->y);
1067 sbox.z = src_box->z;
1068 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1069 sbox.height = util_format_get_nblocksy(src->format, src_box->height);
1070 sbox.depth = src_box->depth;
1071 src_box = &sbox;
1072
1073 src_force_level = src_level;
1074 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
1075 if (util_format_is_subsampled_422(src->format)) {
1076 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1077 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
1078
1079 dst_width = util_format_get_nblocksx(dst->format, dst_width);
1080 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0);
1081 src_width0 = util_format_get_nblocksx(src->format, src_width0);
1082
1083 dstx = util_format_get_nblocksx(dst->format, dstx);
1084
1085 sbox = *src_box;
1086 sbox.x = util_format_get_nblocksx(src->format, src_box->x);
1087 sbox.width = util_format_get_nblocksx(src->format, src_box->width);
1088 src_box = &sbox;
1089 } else {
1090 unsigned blocksize = rsrc->surface.bpe;
1091
1092 switch (blocksize) {
1093 case 1:
1094 dst_templ.format = PIPE_FORMAT_R8_UNORM;
1095 src_templ.format = PIPE_FORMAT_R8_UNORM;
1096 break;
1097 case 2:
1098 dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
1099 src_templ.format = PIPE_FORMAT_R8G8_UNORM;
1100 break;
1101 case 4:
1102 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1103 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
1104 break;
1105 case 8:
1106 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1107 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
1108 break;
1109 case 16:
1110 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1111 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
1112 break;
1113 default:
1114 fprintf(stderr, "Unhandled format %s with blocksize %u\n",
1115 util_format_short_name(src->format), blocksize);
1116 assert(0);
1117 }
1118 }
1119 }
1120
1121 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1122 * equivalent instead, which doesn't force DCC decompression.
1123 * Note that some chips avoid this issue by using SDMA.
1124 */
1125 if (util_format_is_snorm8(dst_templ.format)) {
1126 switch (dst_templ.format) {
1127 case PIPE_FORMAT_R8_SNORM:
1128 dst_templ.format = src_templ.format = PIPE_FORMAT_R8_SINT;
1129 break;
1130 case PIPE_FORMAT_R8G8_SNORM:
1131 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8_SINT;
1132 break;
1133 case PIPE_FORMAT_R8G8B8X8_SNORM:
1134 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8X8_SINT;
1135 break;
1136 case PIPE_FORMAT_R8G8B8A8_SNORM:
1137 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1138 case PIPE_FORMAT_A8B8G8R8_SNORM:
1139 case PIPE_FORMAT_X8B8G8R8_SNORM:
1140 dst_templ.format = src_templ.format = PIPE_FORMAT_R8G8B8A8_SINT;
1141 break;
1142 case PIPE_FORMAT_A8_SNORM:
1143 dst_templ.format = src_templ.format = PIPE_FORMAT_A8_SINT;
1144 break;
1145 case PIPE_FORMAT_L8_SNORM:
1146 dst_templ.format = src_templ.format = PIPE_FORMAT_L8_SINT;
1147 break;
1148 case PIPE_FORMAT_L8A8_SNORM:
1149 dst_templ.format = src_templ.format = PIPE_FORMAT_L8A8_SINT;
1150 break;
1151 case PIPE_FORMAT_I8_SNORM:
1152 dst_templ.format = src_templ.format = PIPE_FORMAT_I8_SINT;
1153 break;
1154 default:; /* fall through */
1155 }
1156 }
1157
1158 vi_disable_dcc_if_incompatible_format(&sctx->b, dst, dst_level,
1159 dst_templ.format);
1160 vi_disable_dcc_if_incompatible_format(&sctx->b, src, src_level,
1161 src_templ.format);
1162
1163 /* Initialize the surface. */
1164 dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
1165 dst_width0, dst_height0,
1166 dst_width, dst_height);
1167
1168 /* Initialize the sampler view. */
1169 src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
1170 src_width0, src_height0,
1171 src_force_level);
1172
1173 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
1174 abs(src_box->depth), &dstbox);
1175
1176 /* Copy. */
1177 si_blitter_begin(ctx, SI_COPY);
1178 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
1179 src_view, src_box, src_width0, src_height0,
1180 PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
1181 false);
1182 si_blitter_end(ctx);
1183
1184 pipe_surface_reference(&dst_view, NULL);
1185 pipe_sampler_view_reference(&src_view, NULL);
1186 }
1187
1188 static void si_do_CB_resolve(struct si_context *sctx,
1189 const struct pipe_blit_info *info,
1190 struct pipe_resource *dst,
1191 unsigned dst_level, unsigned dst_z,
1192 enum pipe_format format)
1193 {
1194 /* Required before and after CB_RESOLVE. */
1195 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
1196
1197 si_blitter_begin(&sctx->b.b, SI_COLOR_RESOLVE |
1198 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1199 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z,
1200 info->src.resource, info->src.box.z,
1201 ~0, sctx->custom_blend_resolve,
1202 format);
1203 si_blitter_end(&sctx->b.b);
1204
1205 /* Flush caches for possible texturing. */
1206 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1207 SI_CONTEXT_INV_GLOBAL_L2 |
1208 SI_CONTEXT_INV_VMEM_L1;
1209 }
1210
1211 static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
1212 const struct pipe_blit_info *info)
1213 {
1214 struct si_context *sctx = (struct si_context*)ctx;
1215 struct r600_texture *src = (struct r600_texture*)info->src.resource;
1216 struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
1217 MAYBE_UNUSED struct r600_texture *rtmp;
1218 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
1219 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
1220 enum pipe_format format = info->src.format;
1221 struct pipe_resource *tmp, templ;
1222 struct pipe_blit_info blit;
1223
1224 /* Check basic requirements for hw resolve. */
1225 if (!(info->src.resource->nr_samples > 1 &&
1226 info->dst.resource->nr_samples <= 1 &&
1227 !util_format_is_pure_integer(format) &&
1228 !util_format_is_depth_or_stencil(format) &&
1229 util_max_layer(info->src.resource, 0) == 0))
1230 return false;
1231
1232 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1233 * the format is R16G16. Use R16A16, which does work.
1234 */
1235 if (format == PIPE_FORMAT_R16G16_UNORM)
1236 format = PIPE_FORMAT_R16A16_UNORM;
1237 if (format == PIPE_FORMAT_R16G16_SNORM)
1238 format = PIPE_FORMAT_R16A16_SNORM;
1239
1240 /* Check the remaining requirements for hw resolve. */
1241 if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
1242 !info->scissor_enable &&
1243 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
1244 util_is_format_compatible(util_format_description(info->src.format),
1245 util_format_description(info->dst.format)) &&
1246 dst_width == info->src.resource->width0 &&
1247 dst_height == info->src.resource->height0 &&
1248 info->dst.box.x == 0 &&
1249 info->dst.box.y == 0 &&
1250 info->dst.box.width == dst_width &&
1251 info->dst.box.height == dst_height &&
1252 info->dst.box.depth == 1 &&
1253 info->src.box.x == 0 &&
1254 info->src.box.y == 0 &&
1255 info->src.box.width == dst_width &&
1256 info->src.box.height == dst_height &&
1257 info->src.box.depth == 1 &&
1258 !dst->surface.is_linear &&
1259 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
1260 /* Check the last constraint. */
1261 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
1262 /* The next fast clear will switch to this mode to
1263 * get direct hw resolve next time if the mode is
1264 * different now.
1265 */
1266 src->last_msaa_resolve_target_micro_mode =
1267 dst->surface.micro_tile_mode;
1268 goto resolve_to_temp;
1269 }
1270
1271 /* Resolving into a surface with DCC is unsupported. Since
1272 * it's being overwritten anyway, clear it to uncompressed.
1273 * This is still the fastest codepath even with this clear.
1274 */
1275 if (vi_dcc_enabled(dst, info->dst.level)) {
1276 /* TODO: Implement per-level DCC clears for GFX9. */
1277 if (sctx->b.chip_class >= GFX9 &&
1278 info->dst.resource->last_level != 0)
1279 goto resolve_to_temp;
1280
1281 vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
1282 0xFFFFFFFF);
1283 dst->dirty_level_mask &= ~(1 << info->dst.level);
1284 }
1285
1286 /* Resolve directly from src to dst. */
1287 si_do_CB_resolve(sctx, info, info->dst.resource,
1288 info->dst.level, info->dst.box.z, format);
1289 return true;
1290 }
1291
1292 resolve_to_temp:
1293 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1294 * a temporary texture and blit.
1295 */
1296 memset(&templ, 0, sizeof(templ));
1297 templ.target = PIPE_TEXTURE_2D;
1298 templ.format = info->src.resource->format;
1299 templ.width0 = info->src.resource->width0;
1300 templ.height0 = info->src.resource->height0;
1301 templ.depth0 = 1;
1302 templ.array_size = 1;
1303 templ.usage = PIPE_USAGE_DEFAULT;
1304 templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
1305 R600_RESOURCE_FLAG_DISABLE_DCC;
1306
1307 /* The src and dst microtile modes must be the same. */
1308 if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1309 templ.bind = PIPE_BIND_SCANOUT;
1310 else
1311 templ.bind = 0;
1312
1313 tmp = ctx->screen->resource_create(ctx->screen, &templ);
1314 if (!tmp)
1315 return false;
1316 rtmp = (struct r600_texture*)tmp;
1317
1318 assert(!rtmp->surface.is_linear);
1319 assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
1320
1321 /* resolve */
1322 si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
1323
1324 /* blit */
1325 blit = *info;
1326 blit.src.resource = tmp;
1327 blit.src.box.z = 0;
1328
1329 si_blitter_begin(ctx, SI_BLIT |
1330 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1331 util_blitter_blit(sctx->blitter, &blit);
1332 si_blitter_end(ctx);
1333
1334 pipe_resource_reference(&tmp, NULL);
1335 return true;
1336 }
1337
1338 static void si_blit(struct pipe_context *ctx,
1339 const struct pipe_blit_info *info)
1340 {
1341 struct si_context *sctx = (struct si_context*)ctx;
1342 struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
1343
1344 if (do_hardware_msaa_resolve(ctx, info)) {
1345 return;
1346 }
1347
1348 /* Using SDMA for copying to a linear texture in GTT is much faster.
1349 * This improves DRI PRIME performance.
1350 *
1351 * resource_copy_region can't do this yet, because dma_copy calls it
1352 * on failure (recursion).
1353 */
1354 if (rdst->surface.is_linear &&
1355 sctx->b.dma_copy &&
1356 util_can_blit_via_copy_region(info, false)) {
1357 sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,
1358 info->dst.box.x, info->dst.box.y,
1359 info->dst.box.z,
1360 info->src.resource, info->src.level,
1361 &info->src.box);
1362 return;
1363 }
1364
1365 assert(util_blitter_is_blit_supported(sctx->blitter, info));
1366
1367 /* The driver doesn't decompress resources automatically while
1368 * u_blitter is rendering. */
1369 vi_disable_dcc_if_incompatible_format(&sctx->b, info->src.resource,
1370 info->src.level,
1371 info->src.format);
1372 vi_disable_dcc_if_incompatible_format(&sctx->b, info->dst.resource,
1373 info->dst.level,
1374 info->dst.format);
1375 si_decompress_subresource(ctx, info->src.resource, info->mask,
1376 info->src.level,
1377 info->src.box.z,
1378 info->src.box.z + info->src.box.depth - 1);
1379
1380 if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
1381 util_try_blit_via_copy_region(ctx, info))
1382 return;
1383
1384 si_blitter_begin(ctx, SI_BLIT |
1385 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
1386 util_blitter_blit(sctx->blitter, info);
1387 si_blitter_end(ctx);
1388 }
1389
1390 static boolean si_generate_mipmap(struct pipe_context *ctx,
1391 struct pipe_resource *tex,
1392 enum pipe_format format,
1393 unsigned base_level, unsigned last_level,
1394 unsigned first_layer, unsigned last_layer)
1395 {
1396 struct si_context *sctx = (struct si_context*)ctx;
1397 struct r600_texture *rtex = (struct r600_texture *)tex;
1398
1399 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
1400 return false;
1401
1402 /* The driver doesn't decompress resources automatically while
1403 * u_blitter is rendering. */
1404 vi_disable_dcc_if_incompatible_format(&sctx->b, tex, base_level,
1405 format);
1406 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
1407 base_level, first_layer, last_layer);
1408
1409 /* Clear dirty_level_mask for the levels that will be overwritten. */
1410 assert(base_level < last_level);
1411 rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
1412 last_level - base_level);
1413
1414 sctx->generate_mipmap_for_depth = rtex->is_depth;
1415
1416 si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
1417 util_blitter_generate_mipmap(sctx->blitter, tex, format,
1418 base_level, last_level,
1419 first_layer, last_layer);
1420 si_blitter_end(ctx);
1421
1422 sctx->generate_mipmap_for_depth = false;
1423 return true;
1424 }
1425
1426 static void si_flush_resource(struct pipe_context *ctx,
1427 struct pipe_resource *res)
1428 {
1429 struct r600_texture *rtex = (struct r600_texture*)res;
1430
1431 assert(res->target != PIPE_BUFFER);
1432 assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
1433
1434 /* st/dri calls flush twice per frame (not a bug), this prevents double
1435 * decompression. */
1436 if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
1437 return;
1438
1439 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
1440 si_blit_decompress_color(ctx, rtex, 0, res->last_level,
1441 0, util_max_layer(res, 0),
1442 rtex->dcc_separate_buffer != NULL);
1443 }
1444
1445 /* Always do the analysis even if DCC is disabled at the moment. */
1446 if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
1447 rtex->separate_dcc_dirty = false;
1448 vi_separate_dcc_process_and_reset_stats(ctx, rtex);
1449 }
1450 }
1451
1452 static void si_decompress_dcc(struct pipe_context *ctx,
1453 struct r600_texture *rtex)
1454 {
1455 if (!rtex->dcc_offset)
1456 return;
1457
1458 si_blit_decompress_color(ctx, rtex, 0, rtex->resource.b.b.last_level,
1459 0, util_max_layer(&rtex->resource.b.b, 0),
1460 true);
1461 }
1462
1463 static void si_pipe_clear_buffer(struct pipe_context *ctx,
1464 struct pipe_resource *dst,
1465 unsigned offset, unsigned size,
1466 const void *clear_value_ptr,
1467 int clear_value_size)
1468 {
1469 struct si_context *sctx = (struct si_context*)ctx;
1470 uint32_t dword_value;
1471 unsigned i;
1472
1473 assert(offset % clear_value_size == 0);
1474 assert(size % clear_value_size == 0);
1475
1476 if (clear_value_size > 4) {
1477 const uint32_t *u32 = clear_value_ptr;
1478 bool clear_dword_duplicated = true;
1479
1480 /* See if we can lower large fills to dword fills. */
1481 for (i = 1; i < clear_value_size / 4; i++)
1482 if (u32[0] != u32[i]) {
1483 clear_dword_duplicated = false;
1484 break;
1485 }
1486
1487 if (!clear_dword_duplicated) {
1488 /* Use transform feedback for 64-bit, 96-bit, and
1489 * 128-bit fills.
1490 */
1491 union pipe_color_union clear_value;
1492
1493 memcpy(&clear_value, clear_value_ptr, clear_value_size);
1494 si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
1495 util_blitter_clear_buffer(sctx->blitter, dst, offset,
1496 size, clear_value_size / 4,
1497 &clear_value);
1498 si_blitter_end(ctx);
1499 return;
1500 }
1501 }
1502
1503 /* Expand the clear value to a dword. */
1504 switch (clear_value_size) {
1505 case 1:
1506 dword_value = *(uint8_t*)clear_value_ptr;
1507 dword_value |= (dword_value << 8) |
1508 (dword_value << 16) |
1509 (dword_value << 24);
1510 break;
1511 case 2:
1512 dword_value = *(uint16_t*)clear_value_ptr;
1513 dword_value |= dword_value << 16;
1514 break;
1515 default:
1516 dword_value = *(uint32_t*)clear_value_ptr;
1517 }
1518
1519 sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
1520 R600_COHERENCY_SHADER);
1521 }
1522
1523 void si_init_blit_functions(struct si_context *sctx)
1524 {
1525 sctx->b.b.clear = si_clear;
1526 sctx->b.b.clear_buffer = si_pipe_clear_buffer;
1527 sctx->b.b.clear_render_target = si_clear_render_target;
1528 sctx->b.b.clear_depth_stencil = si_clear_depth_stencil;
1529 sctx->b.b.resource_copy_region = si_resource_copy_region;
1530 sctx->b.b.blit = si_blit;
1531 sctx->b.b.flush_resource = si_flush_resource;
1532 sctx->b.b.generate_mipmap = si_generate_mipmap;
1533 sctx->b.blit_decompress_depth = si_blit_decompress_depth;
1534 sctx->b.decompress_dcc = si_decompress_dcc;
1535 }