2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_compute.h"
26 #include "util/u_format.h"
27 #include "util/u_surface.h"
29 enum si_blitter_op
/* bitmask */
32 SI_SAVE_FRAMEBUFFER
= 2,
33 SI_SAVE_FRAGMENT_STATE
= 4,
34 SI_DISABLE_RENDER_COND
= 8,
36 SI_CLEAR
= SI_SAVE_FRAGMENT_STATE
,
38 SI_CLEAR_SURFACE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
,
40 SI_COPY
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
41 SI_SAVE_FRAGMENT_STATE
| SI_DISABLE_RENDER_COND
,
43 SI_BLIT
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_TEXTURES
|
44 SI_SAVE_FRAGMENT_STATE
,
46 SI_DECOMPRESS
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
|
47 SI_DISABLE_RENDER_COND
,
49 SI_COLOR_RESOLVE
= SI_SAVE_FRAMEBUFFER
| SI_SAVE_FRAGMENT_STATE
52 static void si_blitter_begin(struct pipe_context
*ctx
, enum si_blitter_op op
)
54 struct si_context
*sctx
= (struct si_context
*)ctx
;
56 util_blitter_save_vertex_buffer_slot(sctx
->blitter
, sctx
->vertex_buffer
);
57 util_blitter_save_vertex_elements(sctx
->blitter
, sctx
->vertex_elements
);
58 util_blitter_save_vertex_shader(sctx
->blitter
, sctx
->vs_shader
.cso
);
59 util_blitter_save_tessctrl_shader(sctx
->blitter
, sctx
->tcs_shader
.cso
);
60 util_blitter_save_tesseval_shader(sctx
->blitter
, sctx
->tes_shader
.cso
);
61 util_blitter_save_geometry_shader(sctx
->blitter
, sctx
->gs_shader
.cso
);
62 util_blitter_save_so_targets(sctx
->blitter
, sctx
->b
.streamout
.num_targets
,
63 (struct pipe_stream_output_target
**)sctx
->b
.streamout
.targets
);
64 util_blitter_save_rasterizer(sctx
->blitter
, sctx
->queued
.named
.rasterizer
);
66 if (op
& SI_SAVE_FRAGMENT_STATE
) {
67 util_blitter_save_blend(sctx
->blitter
, sctx
->queued
.named
.blend
);
68 util_blitter_save_depth_stencil_alpha(sctx
->blitter
, sctx
->queued
.named
.dsa
);
69 util_blitter_save_stencil_ref(sctx
->blitter
, &sctx
->stencil_ref
.state
);
70 util_blitter_save_fragment_shader(sctx
->blitter
, sctx
->ps_shader
.cso
);
71 util_blitter_save_sample_mask(sctx
->blitter
, sctx
->sample_mask
.sample_mask
);
72 util_blitter_save_viewport(sctx
->blitter
, &sctx
->b
.viewports
.states
[0]);
73 util_blitter_save_scissor(sctx
->blitter
, &sctx
->b
.scissors
.states
[0]);
76 if (op
& SI_SAVE_FRAMEBUFFER
)
77 util_blitter_save_framebuffer(sctx
->blitter
, &sctx
->framebuffer
.state
);
79 if (op
& SI_SAVE_TEXTURES
) {
80 util_blitter_save_fragment_sampler_states(
82 (void**)sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.sampler_states
);
84 util_blitter_save_fragment_sampler_views(sctx
->blitter
, 2,
85 sctx
->samplers
[PIPE_SHADER_FRAGMENT
].views
.views
);
88 if (op
& SI_DISABLE_RENDER_COND
)
89 sctx
->b
.render_cond_force_off
= true;
92 static void si_blitter_end(struct pipe_context
*ctx
)
94 struct si_context
*sctx
= (struct si_context
*)ctx
;
96 sctx
->b
.render_cond_force_off
= false;
99 static unsigned u_max_sample(struct pipe_resource
*r
)
101 return r
->nr_samples
? r
->nr_samples
- 1 : 0;
105 si_blit_dbcb_copy(struct si_context
*sctx
,
106 struct r600_texture
*src
,
107 struct r600_texture
*dst
,
108 unsigned planes
, unsigned level_mask
,
109 unsigned first_layer
, unsigned last_layer
,
110 unsigned first_sample
, unsigned last_sample
)
112 struct pipe_surface surf_tmpl
= {{0}};
113 unsigned layer
, sample
, checked_last_layer
, max_layer
;
114 unsigned fully_copied_levels
= 0;
116 if (planes
& PIPE_MASK_Z
)
117 sctx
->dbcb_depth_copy_enabled
= true;
118 if (planes
& PIPE_MASK_S
)
119 sctx
->dbcb_stencil_copy_enabled
= true;
120 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
122 assert(sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
);
124 bool old_update_dirtiness
= sctx
->framebuffer
.do_update_surf_dirtiness
;
125 sctx
->decompression_enabled
= true;
126 sctx
->framebuffer
.do_update_surf_dirtiness
= false;
129 unsigned level
= u_bit_scan(&level_mask
);
131 /* The smaller the mipmap level, the less layers there are
132 * as far as 3D textures are concerned. */
133 max_layer
= util_max_layer(&src
->resource
.b
.b
, level
);
134 checked_last_layer
= MIN2(last_layer
, max_layer
);
136 surf_tmpl
.u
.tex
.level
= level
;
138 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
139 struct pipe_surface
*zsurf
, *cbsurf
;
141 surf_tmpl
.format
= src
->resource
.b
.b
.format
;
142 surf_tmpl
.u
.tex
.first_layer
= layer
;
143 surf_tmpl
.u
.tex
.last_layer
= layer
;
145 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &src
->resource
.b
.b
, &surf_tmpl
);
147 surf_tmpl
.format
= dst
->resource
.b
.b
.format
;
148 cbsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &dst
->resource
.b
.b
, &surf_tmpl
);
150 for (sample
= first_sample
; sample
<= last_sample
; sample
++) {
151 if (sample
!= sctx
->dbcb_copy_sample
) {
152 sctx
->dbcb_copy_sample
= sample
;
153 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
156 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
157 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, cbsurf
, 1 << sample
,
158 sctx
->custom_dsa_flush
, 1.0f
);
159 si_blitter_end(&sctx
->b
.b
);
162 pipe_surface_reference(&zsurf
, NULL
);
163 pipe_surface_reference(&cbsurf
, NULL
);
166 if (first_layer
== 0 && last_layer
>= max_layer
&&
167 first_sample
== 0 && last_sample
>= u_max_sample(&src
->resource
.b
.b
))
168 fully_copied_levels
|= 1u << level
;
171 sctx
->decompression_enabled
= false;
172 sctx
->framebuffer
.do_update_surf_dirtiness
= old_update_dirtiness
;
173 sctx
->dbcb_depth_copy_enabled
= false;
174 sctx
->dbcb_stencil_copy_enabled
= false;
175 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
177 return fully_copied_levels
;
180 static void si_blit_decompress_depth(struct pipe_context
*ctx
,
181 struct r600_texture
*texture
,
182 struct r600_texture
*staging
,
183 unsigned first_level
, unsigned last_level
,
184 unsigned first_layer
, unsigned last_layer
,
185 unsigned first_sample
, unsigned last_sample
)
187 const struct util_format_description
*desc
;
190 assert(staging
!= NULL
&& "use si_blit_decompress_zs_in_place instead");
192 desc
= util_format_description(staging
->resource
.b
.b
.format
);
194 if (util_format_has_depth(desc
))
195 planes
|= PIPE_MASK_Z
;
196 if (util_format_has_stencil(desc
))
197 planes
|= PIPE_MASK_S
;
200 (struct si_context
*)ctx
, texture
, staging
, planes
,
201 u_bit_consecutive(first_level
, last_level
- first_level
+ 1),
202 first_layer
, last_layer
, first_sample
, last_sample
);
205 /* Helper function for si_blit_decompress_zs_in_place.
208 si_blit_decompress_zs_planes_in_place(struct si_context
*sctx
,
209 struct r600_texture
*texture
,
210 unsigned planes
, unsigned level_mask
,
211 unsigned first_layer
, unsigned last_layer
)
213 struct pipe_surface
*zsurf
, surf_tmpl
= {{0}};
214 unsigned layer
, max_layer
, checked_last_layer
;
215 unsigned fully_decompressed_mask
= 0;
220 if (planes
& PIPE_MASK_S
)
221 sctx
->db_flush_stencil_inplace
= true;
222 if (planes
& PIPE_MASK_Z
)
223 sctx
->db_flush_depth_inplace
= true;
224 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
226 surf_tmpl
.format
= texture
->resource
.b
.b
.format
;
228 bool old_update_dirtiness
= sctx
->framebuffer
.do_update_surf_dirtiness
;
229 sctx
->decompression_enabled
= true;
230 sctx
->framebuffer
.do_update_surf_dirtiness
= false;
233 unsigned level
= u_bit_scan(&level_mask
);
235 surf_tmpl
.u
.tex
.level
= level
;
237 /* The smaller the mipmap level, the less layers there are
238 * as far as 3D textures are concerned. */
239 max_layer
= util_max_layer(&texture
->resource
.b
.b
, level
);
240 checked_last_layer
= MIN2(last_layer
, max_layer
);
242 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
243 surf_tmpl
.u
.tex
.first_layer
= layer
;
244 surf_tmpl
.u
.tex
.last_layer
= layer
;
246 zsurf
= sctx
->b
.b
.create_surface(&sctx
->b
.b
, &texture
->resource
.b
.b
, &surf_tmpl
);
248 si_blitter_begin(&sctx
->b
.b
, SI_DECOMPRESS
);
249 util_blitter_custom_depth_stencil(sctx
->blitter
, zsurf
, NULL
, ~0,
250 sctx
->custom_dsa_flush
,
252 si_blitter_end(&sctx
->b
.b
);
254 pipe_surface_reference(&zsurf
, NULL
);
257 /* The texture will always be dirty if some layers aren't flushed.
258 * I don't think this case occurs often though. */
259 if (first_layer
== 0 && last_layer
>= max_layer
) {
260 fully_decompressed_mask
|= 1u << level
;
264 if (planes
& PIPE_MASK_Z
)
265 texture
->dirty_level_mask
&= ~fully_decompressed_mask
;
266 if (planes
& PIPE_MASK_S
)
267 texture
->stencil_dirty_level_mask
&= ~fully_decompressed_mask
;
269 sctx
->decompression_enabled
= false;
270 sctx
->framebuffer
.do_update_surf_dirtiness
= old_update_dirtiness
;
271 sctx
->db_flush_depth_inplace
= false;
272 sctx
->db_flush_stencil_inplace
= false;
273 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
276 /* Helper function of si_flush_depth_texture: decompress the given levels
277 * of Z and/or S planes in place.
280 si_blit_decompress_zs_in_place(struct si_context
*sctx
,
281 struct r600_texture
*texture
,
282 unsigned levels_z
, unsigned levels_s
,
283 unsigned first_layer
, unsigned last_layer
)
285 unsigned both
= levels_z
& levels_s
;
287 /* First, do combined Z & S decompresses for levels that need it. */
289 si_blit_decompress_zs_planes_in_place(
290 sctx
, texture
, PIPE_MASK_Z
| PIPE_MASK_S
,
292 first_layer
, last_layer
);
297 /* Now do separate Z and S decompresses. */
299 si_blit_decompress_zs_planes_in_place(
300 sctx
, texture
, PIPE_MASK_Z
,
302 first_layer
, last_layer
);
306 si_blit_decompress_zs_planes_in_place(
307 sctx
, texture
, PIPE_MASK_S
,
309 first_layer
, last_layer
);
314 si_decompress_depth(struct si_context
*sctx
,
315 struct r600_texture
*tex
,
316 unsigned required_planes
,
317 unsigned first_level
, unsigned last_level
,
318 unsigned first_layer
, unsigned last_layer
)
320 unsigned inplace_planes
= 0;
321 unsigned copy_planes
= 0;
322 unsigned level_mask
= u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
323 unsigned levels_z
= 0;
324 unsigned levels_s
= 0;
326 if (required_planes
& PIPE_MASK_Z
) {
327 levels_z
= level_mask
& tex
->dirty_level_mask
;
330 if (r600_can_sample_zs(tex
, false))
331 inplace_planes
|= PIPE_MASK_Z
;
333 copy_planes
|= PIPE_MASK_Z
;
336 if (required_planes
& PIPE_MASK_S
) {
337 levels_s
= level_mask
& tex
->stencil_dirty_level_mask
;
340 if (r600_can_sample_zs(tex
, true))
341 inplace_planes
|= PIPE_MASK_S
;
343 copy_planes
|= PIPE_MASK_S
;
347 assert(!tex
->tc_compatible_htile
|| levels_z
== 0);
348 assert(!tex
->tc_compatible_htile
|| levels_s
== 0 ||
349 !r600_can_sample_zs(tex
, true));
351 /* We may have to allocate the flushed texture here when called from
352 * si_decompress_subresource.
355 (tex
->flushed_depth_texture
||
356 r600_init_flushed_depth_texture(&sctx
->b
.b
, &tex
->resource
.b
.b
, NULL
))) {
357 struct r600_texture
*dst
= tex
->flushed_depth_texture
;
358 unsigned fully_copied_levels
;
361 assert(tex
->flushed_depth_texture
);
363 if (util_format_is_depth_and_stencil(dst
->resource
.b
.b
.format
))
364 copy_planes
= PIPE_MASK_Z
| PIPE_MASK_S
;
366 if (copy_planes
& PIPE_MASK_Z
) {
370 if (copy_planes
& PIPE_MASK_S
) {
375 fully_copied_levels
= si_blit_dbcb_copy(
376 sctx
, tex
, dst
, copy_planes
, levels
,
377 first_layer
, last_layer
,
378 0, u_max_sample(&tex
->resource
.b
.b
));
380 if (copy_planes
& PIPE_MASK_Z
)
381 tex
->dirty_level_mask
&= ~fully_copied_levels
;
382 if (copy_planes
& PIPE_MASK_S
)
383 tex
->stencil_dirty_level_mask
&= ~fully_copied_levels
;
386 if (inplace_planes
) {
387 si_blit_decompress_zs_in_place(
390 first_layer
, last_layer
);
395 si_decompress_sampler_depth_textures(struct si_context
*sctx
,
396 struct si_textures_info
*textures
)
399 unsigned mask
= textures
->needs_depth_decompress_mask
;
402 struct pipe_sampler_view
*view
;
403 struct si_sampler_view
*sview
;
404 struct r600_texture
*tex
;
406 i
= u_bit_scan(&mask
);
408 view
= textures
->views
.views
[i
];
410 sview
= (struct si_sampler_view
*)view
;
412 tex
= (struct r600_texture
*)view
->texture
;
413 assert(tex
->db_compatible
);
415 si_decompress_depth(sctx
, tex
,
416 sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
417 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
418 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
));
422 static void si_blit_decompress_color(struct pipe_context
*ctx
,
423 struct r600_texture
*rtex
,
424 unsigned first_level
, unsigned last_level
,
425 unsigned first_layer
, unsigned last_layer
,
426 bool need_dcc_decompress
)
428 struct si_context
*sctx
= (struct si_context
*)ctx
;
430 unsigned layer
, checked_last_layer
, max_layer
;
431 unsigned level_mask
=
432 u_bit_consecutive(first_level
, last_level
- first_level
+ 1);
434 if (!need_dcc_decompress
)
435 level_mask
&= rtex
->dirty_level_mask
;
439 if (rtex
->dcc_offset
&& need_dcc_decompress
) {
440 custom_blend
= sctx
->custom_blend_dcc_decompress
;
442 /* disable levels without DCC */
443 for (int i
= first_level
; i
<= last_level
; i
++) {
444 if (!vi_dcc_enabled(rtex
, i
))
445 level_mask
&= ~(1 << i
);
447 } else if (rtex
->fmask
.size
) {
448 custom_blend
= sctx
->custom_blend_fmask_decompress
;
450 custom_blend
= sctx
->custom_blend_eliminate_fastclear
;
453 bool old_update_dirtiness
= sctx
->framebuffer
.do_update_surf_dirtiness
;
454 sctx
->decompression_enabled
= true;
455 sctx
->framebuffer
.do_update_surf_dirtiness
= false;
458 unsigned level
= u_bit_scan(&level_mask
);
460 /* The smaller the mipmap level, the less layers there are
461 * as far as 3D textures are concerned. */
462 max_layer
= util_max_layer(&rtex
->resource
.b
.b
, level
);
463 checked_last_layer
= MIN2(last_layer
, max_layer
);
465 for (layer
= first_layer
; layer
<= checked_last_layer
; layer
++) {
466 struct pipe_surface
*cbsurf
, surf_tmpl
;
468 surf_tmpl
.format
= rtex
->resource
.b
.b
.format
;
469 surf_tmpl
.u
.tex
.level
= level
;
470 surf_tmpl
.u
.tex
.first_layer
= layer
;
471 surf_tmpl
.u
.tex
.last_layer
= layer
;
472 cbsurf
= ctx
->create_surface(ctx
, &rtex
->resource
.b
.b
, &surf_tmpl
);
474 si_blitter_begin(ctx
, SI_DECOMPRESS
);
475 util_blitter_custom_color(sctx
->blitter
, cbsurf
, custom_blend
);
478 pipe_surface_reference(&cbsurf
, NULL
);
481 /* The texture will always be dirty if some layers aren't flushed.
482 * I don't think this case occurs often though. */
483 if (first_layer
== 0 && last_layer
>= max_layer
) {
484 rtex
->dirty_level_mask
&= ~(1 << level
);
488 sctx
->decompression_enabled
= false;
489 sctx
->framebuffer
.do_update_surf_dirtiness
= old_update_dirtiness
;
493 si_decompress_color_texture(struct si_context
*sctx
, struct r600_texture
*tex
,
494 unsigned first_level
, unsigned last_level
)
496 /* CMASK or DCC can be discarded and we can still end up here. */
497 if (!tex
->cmask
.size
&& !tex
->fmask
.size
&& !tex
->dcc_offset
)
500 si_blit_decompress_color(&sctx
->b
.b
, tex
, first_level
, last_level
, 0,
501 util_max_layer(&tex
->resource
.b
.b
, first_level
),
506 si_decompress_sampler_color_textures(struct si_context
*sctx
,
507 struct si_textures_info
*textures
)
510 unsigned mask
= textures
->needs_color_decompress_mask
;
513 struct pipe_sampler_view
*view
;
514 struct r600_texture
*tex
;
516 i
= u_bit_scan(&mask
);
518 view
= textures
->views
.views
[i
];
521 tex
= (struct r600_texture
*)view
->texture
;
523 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
,
524 view
->u
.tex
.last_level
);
529 si_decompress_image_color_textures(struct si_context
*sctx
,
530 struct si_images_info
*images
)
533 unsigned mask
= images
->needs_color_decompress_mask
;
536 const struct pipe_image_view
*view
;
537 struct r600_texture
*tex
;
539 i
= u_bit_scan(&mask
);
541 view
= &images
->views
[i
];
542 assert(view
->resource
->target
!= PIPE_BUFFER
);
544 tex
= (struct r600_texture
*)view
->resource
;
546 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
,
551 static void si_check_render_feedback_texture(struct si_context
*sctx
,
552 struct r600_texture
*tex
,
553 unsigned first_level
,
555 unsigned first_layer
,
558 bool render_feedback
= false;
560 if (!tex
->dcc_offset
)
563 for (unsigned j
= 0; j
< sctx
->framebuffer
.state
.nr_cbufs
; ++j
) {
564 struct r600_surface
* surf
;
566 if (!sctx
->framebuffer
.state
.cbufs
[j
])
569 surf
= (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[j
];
571 if (tex
== (struct r600_texture
*)surf
->base
.texture
&&
572 surf
->base
.u
.tex
.level
>= first_level
&&
573 surf
->base
.u
.tex
.level
<= last_level
&&
574 surf
->base
.u
.tex
.first_layer
<= last_layer
&&
575 surf
->base
.u
.tex
.last_layer
>= first_layer
) {
576 render_feedback
= true;
582 r600_texture_disable_dcc(&sctx
->b
, tex
);
585 static void si_check_render_feedback_textures(struct si_context
*sctx
,
586 struct si_textures_info
*textures
)
588 uint32_t mask
= textures
->views
.enabled_mask
;
591 const struct pipe_sampler_view
*view
;
592 struct r600_texture
*tex
;
594 unsigned i
= u_bit_scan(&mask
);
596 view
= textures
->views
.views
[i
];
597 if(view
->texture
->target
== PIPE_BUFFER
)
600 tex
= (struct r600_texture
*)view
->texture
;
602 si_check_render_feedback_texture(sctx
, tex
,
603 view
->u
.tex
.first_level
,
604 view
->u
.tex
.last_level
,
605 view
->u
.tex
.first_layer
,
606 view
->u
.tex
.last_layer
);
610 static void si_check_render_feedback_images(struct si_context
*sctx
,
611 struct si_images_info
*images
)
613 uint32_t mask
= images
->enabled_mask
;
616 const struct pipe_image_view
*view
;
617 struct r600_texture
*tex
;
619 unsigned i
= u_bit_scan(&mask
);
621 view
= &images
->views
[i
];
622 if (view
->resource
->target
== PIPE_BUFFER
)
625 tex
= (struct r600_texture
*)view
->resource
;
627 si_check_render_feedback_texture(sctx
, tex
,
630 view
->u
.tex
.first_layer
,
631 view
->u
.tex
.last_layer
);
635 static void si_check_render_feedback_resident_textures(struct si_context
*sctx
)
637 util_dynarray_foreach(&sctx
->resident_tex_handles
,
638 struct si_texture_handle
*, tex_handle
) {
639 struct pipe_sampler_view
*view
;
640 struct r600_texture
*tex
;
642 view
= (*tex_handle
)->view
;
643 if (view
->texture
->target
== PIPE_BUFFER
)
646 tex
= (struct r600_texture
*)view
->texture
;
648 si_check_render_feedback_texture(sctx
, tex
,
649 view
->u
.tex
.first_level
,
650 view
->u
.tex
.last_level
,
651 view
->u
.tex
.first_layer
,
652 view
->u
.tex
.last_layer
);
656 static void si_check_render_feedback_resident_images(struct si_context
*sctx
)
658 util_dynarray_foreach(&sctx
->resident_img_handles
,
659 struct si_image_handle
*, img_handle
) {
660 struct pipe_image_view
*view
;
661 struct r600_texture
*tex
;
663 view
= &(*img_handle
)->view
;
664 if (view
->resource
->target
== PIPE_BUFFER
)
667 tex
= (struct r600_texture
*)view
->resource
;
669 si_check_render_feedback_texture(sctx
, tex
,
672 view
->u
.tex
.first_layer
,
673 view
->u
.tex
.last_layer
);
677 static void si_check_render_feedback(struct si_context
*sctx
)
680 if (!sctx
->need_check_render_feedback
)
683 for (int i
= 0; i
< SI_NUM_SHADERS
; ++i
) {
684 si_check_render_feedback_images(sctx
, &sctx
->images
[i
]);
685 si_check_render_feedback_textures(sctx
, &sctx
->samplers
[i
]);
688 si_check_render_feedback_resident_images(sctx
);
689 si_check_render_feedback_resident_textures(sctx
);
691 sctx
->need_check_render_feedback
= false;
694 static void si_decompress_resident_textures(struct si_context
*sctx
)
696 util_dynarray_foreach(&sctx
->resident_tex_needs_color_decompress
,
697 struct si_texture_handle
*, tex_handle
) {
698 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
699 struct r600_texture
*tex
= (struct r600_texture
*)view
->texture
;
701 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.first_level
,
702 view
->u
.tex
.last_level
);
705 util_dynarray_foreach(&sctx
->resident_tex_needs_depth_decompress
,
706 struct si_texture_handle
*, tex_handle
) {
707 struct pipe_sampler_view
*view
= (*tex_handle
)->view
;
708 struct si_sampler_view
*sview
= (struct si_sampler_view
*)view
;
709 struct r600_texture
*tex
= (struct r600_texture
*)view
->texture
;
711 si_decompress_depth(sctx
, tex
,
712 sview
->is_stencil_sampler
? PIPE_MASK_S
: PIPE_MASK_Z
,
713 view
->u
.tex
.first_level
, view
->u
.tex
.last_level
,
714 0, util_max_layer(&tex
->resource
.b
.b
, view
->u
.tex
.first_level
));
718 static void si_decompress_resident_images(struct si_context
*sctx
)
720 util_dynarray_foreach(&sctx
->resident_img_needs_color_decompress
,
721 struct si_image_handle
*, img_handle
) {
722 struct pipe_image_view
*view
= &(*img_handle
)->view
;
723 struct r600_texture
*tex
= (struct r600_texture
*)view
->resource
;
725 si_decompress_color_texture(sctx
, tex
, view
->u
.tex
.level
,
730 static void si_decompress_textures(struct si_context
*sctx
, unsigned shader_mask
)
732 unsigned compressed_colortex_counter
, mask
;
734 if (sctx
->blitter
->running
)
737 /* Update the compressed_colortex_mask if necessary. */
738 compressed_colortex_counter
= p_atomic_read(&sctx
->screen
->b
.compressed_colortex_counter
);
739 if (compressed_colortex_counter
!= sctx
->b
.last_compressed_colortex_counter
) {
740 sctx
->b
.last_compressed_colortex_counter
= compressed_colortex_counter
;
741 si_update_needs_color_decompress_masks(sctx
);
744 /* Decompress color & depth textures if needed. */
745 mask
= sctx
->shader_needs_decompress_mask
& shader_mask
;
747 unsigned i
= u_bit_scan(&mask
);
749 if (sctx
->samplers
[i
].needs_depth_decompress_mask
) {
750 si_decompress_sampler_depth_textures(sctx
, &sctx
->samplers
[i
]);
752 if (sctx
->samplers
[i
].needs_color_decompress_mask
) {
753 si_decompress_sampler_color_textures(sctx
, &sctx
->samplers
[i
]);
755 if (sctx
->images
[i
].needs_color_decompress_mask
) {
756 si_decompress_image_color_textures(sctx
, &sctx
->images
[i
]);
760 if (shader_mask
& u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
)) {
761 if (sctx
->uses_bindless_samplers
)
762 si_decompress_resident_textures(sctx
);
763 if (sctx
->uses_bindless_images
)
764 si_decompress_resident_images(sctx
);
765 } else if (shader_mask
& (1 << PIPE_SHADER_COMPUTE
)) {
766 if (sctx
->cs_shader_state
.program
->uses_bindless_samplers
)
767 si_decompress_resident_textures(sctx
);
768 if (sctx
->cs_shader_state
.program
->uses_bindless_images
)
769 si_decompress_resident_images(sctx
);
772 si_check_render_feedback(sctx
);
775 void si_decompress_graphics_textures(struct si_context
*sctx
)
777 si_decompress_textures(sctx
, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
));
780 void si_decompress_compute_textures(struct si_context
*sctx
)
782 si_decompress_textures(sctx
, 1 << PIPE_SHADER_COMPUTE
);
785 static void si_clear(struct pipe_context
*ctx
, unsigned buffers
,
786 const union pipe_color_union
*color
,
787 double depth
, unsigned stencil
)
789 struct si_context
*sctx
= (struct si_context
*)ctx
;
790 struct pipe_framebuffer_state
*fb
= &sctx
->framebuffer
.state
;
791 struct pipe_surface
*zsbuf
= fb
->zsbuf
;
792 struct r600_texture
*zstex
=
793 zsbuf
? (struct r600_texture
*)zsbuf
->texture
: NULL
;
795 if (buffers
& PIPE_CLEAR_COLOR
) {
796 evergreen_do_fast_color_clear(&sctx
->b
, fb
,
797 &sctx
->framebuffer
.atom
, &buffers
,
798 &sctx
->framebuffer
.dirty_cbufs
,
801 return; /* all buffers have been fast cleared */
804 if (buffers
& PIPE_CLEAR_COLOR
) {
807 /* These buffers cannot use fast clear, make sure to disable expansion. */
808 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
809 struct r600_texture
*tex
;
811 /* If not clearing this buffer, skip. */
812 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
818 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
819 if (tex
->fmask
.size
== 0)
820 tex
->dirty_level_mask
&= ~(1 << fb
->cbufs
[i
]->u
.tex
.level
);
824 if (zstex
&& zstex
->htile_offset
&&
825 zsbuf
->u
.tex
.level
== 0 &&
826 zsbuf
->u
.tex
.first_layer
== 0 &&
827 zsbuf
->u
.tex
.last_layer
== util_max_layer(&zstex
->resource
.b
.b
, 0)) {
828 /* TC-compatible HTILE only supports depth clears to 0 or 1. */
829 if (buffers
& PIPE_CLEAR_DEPTH
&&
830 (!zstex
->tc_compatible_htile
||
831 depth
== 0 || depth
== 1)) {
832 /* Need to disable EXPCLEAR temporarily if clearing
834 if (!zstex
->depth_cleared
|| zstex
->depth_clear_value
!= depth
) {
835 sctx
->db_depth_disable_expclear
= true;
838 zstex
->depth_clear_value
= depth
;
839 sctx
->framebuffer
.dirty_zsbuf
= true;
840 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_DEPTH_CLEAR */
841 sctx
->db_depth_clear
= true;
842 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
845 /* TC-compatible HTILE only supports stencil clears to 0. */
846 if (buffers
& PIPE_CLEAR_STENCIL
&&
847 (!zstex
->tc_compatible_htile
|| stencil
== 0)) {
850 /* Need to disable EXPCLEAR temporarily if clearing
852 if (!zstex
->stencil_cleared
|| zstex
->stencil_clear_value
!= stencil
) {
853 sctx
->db_stencil_disable_expclear
= true;
856 zstex
->stencil_clear_value
= stencil
;
857 sctx
->framebuffer
.dirty_zsbuf
= true;
858 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
); /* updates DB_STENCIL_CLEAR */
859 sctx
->db_stencil_clear
= true;
860 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
864 si_blitter_begin(ctx
, SI_CLEAR
);
865 util_blitter_clear(sctx
->blitter
, fb
->width
, fb
->height
,
866 util_framebuffer_get_num_layers(fb
),
867 buffers
, color
, depth
, stencil
);
870 if (sctx
->db_depth_clear
) {
871 sctx
->db_depth_clear
= false;
872 sctx
->db_depth_disable_expclear
= false;
873 zstex
->depth_cleared
= true;
874 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
877 if (sctx
->db_stencil_clear
) {
878 sctx
->db_stencil_clear
= false;
879 sctx
->db_stencil_disable_expclear
= false;
880 zstex
->stencil_cleared
= true;
881 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
885 static void si_clear_render_target(struct pipe_context
*ctx
,
886 struct pipe_surface
*dst
,
887 const union pipe_color_union
*color
,
888 unsigned dstx
, unsigned dsty
,
889 unsigned width
, unsigned height
,
890 bool render_condition_enabled
)
892 struct si_context
*sctx
= (struct si_context
*)ctx
;
894 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
|
895 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
896 util_blitter_clear_render_target(sctx
->blitter
, dst
, color
,
897 dstx
, dsty
, width
, height
);
901 static void si_clear_depth_stencil(struct pipe_context
*ctx
,
902 struct pipe_surface
*dst
,
903 unsigned clear_flags
,
906 unsigned dstx
, unsigned dsty
,
907 unsigned width
, unsigned height
,
908 bool render_condition_enabled
)
910 struct si_context
*sctx
= (struct si_context
*)ctx
;
912 si_blitter_begin(ctx
, SI_CLEAR_SURFACE
|
913 (render_condition_enabled
? 0 : SI_DISABLE_RENDER_COND
));
914 util_blitter_clear_depth_stencil(sctx
->blitter
, dst
, clear_flags
, depth
, stencil
,
915 dstx
, dsty
, width
, height
);
919 /* Helper for decompressing a portion of a color or depth resource before
920 * blitting if any decompression is needed.
921 * The driver doesn't decompress resources automatically while u_blitter is
923 static void si_decompress_subresource(struct pipe_context
*ctx
,
924 struct pipe_resource
*tex
,
925 unsigned planes
, unsigned level
,
926 unsigned first_layer
, unsigned last_layer
)
928 struct si_context
*sctx
= (struct si_context
*)ctx
;
929 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
931 if (rtex
->db_compatible
) {
932 planes
&= PIPE_MASK_Z
| PIPE_MASK_S
;
934 if (!(rtex
->surface
.flags
& RADEON_SURF_SBUFFER
))
935 planes
&= ~PIPE_MASK_S
;
937 si_decompress_depth(sctx
, rtex
, planes
,
939 first_layer
, last_layer
);
940 } else if (rtex
->fmask
.size
|| rtex
->cmask
.size
|| rtex
->dcc_offset
) {
941 si_blit_decompress_color(ctx
, rtex
, level
, level
,
942 first_layer
, last_layer
, false);
946 struct texture_orig_info
{
956 void si_resource_copy_region(struct pipe_context
*ctx
,
957 struct pipe_resource
*dst
,
959 unsigned dstx
, unsigned dsty
, unsigned dstz
,
960 struct pipe_resource
*src
,
962 const struct pipe_box
*src_box
)
964 struct si_context
*sctx
= (struct si_context
*)ctx
;
965 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
966 struct pipe_surface
*dst_view
, dst_templ
;
967 struct pipe_sampler_view src_templ
, *src_view
;
968 unsigned dst_width
, dst_height
, src_width0
, src_height0
;
969 unsigned dst_width0
, dst_height0
, src_force_level
= 0;
970 struct pipe_box sbox
, dstbox
;
972 /* Handle buffers first. */
973 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
974 si_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
, 0);
978 assert(u_max_sample(dst
) == u_max_sample(src
));
980 /* The driver doesn't decompress resources automatically while
981 * u_blitter is rendering. */
982 si_decompress_subresource(ctx
, src
, PIPE_MASK_RGBAZS
, src_level
,
983 src_box
->z
, src_box
->z
+ src_box
->depth
- 1);
985 dst_width
= u_minify(dst
->width0
, dst_level
);
986 dst_height
= u_minify(dst
->height0
, dst_level
);
987 dst_width0
= dst
->width0
;
988 dst_height0
= dst
->height0
;
989 src_width0
= src
->width0
;
990 src_height0
= src
->height0
;
992 util_blitter_default_dst_texture(&dst_templ
, dst
, dst_level
, dstz
);
993 util_blitter_default_src_texture(sctx
->blitter
, &src_templ
, src
, src_level
);
995 if (util_format_is_compressed(src
->format
) ||
996 util_format_is_compressed(dst
->format
)) {
997 unsigned blocksize
= rsrc
->surface
.bpe
;
1000 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
; /* 64-bit block */
1002 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
; /* 128-bit block */
1003 dst_templ
.format
= src_templ
.format
;
1005 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
1006 dst_height
= util_format_get_nblocksy(dst
->format
, dst_height
);
1007 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
1008 dst_height0
= util_format_get_nblocksy(dst
->format
, dst_height0
);
1009 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
1010 src_height0
= util_format_get_nblocksy(src
->format
, src_height0
);
1012 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
1013 dsty
= util_format_get_nblocksy(dst
->format
, dsty
);
1015 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
1016 sbox
.y
= util_format_get_nblocksy(src
->format
, src_box
->y
);
1017 sbox
.z
= src_box
->z
;
1018 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
1019 sbox
.height
= util_format_get_nblocksy(src
->format
, src_box
->height
);
1020 sbox
.depth
= src_box
->depth
;
1023 src_force_level
= src_level
;
1024 } else if (!util_blitter_is_copy_supported(sctx
->blitter
, dst
, src
)) {
1025 if (util_format_is_subsampled_422(src
->format
)) {
1026 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
1027 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UINT
;
1029 dst_width
= util_format_get_nblocksx(dst
->format
, dst_width
);
1030 dst_width0
= util_format_get_nblocksx(dst
->format
, dst_width0
);
1031 src_width0
= util_format_get_nblocksx(src
->format
, src_width0
);
1033 dstx
= util_format_get_nblocksx(dst
->format
, dstx
);
1036 sbox
.x
= util_format_get_nblocksx(src
->format
, src_box
->x
);
1037 sbox
.width
= util_format_get_nblocksx(src
->format
, src_box
->width
);
1040 unsigned blocksize
= rsrc
->surface
.bpe
;
1042 switch (blocksize
) {
1044 dst_templ
.format
= PIPE_FORMAT_R8_UNORM
;
1045 src_templ
.format
= PIPE_FORMAT_R8_UNORM
;
1048 dst_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
1049 src_templ
.format
= PIPE_FORMAT_R8G8_UNORM
;
1052 dst_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
1053 src_templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
1056 dst_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1057 src_templ
.format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1060 dst_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1061 src_templ
.format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1064 fprintf(stderr
, "Unhandled format %s with blocksize %u\n",
1065 util_format_short_name(src
->format
), blocksize
);
1071 /* SNORM8 blitting has precision issues on some chips. Use the SINT
1072 * equivalent instead, which doesn't force DCC decompression.
1073 * Note that some chips avoid this issue by using SDMA.
1075 if (util_format_is_snorm8(dst_templ
.format
)) {
1076 switch (dst_templ
.format
) {
1077 case PIPE_FORMAT_R8_SNORM
:
1078 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8_SINT
;
1080 case PIPE_FORMAT_R8G8_SNORM
:
1081 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8_SINT
;
1083 case PIPE_FORMAT_R8G8B8X8_SNORM
:
1084 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8B8X8_SINT
;
1086 case PIPE_FORMAT_R8G8B8A8_SNORM
:
1087 /* There are no SINT variants for ABGR and XBGR, so we have to use RGBA. */
1088 case PIPE_FORMAT_A8B8G8R8_SNORM
:
1089 case PIPE_FORMAT_X8B8G8R8_SNORM
:
1090 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_R8G8B8A8_SINT
;
1092 case PIPE_FORMAT_A8_SNORM
:
1093 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_A8_SINT
;
1095 case PIPE_FORMAT_L8_SNORM
:
1096 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_L8_SINT
;
1098 case PIPE_FORMAT_L8A8_SNORM
:
1099 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_L8A8_SINT
;
1101 case PIPE_FORMAT_I8_SNORM
:
1102 dst_templ
.format
= src_templ
.format
= PIPE_FORMAT_I8_SINT
;
1104 default:; /* fall through */
1108 vi_disable_dcc_if_incompatible_format(&sctx
->b
, dst
, dst_level
,
1110 vi_disable_dcc_if_incompatible_format(&sctx
->b
, src
, src_level
,
1113 /* Initialize the surface. */
1114 dst_view
= r600_create_surface_custom(ctx
, dst
, &dst_templ
,
1115 dst_width0
, dst_height0
,
1116 dst_width
, dst_height
);
1118 /* Initialize the sampler view. */
1119 src_view
= si_create_sampler_view_custom(ctx
, src
, &src_templ
,
1120 src_width0
, src_height0
,
1123 u_box_3d(dstx
, dsty
, dstz
, abs(src_box
->width
), abs(src_box
->height
),
1124 abs(src_box
->depth
), &dstbox
);
1127 si_blitter_begin(ctx
, SI_COPY
);
1128 util_blitter_blit_generic(sctx
->blitter
, dst_view
, &dstbox
,
1129 src_view
, src_box
, src_width0
, src_height0
,
1130 PIPE_MASK_RGBAZS
, PIPE_TEX_FILTER_NEAREST
, NULL
,
1132 si_blitter_end(ctx
);
1134 pipe_surface_reference(&dst_view
, NULL
);
1135 pipe_sampler_view_reference(&src_view
, NULL
);
1138 static bool do_hardware_msaa_resolve(struct pipe_context
*ctx
,
1139 const struct pipe_blit_info
*info
)
1141 struct si_context
*sctx
= (struct si_context
*)ctx
;
1142 struct r600_texture
*src
= (struct r600_texture
*)info
->src
.resource
;
1143 struct r600_texture
*dst
= (struct r600_texture
*)info
->dst
.resource
;
1144 MAYBE_UNUSED
struct r600_texture
*rtmp
;
1145 unsigned dst_width
= u_minify(info
->dst
.resource
->width0
, info
->dst
.level
);
1146 unsigned dst_height
= u_minify(info
->dst
.resource
->height0
, info
->dst
.level
);
1147 enum pipe_format format
= info
->src
.format
;
1148 unsigned sample_mask
= ~0;
1149 struct pipe_resource
*tmp
, templ
;
1150 struct pipe_blit_info blit
;
1152 /* Check basic requirements for hw resolve. */
1153 if (!(info
->src
.resource
->nr_samples
> 1 &&
1154 info
->dst
.resource
->nr_samples
<= 1 &&
1155 !util_format_is_pure_integer(format
) &&
1156 !util_format_is_depth_or_stencil(format
) &&
1157 util_max_layer(info
->src
.resource
, 0) == 0))
1160 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
1161 * the format is R16G16. Use R16A16, which does work.
1163 if (format
== PIPE_FORMAT_R16G16_UNORM
)
1164 format
= PIPE_FORMAT_R16A16_UNORM
;
1165 if (format
== PIPE_FORMAT_R16G16_SNORM
)
1166 format
= PIPE_FORMAT_R16A16_SNORM
;
1168 /* Check the remaining requirements for hw resolve. */
1169 if (util_max_layer(info
->dst
.resource
, info
->dst
.level
) == 0 &&
1170 !info
->scissor_enable
&&
1171 (info
->mask
& PIPE_MASK_RGBA
) == PIPE_MASK_RGBA
&&
1172 util_is_format_compatible(util_format_description(info
->src
.format
),
1173 util_format_description(info
->dst
.format
)) &&
1174 dst_width
== info
->src
.resource
->width0
&&
1175 dst_height
== info
->src
.resource
->height0
&&
1176 info
->dst
.box
.x
== 0 &&
1177 info
->dst
.box
.y
== 0 &&
1178 info
->dst
.box
.width
== dst_width
&&
1179 info
->dst
.box
.height
== dst_height
&&
1180 info
->dst
.box
.depth
== 1 &&
1181 info
->src
.box
.x
== 0 &&
1182 info
->src
.box
.y
== 0 &&
1183 info
->src
.box
.width
== dst_width
&&
1184 info
->src
.box
.height
== dst_height
&&
1185 info
->src
.box
.depth
== 1 &&
1186 !dst
->surface
.is_linear
&&
1187 (!dst
->cmask
.size
|| !dst
->dirty_level_mask
)) { /* dst cannot be fast-cleared */
1188 /* Check the last constraint. */
1189 if (src
->surface
.micro_tile_mode
!= dst
->surface
.micro_tile_mode
) {
1190 /* The next fast clear will switch to this mode to
1191 * get direct hw resolve next time if the mode is
1194 src
->last_msaa_resolve_target_micro_mode
=
1195 dst
->surface
.micro_tile_mode
;
1196 goto resolve_to_temp
;
1199 /* Resolving into a surface with DCC is unsupported. Since
1200 * it's being overwritten anyway, clear it to uncompressed.
1201 * This is still the fastest codepath even with this clear.
1203 if (vi_dcc_enabled(dst
, info
->dst
.level
)) {
1204 /* TODO: Implement per-level DCC clears for GFX9. */
1205 if (sctx
->b
.chip_class
>= GFX9
&&
1206 info
->dst
.resource
->last_level
!= 0)
1207 goto resolve_to_temp
;
1209 vi_dcc_clear_level(&sctx
->b
, dst
, info
->dst
.level
,
1211 dst
->dirty_level_mask
&= ~(1 << info
->dst
.level
);
1214 /* Resolve directly from src to dst. */
1215 si_blitter_begin(ctx
, SI_COLOR_RESOLVE
|
1216 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1217 util_blitter_custom_resolve_color(sctx
->blitter
,
1218 info
->dst
.resource
, info
->dst
.level
,
1220 info
->src
.resource
, info
->src
.box
.z
,
1221 sample_mask
, sctx
->custom_blend_resolve
,
1223 si_blitter_end(ctx
);
1228 /* Shader-based resolve is VERY SLOW. Instead, resolve into
1229 * a temporary texture and blit.
1231 memset(&templ
, 0, sizeof(templ
));
1232 templ
.target
= PIPE_TEXTURE_2D
;
1233 templ
.format
= info
->src
.resource
->format
;
1234 templ
.width0
= info
->src
.resource
->width0
;
1235 templ
.height0
= info
->src
.resource
->height0
;
1237 templ
.array_size
= 1;
1238 templ
.usage
= PIPE_USAGE_DEFAULT
;
1239 templ
.flags
= R600_RESOURCE_FLAG_FORCE_TILING
|
1240 R600_RESOURCE_FLAG_DISABLE_DCC
;
1242 /* The src and dst microtile modes must be the same. */
1243 if (src
->surface
.micro_tile_mode
== RADEON_MICRO_MODE_DISPLAY
)
1244 templ
.bind
= PIPE_BIND_SCANOUT
;
1248 tmp
= ctx
->screen
->resource_create(ctx
->screen
, &templ
);
1251 rtmp
= (struct r600_texture
*)tmp
;
1253 assert(!rtmp
->surface
.is_linear
);
1254 assert(src
->surface
.micro_tile_mode
== rtmp
->surface
.micro_tile_mode
);
1257 si_blitter_begin(ctx
, SI_COLOR_RESOLVE
|
1258 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1259 util_blitter_custom_resolve_color(sctx
->blitter
, tmp
, 0, 0,
1260 info
->src
.resource
, info
->src
.box
.z
,
1261 sample_mask
, sctx
->custom_blend_resolve
,
1263 si_blitter_end(ctx
);
1267 blit
.src
.resource
= tmp
;
1270 si_blitter_begin(ctx
, SI_BLIT
|
1271 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1272 util_blitter_blit(sctx
->blitter
, &blit
);
1273 si_blitter_end(ctx
);
1275 pipe_resource_reference(&tmp
, NULL
);
1279 static void si_blit(struct pipe_context
*ctx
,
1280 const struct pipe_blit_info
*info
)
1282 struct si_context
*sctx
= (struct si_context
*)ctx
;
1283 struct r600_texture
*rdst
= (struct r600_texture
*)info
->dst
.resource
;
1285 if (do_hardware_msaa_resolve(ctx
, info
)) {
1289 /* Using SDMA for copying to a linear texture in GTT is much faster.
1290 * This improves DRI PRIME performance.
1292 * resource_copy_region can't do this yet, because dma_copy calls it
1293 * on failure (recursion).
1295 if (rdst
->surface
.is_linear
&&
1297 util_can_blit_via_copy_region(info
, false)) {
1298 sctx
->b
.dma_copy(ctx
, info
->dst
.resource
, info
->dst
.level
,
1299 info
->dst
.box
.x
, info
->dst
.box
.y
,
1301 info
->src
.resource
, info
->src
.level
,
1306 assert(util_blitter_is_blit_supported(sctx
->blitter
, info
));
1308 /* The driver doesn't decompress resources automatically while
1309 * u_blitter is rendering. */
1310 vi_disable_dcc_if_incompatible_format(&sctx
->b
, info
->src
.resource
,
1313 vi_disable_dcc_if_incompatible_format(&sctx
->b
, info
->dst
.resource
,
1316 si_decompress_subresource(ctx
, info
->src
.resource
, info
->mask
,
1319 info
->src
.box
.z
+ info
->src
.box
.depth
- 1);
1321 if (sctx
->screen
->b
.debug_flags
& DBG_FORCE_DMA
&&
1322 util_try_blit_via_copy_region(ctx
, info
))
1325 si_blitter_begin(ctx
, SI_BLIT
|
1326 (info
->render_condition_enable
? 0 : SI_DISABLE_RENDER_COND
));
1327 util_blitter_blit(sctx
->blitter
, info
);
1328 si_blitter_end(ctx
);
1331 static boolean
si_generate_mipmap(struct pipe_context
*ctx
,
1332 struct pipe_resource
*tex
,
1333 enum pipe_format format
,
1334 unsigned base_level
, unsigned last_level
,
1335 unsigned first_layer
, unsigned last_layer
)
1337 struct si_context
*sctx
= (struct si_context
*)ctx
;
1338 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1340 if (!util_blitter_is_copy_supported(sctx
->blitter
, tex
, tex
))
1343 /* The driver doesn't decompress resources automatically while
1344 * u_blitter is rendering. */
1345 vi_disable_dcc_if_incompatible_format(&sctx
->b
, tex
, base_level
,
1347 si_decompress_subresource(ctx
, tex
, PIPE_MASK_RGBAZS
,
1348 base_level
, first_layer
, last_layer
);
1350 /* Clear dirty_level_mask for the levels that will be overwritten. */
1351 assert(base_level
< last_level
);
1352 rtex
->dirty_level_mask
&= ~u_bit_consecutive(base_level
+ 1,
1353 last_level
- base_level
);
1355 si_blitter_begin(ctx
, SI_BLIT
| SI_DISABLE_RENDER_COND
);
1356 util_blitter_generate_mipmap(sctx
->blitter
, tex
, format
,
1357 base_level
, last_level
,
1358 first_layer
, last_layer
);
1359 si_blitter_end(ctx
);
1363 static void si_flush_resource(struct pipe_context
*ctx
,
1364 struct pipe_resource
*res
)
1366 struct r600_texture
*rtex
= (struct r600_texture
*)res
;
1368 assert(res
->target
!= PIPE_BUFFER
);
1369 assert(!rtex
->dcc_separate_buffer
|| rtex
->dcc_gather_statistics
);
1371 /* st/dri calls flush twice per frame (not a bug), this prevents double
1373 if (rtex
->dcc_separate_buffer
&& !rtex
->separate_dcc_dirty
)
1376 if (!rtex
->is_depth
&& (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
1377 si_blit_decompress_color(ctx
, rtex
, 0, res
->last_level
,
1378 0, util_max_layer(res
, 0),
1379 rtex
->dcc_separate_buffer
!= NULL
);
1382 /* Always do the analysis even if DCC is disabled at the moment. */
1383 if (rtex
->dcc_gather_statistics
&& rtex
->separate_dcc_dirty
) {
1384 rtex
->separate_dcc_dirty
= false;
1385 vi_separate_dcc_process_and_reset_stats(ctx
, rtex
);
1389 static void si_decompress_dcc(struct pipe_context
*ctx
,
1390 struct r600_texture
*rtex
)
1392 if (!rtex
->dcc_offset
)
1395 si_blit_decompress_color(ctx
, rtex
, 0, rtex
->resource
.b
.b
.last_level
,
1396 0, util_max_layer(&rtex
->resource
.b
.b
, 0),
1400 static void si_pipe_clear_buffer(struct pipe_context
*ctx
,
1401 struct pipe_resource
*dst
,
1402 unsigned offset
, unsigned size
,
1403 const void *clear_value_ptr
,
1404 int clear_value_size
)
1406 struct si_context
*sctx
= (struct si_context
*)ctx
;
1407 uint32_t dword_value
;
1410 assert(offset
% clear_value_size
== 0);
1411 assert(size
% clear_value_size
== 0);
1413 if (clear_value_size
> 4) {
1414 const uint32_t *u32
= clear_value_ptr
;
1415 bool clear_dword_duplicated
= true;
1417 /* See if we can lower large fills to dword fills. */
1418 for (i
= 1; i
< clear_value_size
/ 4; i
++)
1419 if (u32
[0] != u32
[i
]) {
1420 clear_dword_duplicated
= false;
1424 if (!clear_dword_duplicated
) {
1425 /* Use transform feedback for 64-bit, 96-bit, and
1428 union pipe_color_union clear_value
;
1430 memcpy(&clear_value
, clear_value_ptr
, clear_value_size
);
1431 si_blitter_begin(ctx
, SI_DISABLE_RENDER_COND
);
1432 util_blitter_clear_buffer(sctx
->blitter
, dst
, offset
,
1433 size
, clear_value_size
/ 4,
1435 si_blitter_end(ctx
);
1440 /* Expand the clear value to a dword. */
1441 switch (clear_value_size
) {
1443 dword_value
= *(uint8_t*)clear_value_ptr
;
1444 dword_value
|= (dword_value
<< 8) |
1445 (dword_value
<< 16) |
1446 (dword_value
<< 24);
1449 dword_value
= *(uint16_t*)clear_value_ptr
;
1450 dword_value
|= dword_value
<< 16;
1453 dword_value
= *(uint32_t*)clear_value_ptr
;
1456 sctx
->b
.clear_buffer(ctx
, dst
, offset
, size
, dword_value
,
1457 R600_COHERENCY_SHADER
);
1460 void si_init_blit_functions(struct si_context
*sctx
)
1462 sctx
->b
.b
.clear
= si_clear
;
1463 sctx
->b
.b
.clear_buffer
= si_pipe_clear_buffer
;
1464 sctx
->b
.b
.clear_render_target
= si_clear_render_target
;
1465 sctx
->b
.b
.clear_depth_stencil
= si_clear_depth_stencil
;
1466 sctx
->b
.b
.resource_copy_region
= si_resource_copy_region
;
1467 sctx
->b
.b
.blit
= si_blit
;
1468 sctx
->b
.b
.flush_resource
= si_flush_resource
;
1469 sctx
->b
.b
.generate_mipmap
= si_generate_mipmap
;
1470 sctx
->b
.blit_decompress_depth
= si_blit_decompress_depth
;
1471 sctx
->b
.decompress_dcc
= si_decompress_dcc
;