f7f0e26d7d080e3902374cb6013ac2692e2a4863
[mesa.git] / src / gallium / drivers / radeonsi / si_build_pm4.h
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 /**
26 * This file contains helpers for writing commands to commands streams.
27 */
28
29 #ifndef SI_BUILD_PM4_H
30 #define SI_BUILD_PM4_H
31
32 #include "si_pipe.h"
33 #include "sid.h"
34
35 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
36 {
37 assert(reg < SI_CONTEXT_REG_OFFSET);
38 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
39 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
40 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
41 }
42
43 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
44 {
45 radeon_set_config_reg_seq(cs, reg, 1);
46 radeon_emit(cs, value);
47 }
48
49 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
50 {
51 assert(reg >= SI_CONTEXT_REG_OFFSET);
52 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
53 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
54 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
55 }
56
57 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
58 {
59 radeon_set_context_reg_seq(cs, reg, 1);
60 radeon_emit(cs, value);
61 }
62
63 static inline void radeon_set_context_reg_seq_array(struct radeon_cmdbuf *cs, unsigned reg,
64 unsigned num, const uint32_t *values)
65 {
66 radeon_set_context_reg_seq(cs, reg, num);
67 radeon_emit_array(cs, values, num);
68 }
69
70 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx,
71 unsigned value)
72 {
73 assert(reg >= SI_CONTEXT_REG_OFFSET);
74 assert(cs->current.cdw + 3 <= cs->current.max_dw);
75 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
76 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
77 radeon_emit(cs, value);
78 }
79
80 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
81 {
82 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
83 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
84 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
85 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
86 }
87
88 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
89 {
90 radeon_set_sh_reg_seq(cs, reg, 1);
91 radeon_emit(cs, value);
92 }
93
94 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
95 {
96 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
97 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
98 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
99 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
100 }
101
102 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
103 {
104 radeon_set_uconfig_reg_seq(cs, reg, 1);
105 radeon_emit(cs, value);
106 }
107
108 static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs, struct si_screen *screen,
109 unsigned reg, unsigned idx, unsigned value)
110 {
111 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
112 assert(cs->current.cdw + 3 <= cs->current.max_dw);
113 assert(idx != 0);
114 unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX;
115 if (screen->info.chip_class < GFX9 ||
116 (screen->info.chip_class == GFX9 && screen->info.me_fw_version < 26))
117 opcode = PKT3_SET_UCONFIG_REG;
118 radeon_emit(cs, PKT3(opcode, 1, 0));
119 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
120 radeon_emit(cs, value);
121 }
122
123 static inline void radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, unsigned reg,
124 unsigned value, unsigned mask)
125 {
126 assert(reg >= SI_CONTEXT_REG_OFFSET);
127 assert(cs->current.cdw + 4 <= cs->current.max_dw);
128 radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));
129 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
130 radeon_emit(cs, mask);
131 radeon_emit(cs, value);
132 }
133
134 /* Emit PKT3_CONTEXT_REG_RMW if the register value is different. */
135 static inline void radeon_opt_set_context_reg_rmw(struct si_context *sctx, unsigned offset,
136 enum si_tracked_reg reg, unsigned value,
137 unsigned mask)
138 {
139 struct radeon_cmdbuf *cs = sctx->gfx_cs;
140
141 assert((value & ~mask) == 0);
142 value &= mask;
143
144 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
145 sctx->tracked_regs.reg_value[reg] != value) {
146 radeon_set_context_reg_rmw(cs, offset, value, mask);
147
148 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
149 sctx->tracked_regs.reg_value[reg] = value;
150 }
151 }
152
153 /* Emit PKT3_SET_CONTEXT_REG if the register value is different. */
154 static inline void radeon_opt_set_context_reg(struct si_context *sctx, unsigned offset,
155 enum si_tracked_reg reg, unsigned value)
156 {
157 struct radeon_cmdbuf *cs = sctx->gfx_cs;
158
159 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
160 sctx->tracked_regs.reg_value[reg] != value) {
161 radeon_set_context_reg(cs, offset, value);
162
163 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
164 sctx->tracked_regs.reg_value[reg] = value;
165 }
166 }
167
168 /**
169 * Set 2 consecutive registers if any registers value is different.
170 * @param offset starting register offset
171 * @param value1 is written to first register
172 * @param value2 is written to second register
173 */
174 static inline void radeon_opt_set_context_reg2(struct si_context *sctx, unsigned offset,
175 enum si_tracked_reg reg, unsigned value1,
176 unsigned value2)
177 {
178 struct radeon_cmdbuf *cs = sctx->gfx_cs;
179
180 if (((sctx->tracked_regs.reg_saved >> reg) & 0x3) != 0x3 ||
181 sctx->tracked_regs.reg_value[reg] != value1 ||
182 sctx->tracked_regs.reg_value[reg + 1] != value2) {
183 radeon_set_context_reg_seq(cs, offset, 2);
184 radeon_emit(cs, value1);
185 radeon_emit(cs, value2);
186
187 sctx->tracked_regs.reg_value[reg] = value1;
188 sctx->tracked_regs.reg_value[reg + 1] = value2;
189 sctx->tracked_regs.reg_saved |= 0x3ull << reg;
190 }
191 }
192
193 /**
194 * Set 3 consecutive registers if any registers value is different.
195 */
196 static inline void radeon_opt_set_context_reg3(struct si_context *sctx, unsigned offset,
197 enum si_tracked_reg reg, unsigned value1,
198 unsigned value2, unsigned value3)
199 {
200 struct radeon_cmdbuf *cs = sctx->gfx_cs;
201
202 if (((sctx->tracked_regs.reg_saved >> reg) & 0x7) != 0x7 ||
203 sctx->tracked_regs.reg_value[reg] != value1 ||
204 sctx->tracked_regs.reg_value[reg + 1] != value2 ||
205 sctx->tracked_regs.reg_value[reg + 2] != value3) {
206 radeon_set_context_reg_seq(cs, offset, 3);
207 radeon_emit(cs, value1);
208 radeon_emit(cs, value2);
209 radeon_emit(cs, value3);
210
211 sctx->tracked_regs.reg_value[reg] = value1;
212 sctx->tracked_regs.reg_value[reg + 1] = value2;
213 sctx->tracked_regs.reg_value[reg + 2] = value3;
214 sctx->tracked_regs.reg_saved |= 0x7ull << reg;
215 }
216 }
217
218 /**
219 * Set 4 consecutive registers if any registers value is different.
220 */
221 static inline void radeon_opt_set_context_reg4(struct si_context *sctx, unsigned offset,
222 enum si_tracked_reg reg, unsigned value1,
223 unsigned value2, unsigned value3, unsigned value4)
224 {
225 struct radeon_cmdbuf *cs = sctx->gfx_cs;
226
227 if (((sctx->tracked_regs.reg_saved >> reg) & 0xf) != 0xf ||
228 sctx->tracked_regs.reg_value[reg] != value1 ||
229 sctx->tracked_regs.reg_value[reg + 1] != value2 ||
230 sctx->tracked_regs.reg_value[reg + 2] != value3 ||
231 sctx->tracked_regs.reg_value[reg + 3] != value4) {
232 radeon_set_context_reg_seq(cs, offset, 4);
233 radeon_emit(cs, value1);
234 radeon_emit(cs, value2);
235 radeon_emit(cs, value3);
236 radeon_emit(cs, value4);
237
238 sctx->tracked_regs.reg_value[reg] = value1;
239 sctx->tracked_regs.reg_value[reg + 1] = value2;
240 sctx->tracked_regs.reg_value[reg + 2] = value3;
241 sctx->tracked_regs.reg_value[reg + 3] = value4;
242 sctx->tracked_regs.reg_saved |= 0xfull << reg;
243 }
244 }
245
246 /**
247 * Set consecutive registers if any registers value is different.
248 */
249 static inline void radeon_opt_set_context_regn(struct si_context *sctx, unsigned offset,
250 unsigned *value, unsigned *saved_val, unsigned num)
251 {
252 struct radeon_cmdbuf *cs = sctx->gfx_cs;
253 int i, j;
254
255 for (i = 0; i < num; i++) {
256 if (saved_val[i] != value[i]) {
257 radeon_set_context_reg_seq(cs, offset, num);
258 for (j = 0; j < num; j++)
259 radeon_emit(cs, value[j]);
260
261 memcpy(saved_val, value, sizeof(uint32_t) * num);
262 break;
263 }
264 }
265 }
266
267 #endif