24e43410164b855817f71279d85006251e8c7160
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "si_compute.h"
27
28 #include "ac_rtld.h"
29 #include "amd_kernel_code_t.h"
30 #include "nir/tgsi_to_nir.h"
31 #include "si_build_pm4.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35
36 #define COMPUTE_DBG(sscreen, fmt, args...) \
37 do { \
38 if ((sscreen->debug_flags & DBG(COMPUTE))) \
39 fprintf(stderr, fmt, ##args); \
40 } while (0);
41
42 struct dispatch_packet {
43 uint16_t header;
44 uint16_t setup;
45 uint16_t workgroup_size_x;
46 uint16_t workgroup_size_y;
47 uint16_t workgroup_size_z;
48 uint16_t reserved0;
49 uint32_t grid_size_x;
50 uint32_t grid_size_y;
51 uint32_t grid_size_z;
52 uint32_t private_segment_size;
53 uint32_t group_segment_size;
54 uint64_t kernel_object;
55 uint64_t kernarg_address;
56 uint64_t reserved2;
57 };
58
59 static const amd_kernel_code_t *si_compute_get_code_object(const struct si_compute *program,
60 uint64_t symbol_offset)
61 {
62 const struct si_shader_selector *sel = &program->sel;
63
64 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
65 return NULL;
66
67 struct ac_rtld_binary rtld;
68 if (!ac_rtld_open(&rtld,
69 (struct ac_rtld_open_info){.info = &sel->screen->info,
70 .shader_type = MESA_SHADER_COMPUTE,
71 .wave_size = sel->screen->compute_wave_size,
72 .num_parts = 1,
73 .elf_ptrs = &program->shader.binary.elf_buffer,
74 .elf_sizes = &program->shader.binary.elf_size}))
75 return NULL;
76
77 const amd_kernel_code_t *result = NULL;
78 const char *text;
79 size_t size;
80 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
81 goto out;
82
83 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
84 goto out;
85
86 result = (const amd_kernel_code_t *)(text + symbol_offset);
87
88 out:
89 ac_rtld_close(&rtld);
90 return result;
91 }
92
93 static void code_object_to_config(const amd_kernel_code_t *code_object,
94 struct ac_shader_config *out_config)
95 {
96
97 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
98 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
99 out_config->num_sgprs = code_object->wavefront_sgpr_count;
100 out_config->num_vgprs = code_object->workitem_vgpr_count;
101 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
102 out_config->rsrc1 = rsrc1;
103 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
104 out_config->rsrc2 = rsrc2;
105 out_config->scratch_bytes_per_wave =
106 align(code_object->workitem_private_segment_byte_size * 64, 1024);
107 }
108
109 /* Asynchronous compute shader compilation. */
110 static void si_create_compute_state_async(void *job, int thread_index)
111 {
112 struct si_compute *program = (struct si_compute *)job;
113 struct si_shader_selector *sel = &program->sel;
114 struct si_shader *shader = &program->shader;
115 struct ac_llvm_compiler *compiler;
116 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
117 struct si_screen *sscreen = sel->screen;
118
119 assert(!debug->debug_message || debug->async);
120 assert(thread_index >= 0);
121 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
122 compiler = &sscreen->compiler[thread_index];
123
124 if (!compiler->passes)
125 si_init_compiler(sscreen, compiler);
126
127 assert(program->ir_type == PIPE_SHADER_IR_NIR);
128 si_nir_scan_shader(sel->nir, &sel->info);
129
130 /* Store the declared LDS size into si_shader_info for the shader
131 * cache to include it.
132 */
133 sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
134
135 si_get_active_slot_masks(&sel->info, &sel->active_const_and_shader_buffers,
136 &sel->active_samplers_and_images);
137
138 program->shader.is_monolithic = true;
139 program->reads_variable_block_size =
140 sel->info.uses_block_size && sel->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
141 program->num_cs_user_data_dwords =
142 sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
143
144 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS + (sel->info.uses_grid_size ? 3 : 0) +
145 (program->reads_variable_block_size ? 3 : 0) +
146 program->num_cs_user_data_dwords;
147
148 /* Fast path for compute shaders - some descriptors passed via user SGPRs. */
149 /* Shader buffers in user SGPRs. */
150 for (unsigned i = 0; i < 3 && user_sgprs <= 12 && sel->info.shader_buffers_declared & (1 << i); i++) {
151 user_sgprs = align(user_sgprs, 4);
152 if (i == 0)
153 sel->cs_shaderbufs_sgpr_index = user_sgprs;
154 user_sgprs += 4;
155 sel->cs_num_shaderbufs_in_user_sgprs++;
156 }
157
158 /* Images in user SGPRs. */
159 unsigned non_msaa_images = sel->info.images_declared & ~sel->info.msaa_images_declared;
160
161 for (unsigned i = 0; i < 3 && non_msaa_images & (1 << i); i++) {
162 unsigned num_sgprs = sel->info.image_buffers & (1 << i) ? 4 : 8;
163
164 if (align(user_sgprs, num_sgprs) + num_sgprs > 16)
165 break;
166
167 user_sgprs = align(user_sgprs, num_sgprs);
168 if (i == 0)
169 sel->cs_images_sgpr_index = user_sgprs;
170 user_sgprs += num_sgprs;
171 sel->cs_num_images_in_user_sgprs++;
172 }
173 sel->cs_images_num_sgprs = user_sgprs - sel->cs_images_sgpr_index;
174 assert(user_sgprs <= 16);
175
176 unsigned char ir_sha1_cache_key[20];
177 si_get_ir_cache_key(sel, false, false, ir_sha1_cache_key);
178
179 /* Try to load the shader from the shader cache. */
180 simple_mtx_lock(&sscreen->shader_cache_mutex);
181
182 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
183 simple_mtx_unlock(&sscreen->shader_cache_mutex);
184
185 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
186 si_shader_dump(sscreen, shader, debug, stderr, true);
187
188 if (!si_shader_binary_upload(sscreen, shader, 0))
189 program->shader.compilation_failed = true;
190 } else {
191 simple_mtx_unlock(&sscreen->shader_cache_mutex);
192
193 if (!si_create_shader_variant(sscreen, compiler, &program->shader, debug)) {
194 program->shader.compilation_failed = true;
195 return;
196 }
197
198 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
199
200 shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) /
201 (sscreen->compute_wave_size == 32 ? 8 : 4)) |
202 S_00B848_DX10_CLAMP(1) |
203 S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
204 S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
205 S_00B848_FLOAT_MODE(shader->config.float_mode);
206
207 if (sscreen->info.chip_class < GFX10) {
208 shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
209 }
210
211 shader->config.rsrc2 = S_00B84C_USER_SGPR(user_sgprs) | S_00B84C_SCRATCH_EN(scratch_enabled) |
212 S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
213 S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
214 S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
215 S_00B84C_TG_SIZE_EN(sel->info.uses_subgroup_info) |
216 S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2]
217 ? 2
218 : sel->info.uses_thread_id[1] ? 1 : 0) |
219 S_00B84C_LDS_SIZE(shader->config.lds_size);
220
221 simple_mtx_lock(&sscreen->shader_cache_mutex);
222 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
223 simple_mtx_unlock(&sscreen->shader_cache_mutex);
224 }
225
226 ralloc_free(sel->nir);
227 sel->nir = NULL;
228 }
229
230 static void *si_create_compute_state(struct pipe_context *ctx, const struct pipe_compute_state *cso)
231 {
232 struct si_context *sctx = (struct si_context *)ctx;
233 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
234 struct si_compute *program = CALLOC_STRUCT(si_compute);
235 struct si_shader_selector *sel = &program->sel;
236
237 pipe_reference_init(&sel->base.reference, 1);
238 sel->info.stage = MESA_SHADER_COMPUTE;
239 sel->type = PIPE_SHADER_COMPUTE;
240 sel->screen = sscreen;
241 sel->const_and_shader_buf_descriptors_index =
242 si_const_and_shader_buffer_descriptors_idx(sel->type);
243 sel->sampler_and_images_descriptors_index =
244 si_sampler_and_image_descriptors_idx(sel->type);
245 program->shader.selector = &program->sel;
246 program->ir_type = cso->ir_type;
247 program->local_size = cso->req_local_mem;
248 program->private_size = cso->req_private_mem;
249 program->input_size = cso->req_input_mem;
250
251 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
252 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
253 program->ir_type = PIPE_SHADER_IR_NIR;
254 sel->nir = tgsi_to_nir(cso->prog, ctx->screen, true);
255 } else {
256 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
257 sel->nir = (struct nir_shader *)cso->prog;
258 }
259
260 sel->compiler_ctx_state.debug = sctx->debug;
261 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
262 p_atomic_inc(&sscreen->num_shaders_created);
263
264 si_schedule_initial_compile(sctx, MESA_SHADER_COMPUTE, &sel->ready, &sel->compiler_ctx_state,
265 program, si_create_compute_state_async);
266 } else {
267 const struct pipe_binary_program_header *header;
268 header = cso->prog;
269
270 program->shader.binary.elf_size = header->num_bytes;
271 program->shader.binary.elf_buffer = malloc(header->num_bytes);
272 if (!program->shader.binary.elf_buffer) {
273 FREE(program);
274 return NULL;
275 }
276 memcpy((void *)program->shader.binary.elf_buffer, header->blob, header->num_bytes);
277
278 const amd_kernel_code_t *code_object = si_compute_get_code_object(program, 0);
279 code_object_to_config(code_object, &program->shader.config);
280
281 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
282 if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
283 fprintf(stderr, "LLVM failed to upload shader\n");
284 free((void *)program->shader.binary.elf_buffer);
285 FREE(program);
286 return NULL;
287 }
288 }
289
290 return program;
291 }
292
293 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
294 {
295 struct si_context *sctx = (struct si_context *)ctx;
296 struct si_compute *program = (struct si_compute *)state;
297 struct si_shader_selector *sel = &program->sel;
298
299 sctx->cs_shader_state.program = program;
300 if (!program)
301 return;
302
303 /* Wait because we need active slot usage masks. */
304 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
305 util_queue_fence_wait(&sel->ready);
306
307 si_set_active_descriptors(sctx,
308 SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
309 sel->active_const_and_shader_buffers);
310 si_set_active_descriptors(sctx, SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
311 sel->active_samplers_and_images);
312
313 sctx->compute_shaderbuf_sgprs_dirty = true;
314 sctx->compute_image_sgprs_dirty = true;
315 }
316
317 static void si_set_global_binding(struct pipe_context *ctx, unsigned first, unsigned n,
318 struct pipe_resource **resources, uint32_t **handles)
319 {
320 unsigned i;
321 struct si_context *sctx = (struct si_context *)ctx;
322 struct si_compute *program = sctx->cs_shader_state.program;
323
324 if (first + n > program->max_global_buffers) {
325 unsigned old_max = program->max_global_buffers;
326 program->max_global_buffers = first + n;
327 program->global_buffers = realloc(
328 program->global_buffers, program->max_global_buffers * sizeof(program->global_buffers[0]));
329 if (!program->global_buffers) {
330 fprintf(stderr, "radeonsi: failed to allocate compute global_buffers\n");
331 return;
332 }
333
334 memset(&program->global_buffers[old_max], 0,
335 (program->max_global_buffers - old_max) * sizeof(program->global_buffers[0]));
336 }
337
338 if (!resources) {
339 for (i = 0; i < n; i++) {
340 pipe_resource_reference(&program->global_buffers[first + i], NULL);
341 }
342 return;
343 }
344
345 for (i = 0; i < n; i++) {
346 uint64_t va;
347 uint32_t offset;
348 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
349 va = si_resource(resources[i])->gpu_address;
350 offset = util_le32_to_cpu(*handles[i]);
351 va += offset;
352 va = util_cpu_to_le64(va);
353 memcpy(handles[i], &va, sizeof(va));
354 }
355 }
356
357 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
358 {
359 uint64_t bc_va = sctx->border_color_buffer->gpu_address;
360
361 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
362 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
363 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
364 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
365 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
366
367 if (sctx->chip_class == GFX6) {
368 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
369 * and is now per pipe, so it should be handled in the
370 * kernel if we want to use something other than the default value.
371 *
372 * TODO: This should be:
373 * (number of compute units) * 4 * (waves per simd) - 1
374 */
375 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
376
377 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed)
378 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
379 }
380
381 if (sctx->chip_class >= GFX7) {
382 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
383 radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
384 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
385 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
386
387 /* Disable profiling on compute queues. */
388 if (cs != sctx->gfx_cs || !sctx->screen->info.has_graphics) {
389 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_PERFCOUNT_ENABLE, 0);
390 radeon_set_sh_reg(cs, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, 0);
391 }
392
393 /* Set the pointer to border colors. */
394 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
395 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
396 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
397 }
398
399 /* cs_preamble_state initializes this for the gfx queue, so only do this
400 * if we are on a compute queue.
401 */
402 if (sctx->chip_class >= GFX9 &&
403 (cs != sctx->gfx_cs || !sctx->screen->info.has_graphics)) {
404 radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY,
405 sctx->chip_class >= GFX10 ? 0x20 : 0);
406 }
407
408 if (sctx->chip_class >= GFX10) {
409 radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0);
410 radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0);
411 radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0);
412 radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0);
413 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
414 radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0);
415 }
416 }
417
418 static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_shader *shader,
419 struct ac_shader_config *config)
420 {
421 uint64_t scratch_bo_size, scratch_needed;
422 scratch_bo_size = 0;
423 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
424 if (sctx->compute_scratch_buffer)
425 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
426
427 if (scratch_bo_size < scratch_needed) {
428 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
429
430 sctx->compute_scratch_buffer =
431 si_aligned_buffer_create(&sctx->screen->b, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
432 scratch_needed, sctx->screen->info.pte_fragment_size);
433
434 if (!sctx->compute_scratch_buffer)
435 return false;
436 }
437
438 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
439 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
440
441 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
442 return false;
443
444 si_resource_reference(&shader->scratch_bo, sctx->compute_scratch_buffer);
445 }
446
447 return true;
448 }
449
450 static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute *program,
451 struct si_shader *shader, const amd_kernel_code_t *code_object,
452 unsigned offset)
453 {
454 struct radeon_cmdbuf *cs = sctx->gfx_cs;
455 struct ac_shader_config inline_config = {0};
456 struct ac_shader_config *config;
457 uint64_t shader_va;
458
459 if (sctx->cs_shader_state.emitted_program == program && sctx->cs_shader_state.offset == offset)
460 return true;
461
462 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
463 config = &shader->config;
464 } else {
465 unsigned lds_blocks;
466
467 config = &inline_config;
468 code_object_to_config(code_object, config);
469
470 lds_blocks = config->lds_size;
471 /* XXX: We are over allocating LDS. For GFX6, the shader reports
472 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
473 * allocated in the shader and 4 bytes allocated by the state
474 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
475 */
476 if (sctx->chip_class <= GFX6) {
477 lds_blocks += align(program->local_size, 256) >> 8;
478 } else {
479 lds_blocks += align(program->local_size, 512) >> 9;
480 }
481
482 /* TODO: use si_multiwave_lds_size_workaround */
483 assert(lds_blocks <= 0xFF);
484
485 config->rsrc2 &= C_00B84C_LDS_SIZE;
486 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
487 }
488
489 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
490 return false;
491
492 if (shader->scratch_bo) {
493 COMPUTE_DBG(sctx->screen,
494 "Waves: %u; Scratch per wave: %u bytes; "
495 "Total Scratch: %u bytes\n",
496 sctx->scratch_waves, config->scratch_bytes_per_wave,
497 config->scratch_bytes_per_wave * sctx->scratch_waves);
498
499 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->scratch_bo, RADEON_USAGE_READWRITE,
500 RADEON_PRIO_SCRATCH_BUFFER);
501 }
502
503 /* Prefetch the compute shader to TC L2.
504 *
505 * We should also prefetch graphics shaders if a compute dispatch was
506 * the last command, and the compute shader if a draw call was the last
507 * command. However, that would add more complexity and we're likely
508 * to get a shader state change in that case anyway.
509 */
510 if (sctx->chip_class >= GFX7) {
511 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b, 0, program->shader.bo->b.b.width0);
512 }
513
514 shader_va = shader->bo->gpu_address + offset;
515 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
516 /* Shader code is placed after the amd_kernel_code_t
517 * struct. */
518 shader_va += sizeof(amd_kernel_code_t);
519 }
520
521 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo, RADEON_USAGE_READ,
522 RADEON_PRIO_SHADER_BINARY);
523
524 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
525 radeon_emit(cs, shader_va >> 8);
526 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
527
528 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
529 radeon_emit(cs, config->rsrc1);
530 radeon_emit(cs, config->rsrc2);
531
532 COMPUTE_DBG(sctx->screen,
533 "COMPUTE_PGM_RSRC1: 0x%08x "
534 "COMPUTE_PGM_RSRC2: 0x%08x\n",
535 config->rsrc1, config->rsrc2);
536
537 sctx->max_seen_compute_scratch_bytes_per_wave =
538 MAX2(sctx->max_seen_compute_scratch_bytes_per_wave, config->scratch_bytes_per_wave);
539
540 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
541 S_00B860_WAVES(sctx->scratch_waves) |
542 S_00B860_WAVESIZE(sctx->max_seen_compute_scratch_bytes_per_wave >> 10));
543
544 sctx->cs_shader_state.emitted_program = program;
545 sctx->cs_shader_state.offset = offset;
546 sctx->cs_shader_state.uses_scratch = config->scratch_bytes_per_wave != 0;
547
548 return true;
549 }
550
551 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
552 const amd_kernel_code_t *code_object, unsigned user_sgpr)
553 {
554 struct radeon_cmdbuf *cs = sctx->gfx_cs;
555 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
556
557 unsigned max_private_element_size =
558 AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
559
560 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
561 uint32_t scratch_dword1 =
562 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE(1);
563
564 /* Disable address clamping */
565 uint32_t scratch_dword2 = 0xffffffff;
566 uint32_t scratch_dword3 = S_008F0C_INDEX_STRIDE(3) | S_008F0C_ADD_TID_ENABLE(1);
567
568 if (sctx->chip_class >= GFX9) {
569 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
570 } else {
571 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
572
573 if (sctx->chip_class < GFX8) {
574 /* BUF_DATA_FORMAT is ignored, but it cannot be
575 * BUF_DATA_FORMAT_INVALID. */
576 scratch_dword3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
577 }
578 }
579
580 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 4);
581 radeon_emit(cs, scratch_dword0);
582 radeon_emit(cs, scratch_dword1);
583 radeon_emit(cs, scratch_dword2);
584 radeon_emit(cs, scratch_dword3);
585 }
586
587 static void si_setup_user_sgprs_co_v2(struct si_context *sctx, const amd_kernel_code_t *code_object,
588 const struct pipe_grid_info *info, uint64_t kernel_args_va)
589 {
590 struct si_compute *program = sctx->cs_shader_state.program;
591 struct radeon_cmdbuf *cs = sctx->gfx_cs;
592
593 static const enum amd_code_property_mask_t workgroup_count_masks[] = {
594 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
595 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
596 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z};
597
598 unsigned i, user_sgpr = 0;
599 if (AMD_HSA_BITS_GET(code_object->code_properties,
600 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
601 if (code_object->workitem_private_segment_byte_size > 0) {
602 setup_scratch_rsrc_user_sgprs(sctx, code_object, user_sgpr);
603 }
604 user_sgpr += 4;
605 }
606
607 if (AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
608 struct dispatch_packet dispatch;
609 unsigned dispatch_offset;
610 struct si_resource *dispatch_buf = NULL;
611 uint64_t dispatch_va;
612
613 /* Upload dispatch ptr */
614 memset(&dispatch, 0, sizeof(dispatch));
615
616 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
617 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
618 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
619
620 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
621 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
622 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
623
624 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
625 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
626
627 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
628
629 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch), 256, &dispatch, &dispatch_offset,
630 (struct pipe_resource **)&dispatch_buf);
631
632 if (!dispatch_buf) {
633 fprintf(stderr, "Error: Failed to allocate dispatch "
634 "packet.");
635 }
636 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf, RADEON_USAGE_READ,
637 RADEON_PRIO_CONST_BUFFER);
638
639 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
640
641 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
642 radeon_emit(cs, dispatch_va);
643 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) | S_008F04_STRIDE(0));
644
645 si_resource_reference(&dispatch_buf, NULL);
646 user_sgpr += 2;
647 }
648
649 if (AMD_HSA_BITS_GET(code_object->code_properties,
650 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
651 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
652 radeon_emit(cs, kernel_args_va);
653 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(kernel_args_va >> 32) | S_008F04_STRIDE(0));
654 user_sgpr += 2;
655 }
656
657 for (i = 0; i < 3 && user_sgpr < 16; i++) {
658 if (code_object->code_properties & workgroup_count_masks[i]) {
659 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 1);
660 radeon_emit(cs, info->grid[i]);
661 user_sgpr += 1;
662 }
663 }
664 }
665
666 static bool si_upload_compute_input(struct si_context *sctx, const amd_kernel_code_t *code_object,
667 const struct pipe_grid_info *info)
668 {
669 struct si_compute *program = sctx->cs_shader_state.program;
670 struct si_resource *input_buffer = NULL;
671 uint32_t kernel_args_offset = 0;
672 uint32_t *kernel_args;
673 void *kernel_args_ptr;
674 uint64_t kernel_args_va;
675
676 u_upload_alloc(sctx->b.const_uploader, 0, program->input_size,
677 sctx->screen->info.tcc_cache_line_size, &kernel_args_offset,
678 (struct pipe_resource **)&input_buffer, &kernel_args_ptr);
679
680 if (unlikely(!kernel_args_ptr))
681 return false;
682
683 kernel_args = (uint32_t *)kernel_args_ptr;
684 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
685
686 memcpy(kernel_args, info->input, program->input_size);
687
688 for (unsigned i = 0; i < program->input_size / 4; i++) {
689 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i, kernel_args[i]);
690 }
691
692 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer, RADEON_USAGE_READ,
693 RADEON_PRIO_CONST_BUFFER);
694
695 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
696 si_resource_reference(&input_buffer, NULL);
697 return true;
698 }
699
700 static void si_setup_nir_user_data(struct si_context *sctx, const struct pipe_grid_info *info)
701 {
702 struct si_compute *program = sctx->cs_shader_state.program;
703 struct si_shader_selector *sel = &program->sel;
704 struct radeon_cmdbuf *cs = sctx->gfx_cs;
705 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 + 4 * SI_NUM_RESOURCE_SGPRS;
706 unsigned block_size_reg = grid_size_reg +
707 /* 12 bytes = 3 dwords. */
708 12 * sel->info.uses_grid_size;
709 unsigned cs_user_data_reg = block_size_reg + 12 * program->reads_variable_block_size;
710
711 if (info->indirect) {
712 if (sel->info.uses_grid_size) {
713 for (unsigned i = 0; i < 3; ++i) {
714 si_cp_copy_data(sctx, sctx->gfx_cs, COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
715 COPY_DATA_SRC_MEM, si_resource(info->indirect),
716 info->indirect_offset + 4 * i);
717 }
718 }
719 } else {
720 if (sel->info.uses_grid_size) {
721 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
722 radeon_emit(cs, info->grid[0]);
723 radeon_emit(cs, info->grid[1]);
724 radeon_emit(cs, info->grid[2]);
725 }
726 if (program->reads_variable_block_size) {
727 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
728 radeon_emit(cs, info->block[0]);
729 radeon_emit(cs, info->block[1]);
730 radeon_emit(cs, info->block[2]);
731 }
732 }
733
734 if (program->num_cs_user_data_dwords) {
735 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
736 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
737 }
738 }
739
740 static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_grid_info *info)
741 {
742 struct si_screen *sscreen = sctx->screen;
743 struct radeon_cmdbuf *cs = sctx->gfx_cs;
744 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
745 unsigned threads_per_threadgroup = info->block[0] * info->block[1] * info->block[2];
746 unsigned waves_per_threadgroup =
747 DIV_ROUND_UP(threads_per_threadgroup, sscreen->compute_wave_size);
748 unsigned threadgroups_per_cu = 1;
749
750 if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1)
751 threadgroups_per_cu = 2;
752
753 radeon_set_sh_reg(
754 cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
755 ac_get_compute_resource_limits(&sscreen->info, waves_per_threadgroup,
756 sctx->cs_max_waves_per_sh, threadgroups_per_cu));
757
758 unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) | S_00B800_FORCE_START_AT_000(1) |
759 /* If the KMD allows it (there is a KMD hw register for it),
760 * allow launching waves out-of-order. (same as Vulkan) */
761 S_00B800_ORDER_MODE(sctx->chip_class >= GFX7) |
762 S_00B800_CS_W32_EN(sscreen->compute_wave_size == 32);
763
764 const uint *last_block = info->last_block;
765 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
766
767 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
768
769 if (partial_block_en) {
770 unsigned partial[3];
771
772 /* If no partial_block, these should be an entire block size, not 0. */
773 partial[0] = last_block[0] ? last_block[0] : info->block[0];
774 partial[1] = last_block[1] ? last_block[1] : info->block[1];
775 partial[2] = last_block[2] ? last_block[2] : info->block[2];
776
777 radeon_emit(
778 cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) | S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
779 radeon_emit(
780 cs, S_00B820_NUM_THREAD_FULL(info->block[1]) | S_00B820_NUM_THREAD_PARTIAL(partial[1]));
781 radeon_emit(
782 cs, S_00B824_NUM_THREAD_FULL(info->block[2]) | S_00B824_NUM_THREAD_PARTIAL(partial[2]));
783
784 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
785 } else {
786 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
787 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
788 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
789 }
790
791 if (info->indirect) {
792 uint64_t base_va = si_resource(info->indirect)->gpu_address;
793
794 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(info->indirect), RADEON_USAGE_READ,
795 RADEON_PRIO_DRAW_INDIRECT);
796
797 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) | PKT3_SHADER_TYPE_S(1));
798 radeon_emit(cs, 1);
799 radeon_emit(cs, base_va);
800 radeon_emit(cs, base_va >> 32);
801
802 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
803 radeon_emit(cs, info->indirect_offset);
804 radeon_emit(cs, dispatch_initiator);
805 } else {
806 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
807 radeon_emit(cs, info->grid[0]);
808 radeon_emit(cs, info->grid[1]);
809 radeon_emit(cs, info->grid[2]);
810 radeon_emit(cs, dispatch_initiator);
811 }
812 }
813
814 static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
815 {
816 struct si_context *sctx = (struct si_context *)ctx;
817 struct si_compute *program = sctx->cs_shader_state.program;
818 const amd_kernel_code_t *code_object = si_compute_get_code_object(program, info->pc);
819 int i;
820 /* HW bug workaround when CS threadgroups > 256 threads and async
821 * compute isn't used, i.e. only one compute job can run at a time.
822 * If async compute is possible, the threadgroup size must be limited
823 * to 256 threads on all queues to avoid the bug.
824 * Only GFX6 and certain GFX7 chips are affected.
825 */
826 bool cs_regalloc_hang =
827 (sctx->chip_class == GFX6 || sctx->family == CHIP_BONAIRE || sctx->family == CHIP_KABINI) &&
828 info->block[0] * info->block[1] * info->block[2] > 256;
829
830 if (cs_regalloc_hang)
831 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
832
833 if (program->ir_type != PIPE_SHADER_IR_NATIVE && program->shader.compilation_failed)
834 return;
835
836 if (sctx->has_graphics) {
837 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
838 si_update_fb_dirtiness_after_rendering(sctx);
839 sctx->last_num_draw_calls = sctx->num_draw_calls;
840 }
841
842 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
843 }
844
845 /* Add buffer sizes for memory checking in need_cs_space. */
846 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
847 /* TODO: add the scratch buffer */
848
849 if (info->indirect) {
850 si_context_add_resource_size(sctx, info->indirect);
851
852 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
853 if (sctx->chip_class <= GFX8 && si_resource(info->indirect)->TC_L2_dirty) {
854 sctx->flags |= SI_CONTEXT_WB_L2;
855 si_resource(info->indirect)->TC_L2_dirty = false;
856 }
857 }
858
859 si_need_gfx_cs_space(sctx);
860
861 /* If we're using a secure context, determine if cs must be secure or not */
862 if (unlikely(sctx->ws->ws_is_secure(sctx->ws))) {
863 bool secure = si_compute_resources_check_encrypted(sctx);
864 if (secure != sctx->ws->cs_is_secure(sctx->gfx_cs)) {
865 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
866 sctx->ws->cs_set_secure(sctx->gfx_cs, secure);
867 }
868 }
869
870 if (sctx->bo_list_add_all_compute_resources)
871 si_compute_resources_add_all_to_bo_list(sctx);
872
873 if (!sctx->cs_shader_state.initialized) {
874 si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
875
876 sctx->cs_shader_state.emitted_program = NULL;
877 sctx->cs_shader_state.initialized = true;
878 }
879
880 if (sctx->flags)
881 sctx->emit_cache_flush(sctx);
882
883 if (!si_switch_compute_shader(sctx, program, &program->shader, code_object, info->pc))
884 return;
885
886 si_upload_compute_shader_descriptors(sctx);
887 si_emit_compute_shader_pointers(sctx);
888
889 if (sctx->has_graphics && si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
890 sctx->atoms.s.render_cond.emit(sctx);
891 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
892 }
893
894 if (program->ir_type == PIPE_SHADER_IR_NATIVE &&
895 unlikely(!si_upload_compute_input(sctx, code_object, info)))
896 return;
897
898 /* Global buffers */
899 for (i = 0; i < program->max_global_buffers; i++) {
900 struct si_resource *buffer = si_resource(program->global_buffers[i]);
901 if (!buffer) {
902 continue;
903 }
904 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer, RADEON_USAGE_READWRITE,
905 RADEON_PRIO_COMPUTE_GLOBAL);
906 }
907
908 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
909 si_setup_nir_user_data(sctx, info);
910
911 si_emit_dispatch_packets(sctx, info);
912
913 if (unlikely(sctx->current_saved_cs)) {
914 si_trace_emit(sctx);
915 si_log_compute_state(sctx, sctx->log);
916 }
917
918 sctx->compute_is_busy = true;
919 sctx->num_compute_calls++;
920 if (sctx->cs_shader_state.uses_scratch)
921 sctx->num_spill_compute_calls++;
922
923 if (cs_regalloc_hang)
924 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
925 }
926
927 void si_destroy_compute(struct si_compute *program)
928 {
929 struct si_shader_selector *sel = &program->sel;
930
931 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
932 util_queue_drop_job(&sel->screen->shader_compiler_queue, &sel->ready);
933 util_queue_fence_destroy(&sel->ready);
934 }
935
936 for (unsigned i = 0; i < program->max_global_buffers; i++)
937 pipe_resource_reference(&program->global_buffers[i], NULL);
938 FREE(program->global_buffers);
939
940 si_shader_destroy(&program->shader);
941 ralloc_free(program->sel.nir);
942 FREE(program);
943 }
944
945 static void si_delete_compute_state(struct pipe_context *ctx, void *state)
946 {
947 struct si_compute *program = (struct si_compute *)state;
948 struct si_context *sctx = (struct si_context *)ctx;
949
950 if (!state)
951 return;
952
953 if (program == sctx->cs_shader_state.program)
954 sctx->cs_shader_state.program = NULL;
955
956 if (program == sctx->cs_shader_state.emitted_program)
957 sctx->cs_shader_state.emitted_program = NULL;
958
959 si_compute_reference(&program, NULL);
960 }
961
962 static void si_set_compute_resources(struct pipe_context *ctx_, unsigned start, unsigned count,
963 struct pipe_surface **surfaces)
964 {
965 }
966
967 void si_init_compute_functions(struct si_context *sctx)
968 {
969 sctx->b.create_compute_state = si_create_compute_state;
970 sctx->b.delete_compute_state = si_delete_compute_state;
971 sctx->b.bind_compute_state = si_bind_compute_state;
972 sctx->b.set_compute_resources = si_set_compute_resources;
973 sctx->b.set_global_binding = si_set_global_binding;
974 sctx->b.launch_grid = si_launch_grid;
975 }