src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include "si_compute.h"
  27
  28 #include "ac_rtld.h"
  29 #include "amd_kernel_code_t.h"
  30 #include "nir/tgsi_to_nir.h"
  31 #include "si_build_pm4.h"
  32 #include "util/u_async_debug.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_upload_mgr.h"
  35
  36 #define COMPUTE_DBG(sscreen, fmt, args...)                                                         \
  37    do {                                                                                            \
  38       if ((sscreen->debug_flags & DBG(COMPUTE)))                                                   \
  39          fprintf(stderr, fmt, ##args);                                                             \
  40    } while (0);
  41
  42 struct dispatch_packet {
  43    uint16_t header;
  44    uint16_t setup;
  45    uint16_t workgroup_size_x;
  46    uint16_t workgroup_size_y;
  47    uint16_t workgroup_size_z;
  48    uint16_t reserved0;
  49    uint32_t grid_size_x;
  50    uint32_t grid_size_y;
  51    uint32_t grid_size_z;
  52    uint32_t private_segment_size;
  53    uint32_t group_segment_size;
  54    uint64_t kernel_object;
  55    uint64_t kernarg_address;
  56    uint64_t reserved2;
  57 };
  58
  59 static const amd_kernel_code_t *si_compute_get_code_object(const struct si_compute *program,
  60                                                            uint64_t symbol_offset)
  61 {
  62    const struct si_shader_selector *sel = &program->sel;
  63
  64    if (program->ir_type != PIPE_SHADER_IR_NATIVE)
  65       return NULL;
  66
  67    struct ac_rtld_binary rtld;
  68    if (!ac_rtld_open(&rtld,
  69                      (struct ac_rtld_open_info){.info = &sel->screen->info,
  70                                                 .shader_type = MESA_SHADER_COMPUTE,
  71                                                 .wave_size = sel->screen->compute_wave_size,
  72                                                 .num_parts = 1,
  73                                                 .elf_ptrs = &program->shader.binary.elf_buffer,
  74                                                 .elf_sizes = &program->shader.binary.elf_size}))
  75       return NULL;
  76
  77    const amd_kernel_code_t *result = NULL;
  78    const char *text;
  79    size_t size;
  80    if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
  81       goto out;
  82
  83    if (symbol_offset + sizeof(amd_kernel_code_t) > size)
  84       goto out;
  85
  86    result = (const amd_kernel_code_t *)(text + symbol_offset);
  87
  88 out:
  89    ac_rtld_close(&rtld);
  90    return result;
  91 }
  92
  93 static void code_object_to_config(const amd_kernel_code_t *code_object,
  94                                   struct ac_shader_config *out_config)
  95 {
  96
  97    uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
  98    uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
  99    out_config->num_sgprs = code_object->wavefront_sgpr_count;
 100    out_config->num_vgprs = code_object->workitem_vgpr_count;
 101    out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
 102    out_config->rsrc1 = rsrc1;
 103    out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
 104    out_config->rsrc2 = rsrc2;
 105    out_config->scratch_bytes_per_wave =
 106       align(code_object->workitem_private_segment_byte_size * 64, 1024);
 107 }
 108
 109 /* Asynchronous compute shader compilation. */
 110 static void si_create_compute_state_async(void *job, int thread_index)
 111 {
 112    struct si_compute *program = (struct si_compute *)job;
 113    struct si_shader_selector *sel = &program->sel;
 114    struct si_shader *shader = &program->shader;
 115    struct ac_llvm_compiler *compiler;
 116    struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
 117    struct si_screen *sscreen = sel->screen;
 118
 119    assert(!debug->debug_message || debug->async);
 120    assert(thread_index >= 0);
 121    assert(thread_index < ARRAY_SIZE(sscreen->compiler));
 122    compiler = &sscreen->compiler[thread_index];
 123
 124    if (!compiler->passes)
 125       si_init_compiler(sscreen, compiler);
 126
 127    assert(program->ir_type == PIPE_SHADER_IR_NIR);
 128    si_nir_scan_shader(sel->nir, &sel->info);
 129
 130    sel->info.base.cs.shared_size = program->local_size;
 131    si_get_active_slot_masks(&sel->info, &sel->active_const_and_shader_buffers,
 132                             &sel->active_samplers_and_images);
 133
 134    program->shader.is_monolithic = true;
 135    program->reads_variable_block_size =
 136       sel->info.uses_block_size && sel->info.base.cs.local_size[0] == 0;
 137    program->num_cs_user_data_dwords =
 138       sel->info.base.cs.user_data_components_amd;
 139
 140    unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS + (sel->info.uses_grid_size ? 3 : 0) +
 141                          (program->reads_variable_block_size ? 3 : 0) +
 142                          program->num_cs_user_data_dwords;
 143
 144    /* Fast path for compute shaders - some descriptors passed via user SGPRs. */
 145    /* Shader buffers in user SGPRs. */
 146    for (unsigned i = 0; i < MIN2(3, sel->info.base.num_ssbos) && user_sgprs <= 12; i++) {
 147       user_sgprs = align(user_sgprs, 4);
 148       if (i == 0)
 149          sel->cs_shaderbufs_sgpr_index = user_sgprs;
 150       user_sgprs += 4;
 151       sel->cs_num_shaderbufs_in_user_sgprs++;
 152    }
 153
 154    /* Images in user SGPRs. */
 155    unsigned non_msaa_images = u_bit_consecutive(0, sel->info.base.num_images) &
 156                               ~sel->info.base.msaa_images;
 157
 158    for (unsigned i = 0; i < 3 && non_msaa_images & (1 << i); i++) {
 159       unsigned num_sgprs = sel->info.base.image_buffers & (1 << i) ? 4 : 8;
 160
 161       if (align(user_sgprs, num_sgprs) + num_sgprs > 16)
 162          break;
 163
 164       user_sgprs = align(user_sgprs, num_sgprs);
 165       if (i == 0)
 166          sel->cs_images_sgpr_index = user_sgprs;
 167       user_sgprs += num_sgprs;
 168       sel->cs_num_images_in_user_sgprs++;
 169    }
 170    sel->cs_images_num_sgprs = user_sgprs - sel->cs_images_sgpr_index;
 171    assert(user_sgprs <= 16);
 172
 173    unsigned char ir_sha1_cache_key[20];
 174    si_get_ir_cache_key(sel, false, false, ir_sha1_cache_key);
 175
 176    /* Try to load the shader from the shader cache. */
 177    simple_mtx_lock(&sscreen->shader_cache_mutex);
 178
 179    if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
 180       simple_mtx_unlock(&sscreen->shader_cache_mutex);
 181
 182       si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
 183       si_shader_dump(sscreen, shader, debug, stderr, true);
 184
 185       if (!si_shader_binary_upload(sscreen, shader, 0))
 186          program->shader.compilation_failed = true;
 187    } else {
 188       simple_mtx_unlock(&sscreen->shader_cache_mutex);
 189
 190       if (!si_create_shader_variant(sscreen, compiler, &program->shader, debug)) {
 191          program->shader.compilation_failed = true;
 192          return;
 193       }
 194
 195       bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
 196
 197       shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) /
 198                                             (sscreen->compute_wave_size == 32 ? 8 : 4)) |
 199                              S_00B848_DX10_CLAMP(1) |
 200                              S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
 201                              S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
 202                              S_00B848_FLOAT_MODE(shader->config.float_mode);
 203
 204       if (sscreen->info.chip_class < GFX10) {
 205          shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
 206       }
 207
 208       shader->config.rsrc2 = S_00B84C_USER_SGPR(user_sgprs) | S_00B84C_SCRATCH_EN(scratch_enabled) |
 209                              S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
 210                              S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
 211                              S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
 212                              S_00B84C_TG_SIZE_EN(sel->info.uses_subgroup_info) |
 213                              S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2]
 214                                                         ? 2
 215                                                         : sel->info.uses_thread_id[1] ? 1 : 0) |
 216                              S_00B84C_LDS_SIZE(shader->config.lds_size);
 217
 218       simple_mtx_lock(&sscreen->shader_cache_mutex);
 219       si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
 220       simple_mtx_unlock(&sscreen->shader_cache_mutex);
 221    }
 222
 223    ralloc_free(sel->nir);
 224    sel->nir = NULL;
 225 }
 226
 227 static void *si_create_compute_state(struct pipe_context *ctx, const struct pipe_compute_state *cso)
 228 {
 229    struct si_context *sctx = (struct si_context *)ctx;
 230    struct si_screen *sscreen = (struct si_screen *)ctx->screen;
 231    struct si_compute *program = CALLOC_STRUCT(si_compute);
 232    struct si_shader_selector *sel = &program->sel;
 233
 234    pipe_reference_init(&sel->base.reference, 1);
 235    sel->info.stage = MESA_SHADER_COMPUTE;
 236    sel->screen = sscreen;
 237    sel->const_and_shader_buf_descriptors_index =
 238       si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_COMPUTE);
 239    sel->sampler_and_images_descriptors_index =
 240       si_sampler_and_image_descriptors_idx(PIPE_SHADER_COMPUTE);
 241    program->shader.selector = &program->sel;
 242    program->ir_type = cso->ir_type;
 243    program->local_size = cso->req_local_mem;
 244    program->private_size = cso->req_private_mem;
 245    program->input_size = cso->req_input_mem;
 246
 247    if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
 248       if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
 249          program->ir_type = PIPE_SHADER_IR_NIR;
 250          sel->nir = tgsi_to_nir(cso->prog, ctx->screen, true);
 251       } else {
 252          assert(cso->ir_type == PIPE_SHADER_IR_NIR);
 253          sel->nir = (struct nir_shader *)cso->prog;
 254       }
 255
 256       sel->compiler_ctx_state.debug = sctx->debug;
 257       sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
 258       p_atomic_inc(&sscreen->num_shaders_created);
 259
 260       si_schedule_initial_compile(sctx, MESA_SHADER_COMPUTE, &sel->ready, &sel->compiler_ctx_state,
 261                                   program, si_create_compute_state_async);
 262    } else {
 263       const struct pipe_binary_program_header *header;
 264       header = cso->prog;
 265
 266       program->shader.binary.elf_size = header->num_bytes;
 267       program->shader.binary.elf_buffer = malloc(header->num_bytes);
 268       if (!program->shader.binary.elf_buffer) {
 269          FREE(program);
 270          return NULL;
 271       }
 272       memcpy((void *)program->shader.binary.elf_buffer, header->blob, header->num_bytes);
 273
 274       const amd_kernel_code_t *code_object = si_compute_get_code_object(program, 0);
 275       code_object_to_config(code_object, &program->shader.config);
 276
 277       si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
 278       if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
 279          fprintf(stderr, "LLVM failed to upload shader\n");
 280          free((void *)program->shader.binary.elf_buffer);
 281          FREE(program);
 282          return NULL;
 283       }
 284    }
 285
 286    return program;
 287 }
 288
 289 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 290 {
 291    struct si_context *sctx = (struct si_context *)ctx;
 292    struct si_compute *program = (struct si_compute *)state;
 293    struct si_shader_selector *sel = &program->sel;
 294
 295    sctx->cs_shader_state.program = program;
 296    if (!program)
 297       return;
 298
 299    /* Wait because we need active slot usage masks. */
 300    if (program->ir_type != PIPE_SHADER_IR_NATIVE)
 301       util_queue_fence_wait(&sel->ready);
 302
 303    si_set_active_descriptors(sctx,
 304                              SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
 305                              sel->active_const_and_shader_buffers);
 306    si_set_active_descriptors(sctx, SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
 307                              sel->active_samplers_and_images);
 308
 309    sctx->compute_shaderbuf_sgprs_dirty = true;
 310    sctx->compute_image_sgprs_dirty = true;
 311 }
 312
 313 static void si_set_global_binding(struct pipe_context *ctx, unsigned first, unsigned n,
 314                                   struct pipe_resource **resources, uint32_t **handles)
 315 {
 316    unsigned i;
 317    struct si_context *sctx = (struct si_context *)ctx;
 318    struct si_compute *program = sctx->cs_shader_state.program;
 319
 320    if (first + n > program->max_global_buffers) {
 321       unsigned old_max = program->max_global_buffers;
 322       program->max_global_buffers = first + n;
 323       program->global_buffers = realloc(
 324          program->global_buffers, program->max_global_buffers * sizeof(program->global_buffers[0]));
 325       if (!program->global_buffers) {
 326          fprintf(stderr, "radeonsi: failed to allocate compute global_buffers\n");
 327          return;
 328       }
 329
 330       memset(&program->global_buffers[old_max], 0,
 331              (program->max_global_buffers - old_max) * sizeof(program->global_buffers[0]));
 332    }
 333
 334    if (!resources) {
 335       for (i = 0; i < n; i++) {
 336          pipe_resource_reference(&program->global_buffers[first + i], NULL);
 337       }
 338       return;
 339    }
 340
 341    for (i = 0; i < n; i++) {
 342       uint64_t va;
 343       uint32_t offset;
 344       pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
 345       va = si_resource(resources[i])->gpu_address;
 346       offset = util_le32_to_cpu(*handles[i]);
 347       va += offset;
 348       va = util_cpu_to_le64(va);
 349       memcpy(handles[i], &va, sizeof(va));
 350    }
 351 }
 352
 353 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
 354 {
 355    uint64_t bc_va = sctx->border_color_buffer->gpu_address;
 356
 357    radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
 358    /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
 359     * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
 360    radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 361    radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 362
 363    if (sctx->chip_class == GFX6) {
 364       /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 365        * and is now per pipe, so it should be handled in the
 366        * kernel if we want to use something other than the default value.
 367        *
 368        * TODO: This should be:
 369        * (number of compute units) * 4 * (waves per simd) - 1
 370        */
 371       radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
 372
 373       if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed)
 374          radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
 375    }
 376
 377    if (sctx->chip_class >= GFX7) {
 378       /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
 379       radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
 380       radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 381       radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 382
 383       /* Disable profiling on compute queues. */
 384       if (cs != sctx->gfx_cs || !sctx->screen->info.has_graphics) {
 385          radeon_set_sh_reg(cs, R_00B82C_COMPUTE_PERFCOUNT_ENABLE, 0);
 386          radeon_set_sh_reg(cs, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, 0);
 387       }
 388
 389       /* Set the pointer to border colors. */
 390       radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
 391       radeon_emit(cs, bc_va >> 8);                    /* R_030E00_TA_CS_BC_BASE_ADDR */
 392       radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
 393    }
 394
 395    /* cs_preamble_state initializes this for the gfx queue, so only do this
 396     * if we are on a compute queue.
 397     */
 398    if (sctx->chip_class >= GFX9 &&
 399        (cs != sctx->gfx_cs || !sctx->screen->info.has_graphics)) {
 400       radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY,
 401                              sctx->chip_class >= GFX10 ? 0x20 : 0);
 402    }
 403
 404    if (sctx->chip_class >= GFX10) {
 405       radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0);
 406       radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0);
 407       radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0);
 408       radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0);
 409       radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
 410       radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0);
 411    }
 412 }
 413
 414 static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_shader *shader,
 415                                             struct ac_shader_config *config)
 416 {
 417    uint64_t scratch_bo_size, scratch_needed;
 418    scratch_bo_size = 0;
 419    scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
 420    if (sctx->compute_scratch_buffer)
 421       scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
 422
 423    if (scratch_bo_size < scratch_needed) {
 424       si_resource_reference(&sctx->compute_scratch_buffer, NULL);
 425
 426       sctx->compute_scratch_buffer =
 427          si_aligned_buffer_create(&sctx->screen->b, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
 428                                   scratch_needed, sctx->screen->info.pte_fragment_size);
 429
 430       if (!sctx->compute_scratch_buffer)
 431          return false;
 432    }
 433
 434    if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
 435       uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 436
 437       if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
 438          return false;
 439
 440       si_resource_reference(&shader->scratch_bo, sctx->compute_scratch_buffer);
 441    }
 442
 443    return true;
 444 }
 445
 446 static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute *program,
 447                                      struct si_shader *shader, const amd_kernel_code_t *code_object,
 448                                      unsigned offset)
 449 {
 450    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 451    struct ac_shader_config inline_config = {0};
 452    struct ac_shader_config *config;
 453    uint64_t shader_va;
 454
 455    if (sctx->cs_shader_state.emitted_program == program && sctx->cs_shader_state.offset == offset)
 456       return true;
 457
 458    if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
 459       config = &shader->config;
 460    } else {
 461       unsigned lds_blocks;
 462
 463       config = &inline_config;
 464       code_object_to_config(code_object, config);
 465
 466       lds_blocks = config->lds_size;
 467       /* XXX: We are over allocating LDS.  For GFX6, the shader reports
 468        * LDS in blocks of 256 bytes, so if there are 4 bytes lds
 469        * allocated in the shader and 4 bytes allocated by the state
 470        * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
 471        */
 472       if (sctx->chip_class <= GFX6) {
 473          lds_blocks += align(program->local_size, 256) >> 8;
 474       } else {
 475          lds_blocks += align(program->local_size, 512) >> 9;
 476       }
 477
 478       /* TODO: use si_multiwave_lds_size_workaround */
 479       assert(lds_blocks <= 0xFF);
 480
 481       config->rsrc2 &= C_00B84C_LDS_SIZE;
 482       config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
 483    }
 484
 485    if (!si_setup_compute_scratch_buffer(sctx, shader, config))
 486       return false;
 487
 488    if (shader->scratch_bo) {
 489       COMPUTE_DBG(sctx->screen,
 490                   "Waves: %u; Scratch per wave: %u bytes; "
 491                   "Total Scratch: %u bytes\n",
 492                   sctx->scratch_waves, config->scratch_bytes_per_wave,
 493                   config->scratch_bytes_per_wave * sctx->scratch_waves);
 494
 495       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->scratch_bo, RADEON_USAGE_READWRITE,
 496                                 RADEON_PRIO_SCRATCH_BUFFER);
 497    }
 498
 499    /* Prefetch the compute shader to TC L2.
 500     *
 501     * We should also prefetch graphics shaders if a compute dispatch was
 502     * the last command, and the compute shader if a draw call was the last
 503     * command. However, that would add more complexity and we're likely
 504     * to get a shader state change in that case anyway.
 505     */
 506    if (sctx->chip_class >= GFX7) {
 507       cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b, 0, program->shader.bo->b.b.width0);
 508    }
 509
 510    shader_va = shader->bo->gpu_address + offset;
 511    if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
 512       /* Shader code is placed after the amd_kernel_code_t
 513        * struct. */
 514       shader_va += sizeof(amd_kernel_code_t);
 515    }
 516
 517    radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo, RADEON_USAGE_READ,
 518                              RADEON_PRIO_SHADER_BINARY);
 519
 520    radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
 521    radeon_emit(cs, shader_va >> 8);
 522    radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
 523
 524    radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
 525    radeon_emit(cs, config->rsrc1);
 526    radeon_emit(cs, config->rsrc2);
 527
 528    COMPUTE_DBG(sctx->screen,
 529                "COMPUTE_PGM_RSRC1: 0x%08x "
 530                "COMPUTE_PGM_RSRC2: 0x%08x\n",
 531                config->rsrc1, config->rsrc2);
 532
 533    sctx->max_seen_compute_scratch_bytes_per_wave =
 534       MAX2(sctx->max_seen_compute_scratch_bytes_per_wave, config->scratch_bytes_per_wave);
 535
 536    radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
 537                      S_00B860_WAVES(sctx->scratch_waves) |
 538                         S_00B860_WAVESIZE(sctx->max_seen_compute_scratch_bytes_per_wave >> 10));
 539
 540    sctx->cs_shader_state.emitted_program = program;
 541    sctx->cs_shader_state.offset = offset;
 542    sctx->cs_shader_state.uses_scratch = config->scratch_bytes_per_wave != 0;
 543
 544    return true;
 545 }
 546
 547 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
 548                                           const amd_kernel_code_t *code_object, unsigned user_sgpr)
 549 {
 550    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 551    uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 552
 553    unsigned max_private_element_size =
 554       AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
 555
 556    uint32_t scratch_dword0 = scratch_va & 0xffffffff;
 557    uint32_t scratch_dword1 =
 558       S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE(1);
 559
 560    /* Disable address clamping */
 561    uint32_t scratch_dword2 = 0xffffffff;
 562    uint32_t scratch_dword3 = S_008F0C_INDEX_STRIDE(3) | S_008F0C_ADD_TID_ENABLE(1);
 563
 564    if (sctx->chip_class >= GFX9) {
 565       assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
 566    } else {
 567       scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
 568
 569       if (sctx->chip_class < GFX8) {
 570          /* BUF_DATA_FORMAT is ignored, but it cannot be
 571           * BUF_DATA_FORMAT_INVALID. */
 572          scratch_dword3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
 573       }
 574    }
 575
 576    radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 4);
 577    radeon_emit(cs, scratch_dword0);
 578    radeon_emit(cs, scratch_dword1);
 579    radeon_emit(cs, scratch_dword2);
 580    radeon_emit(cs, scratch_dword3);
 581 }
 582
 583 static void si_setup_user_sgprs_co_v2(struct si_context *sctx, const amd_kernel_code_t *code_object,
 584                                       const struct pipe_grid_info *info, uint64_t kernel_args_va)
 585 {
 586    struct si_compute *program = sctx->cs_shader_state.program;
 587    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 588
 589    static const enum amd_code_property_mask_t workgroup_count_masks[] = {
 590       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
 591       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
 592       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z};
 593
 594    unsigned i, user_sgpr = 0;
 595    if (AMD_HSA_BITS_GET(code_object->code_properties,
 596                         AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
 597       if (code_object->workitem_private_segment_byte_size > 0) {
 598          setup_scratch_rsrc_user_sgprs(sctx, code_object, user_sgpr);
 599       }
 600       user_sgpr += 4;
 601    }
 602
 603    if (AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
 604       struct dispatch_packet dispatch;
 605       unsigned dispatch_offset;
 606       struct si_resource *dispatch_buf = NULL;
 607       uint64_t dispatch_va;
 608
 609       /* Upload dispatch ptr */
 610       memset(&dispatch, 0, sizeof(dispatch));
 611
 612       dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
 613       dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
 614       dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
 615
 616       dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
 617       dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
 618       dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
 619
 620       dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
 621       dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
 622
 623       dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
 624
 625       u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch), 256, &dispatch, &dispatch_offset,
 626                     (struct pipe_resource **)&dispatch_buf);
 627
 628       if (!dispatch_buf) {
 629          fprintf(stderr, "Error: Failed to allocate dispatch "
 630                          "packet.");
 631       }
 632       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf, RADEON_USAGE_READ,
 633                                 RADEON_PRIO_CONST_BUFFER);
 634
 635       dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
 636
 637       radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
 638       radeon_emit(cs, dispatch_va);
 639       radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) | S_008F04_STRIDE(0));
 640
 641       si_resource_reference(&dispatch_buf, NULL);
 642       user_sgpr += 2;
 643    }
 644
 645    if (AMD_HSA_BITS_GET(code_object->code_properties,
 646                         AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
 647       radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
 648       radeon_emit(cs, kernel_args_va);
 649       radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(kernel_args_va >> 32) | S_008F04_STRIDE(0));
 650       user_sgpr += 2;
 651    }
 652
 653    for (i = 0; i < 3 && user_sgpr < 16; i++) {
 654       if (code_object->code_properties & workgroup_count_masks[i]) {
 655          radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 1);
 656          radeon_emit(cs, info->grid[i]);
 657          user_sgpr += 1;
 658       }
 659    }
 660 }
 661
 662 static bool si_upload_compute_input(struct si_context *sctx, const amd_kernel_code_t *code_object,
 663                                     const struct pipe_grid_info *info)
 664 {
 665    struct si_compute *program = sctx->cs_shader_state.program;
 666    struct si_resource *input_buffer = NULL;
 667    uint32_t kernel_args_offset = 0;
 668    uint32_t *kernel_args;
 669    void *kernel_args_ptr;
 670    uint64_t kernel_args_va;
 671
 672    u_upload_alloc(sctx->b.const_uploader, 0, program->input_size,
 673                   sctx->screen->info.tcc_cache_line_size, &kernel_args_offset,
 674                   (struct pipe_resource **)&input_buffer, &kernel_args_ptr);
 675
 676    if (unlikely(!kernel_args_ptr))
 677       return false;
 678
 679    kernel_args = (uint32_t *)kernel_args_ptr;
 680    kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
 681
 682    memcpy(kernel_args, info->input, program->input_size);
 683
 684    for (unsigned i = 0; i < program->input_size / 4; i++) {
 685       COMPUTE_DBG(sctx->screen, "input %u : %u\n", i, kernel_args[i]);
 686    }
 687
 688    radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer, RADEON_USAGE_READ,
 689                              RADEON_PRIO_CONST_BUFFER);
 690
 691    si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
 692    si_resource_reference(&input_buffer, NULL);
 693    return true;
 694 }
 695
 696 static void si_setup_nir_user_data(struct si_context *sctx, const struct pipe_grid_info *info)
 697 {
 698    struct si_compute *program = sctx->cs_shader_state.program;
 699    struct si_shader_selector *sel = &program->sel;
 700    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 701    unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 + 4 * SI_NUM_RESOURCE_SGPRS;
 702    unsigned block_size_reg = grid_size_reg +
 703                              /* 12 bytes = 3 dwords. */
 704                              12 * sel->info.uses_grid_size;
 705    unsigned cs_user_data_reg = block_size_reg + 12 * program->reads_variable_block_size;
 706
 707    if (info->indirect) {
 708       if (sel->info.uses_grid_size) {
 709          for (unsigned i = 0; i < 3; ++i) {
 710             si_cp_copy_data(sctx, sctx->gfx_cs, COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
 711                             COPY_DATA_SRC_MEM, si_resource(info->indirect),
 712                             info->indirect_offset + 4 * i);
 713          }
 714       }
 715    } else {
 716       if (sel->info.uses_grid_size) {
 717          radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
 718          radeon_emit(cs, info->grid[0]);
 719          radeon_emit(cs, info->grid[1]);
 720          radeon_emit(cs, info->grid[2]);
 721       }
 722       if (program->reads_variable_block_size) {
 723          radeon_set_sh_reg_seq(cs, block_size_reg, 3);
 724          radeon_emit(cs, info->block[0]);
 725          radeon_emit(cs, info->block[1]);
 726          radeon_emit(cs, info->block[2]);
 727       }
 728    }
 729
 730    if (program->num_cs_user_data_dwords) {
 731       radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
 732       radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
 733    }
 734 }
 735
 736 static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_grid_info *info)
 737 {
 738    struct si_screen *sscreen = sctx->screen;
 739    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 740    bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
 741    unsigned threads_per_threadgroup = info->block[0] * info->block[1] * info->block[2];
 742    unsigned waves_per_threadgroup =
 743       DIV_ROUND_UP(threads_per_threadgroup, sscreen->compute_wave_size);
 744    unsigned threadgroups_per_cu = 1;
 745
 746    if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1)
 747       threadgroups_per_cu = 2;
 748
 749    radeon_set_sh_reg(
 750       cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
 751       ac_get_compute_resource_limits(&sscreen->info, waves_per_threadgroup,
 752                                      sctx->cs_max_waves_per_sh, threadgroups_per_cu));
 753
 754    unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) | S_00B800_FORCE_START_AT_000(1) |
 755                                  /* If the KMD allows it (there is a KMD hw register for it),
 756                                   * allow launching waves out-of-order. (same as Vulkan) */
 757                                  S_00B800_ORDER_MODE(sctx->chip_class >= GFX7) |
 758                                  S_00B800_CS_W32_EN(sscreen->compute_wave_size == 32);
 759
 760    const uint *last_block = info->last_block;
 761    bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
 762
 763    radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
 764
 765    if (partial_block_en) {
 766       unsigned partial[3];
 767
 768       /* If no partial_block, these should be an entire block size, not 0. */
 769       partial[0] = last_block[0] ? last_block[0] : info->block[0];
 770       partial[1] = last_block[1] ? last_block[1] : info->block[1];
 771       partial[2] = last_block[2] ? last_block[2] : info->block[2];
 772
 773       radeon_emit(
 774          cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) | S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
 775       radeon_emit(
 776          cs, S_00B820_NUM_THREAD_FULL(info->block[1]) | S_00B820_NUM_THREAD_PARTIAL(partial[1]));
 777       radeon_emit(
 778          cs, S_00B824_NUM_THREAD_FULL(info->block[2]) | S_00B824_NUM_THREAD_PARTIAL(partial[2]));
 779
 780       dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
 781    } else {
 782       radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
 783       radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
 784       radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
 785    }
 786
 787    if (info->indirect) {
 788       uint64_t base_va = si_resource(info->indirect)->gpu_address;
 789
 790       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(info->indirect), RADEON_USAGE_READ,
 791                                 RADEON_PRIO_DRAW_INDIRECT);
 792
 793       radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) | PKT3_SHADER_TYPE_S(1));
 794       radeon_emit(cs, 1);
 795       radeon_emit(cs, base_va);
 796       radeon_emit(cs, base_va >> 32);
 797
 798       radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
 799       radeon_emit(cs, info->indirect_offset);
 800       radeon_emit(cs, dispatch_initiator);
 801    } else {
 802       radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
 803       radeon_emit(cs, info->grid[0]);
 804       radeon_emit(cs, info->grid[1]);
 805       radeon_emit(cs, info->grid[2]);
 806       radeon_emit(cs, dispatch_initiator);
 807    }
 808 }
 809
 810 static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
 811 {
 812    struct si_context *sctx = (struct si_context *)ctx;
 813    struct si_compute *program = sctx->cs_shader_state.program;
 814    const amd_kernel_code_t *code_object = si_compute_get_code_object(program, info->pc);
 815    int i;
 816    /* HW bug workaround when CS threadgroups > 256 threads and async
 817     * compute isn't used, i.e. only one compute job can run at a time.
 818     * If async compute is possible, the threadgroup size must be limited
 819     * to 256 threads on all queues to avoid the bug.
 820     * Only GFX6 and certain GFX7 chips are affected.
 821     */
 822    bool cs_regalloc_hang =
 823       (sctx->chip_class == GFX6 || sctx->family == CHIP_BONAIRE || sctx->family == CHIP_KABINI) &&
 824       info->block[0] * info->block[1] * info->block[2] > 256;
 825
 826    if (cs_regalloc_hang)
 827       sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
 828
 829    if (program->ir_type != PIPE_SHADER_IR_NATIVE && program->shader.compilation_failed)
 830       return;
 831
 832    if (sctx->has_graphics) {
 833       if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
 834          si_update_fb_dirtiness_after_rendering(sctx);
 835          sctx->last_num_draw_calls = sctx->num_draw_calls;
 836       }
 837
 838       si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
 839    }
 840
 841    /* Add buffer sizes for memory checking in need_cs_space. */
 842    si_context_add_resource_size(sctx, &program->shader.bo->b.b);
 843    /* TODO: add the scratch buffer */
 844
 845    if (info->indirect) {
 846       si_context_add_resource_size(sctx, info->indirect);
 847
 848       /* Indirect buffers use TC L2 on GFX9, but not older hw. */
 849       if (sctx->chip_class <= GFX8 && si_resource(info->indirect)->TC_L2_dirty) {
 850          sctx->flags |= SI_CONTEXT_WB_L2;
 851          si_resource(info->indirect)->TC_L2_dirty = false;
 852       }
 853    }
 854
 855    si_need_gfx_cs_space(sctx);
 856
 857    /* If we're using a secure context, determine if cs must be secure or not */
 858    if (unlikely(sctx->ws->ws_is_secure(sctx->ws))) {
 859       bool secure = si_compute_resources_check_encrypted(sctx);
 860       if (secure != sctx->ws->cs_is_secure(sctx->gfx_cs)) {
 861          si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 862          sctx->ws->cs_set_secure(sctx->gfx_cs, secure);
 863       }
 864    }
 865
 866    if (sctx->bo_list_add_all_compute_resources)
 867       si_compute_resources_add_all_to_bo_list(sctx);
 868
 869    if (!sctx->cs_shader_state.initialized) {
 870       si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
 871
 872       sctx->cs_shader_state.emitted_program = NULL;
 873       sctx->cs_shader_state.initialized = true;
 874    }
 875
 876    if (sctx->flags)
 877       sctx->emit_cache_flush(sctx);
 878
 879    if (!si_switch_compute_shader(sctx, program, &program->shader, code_object, info->pc))
 880       return;
 881
 882    si_upload_compute_shader_descriptors(sctx);
 883    si_emit_compute_shader_pointers(sctx);
 884
 885    if (sctx->has_graphics && si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
 886       sctx->atoms.s.render_cond.emit(sctx);
 887       si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
 888    }
 889
 890    if (program->ir_type == PIPE_SHADER_IR_NATIVE &&
 891        unlikely(!si_upload_compute_input(sctx, code_object, info)))
 892       return;
 893
 894    /* Global buffers */
 895    for (i = 0; i < program->max_global_buffers; i++) {
 896       struct si_resource *buffer = si_resource(program->global_buffers[i]);
 897       if (!buffer) {
 898          continue;
 899       }
 900       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer, RADEON_USAGE_READWRITE,
 901                                 RADEON_PRIO_COMPUTE_GLOBAL);
 902    }
 903
 904    if (program->ir_type != PIPE_SHADER_IR_NATIVE)
 905       si_setup_nir_user_data(sctx, info);
 906
 907    si_emit_dispatch_packets(sctx, info);
 908
 909    if (unlikely(sctx->current_saved_cs)) {
 910       si_trace_emit(sctx);
 911       si_log_compute_state(sctx, sctx->log);
 912    }
 913
 914    sctx->compute_is_busy = true;
 915    sctx->num_compute_calls++;
 916    if (sctx->cs_shader_state.uses_scratch)
 917       sctx->num_spill_compute_calls++;
 918
 919    if (cs_regalloc_hang)
 920       sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
 921 }
 922
 923 void si_destroy_compute(struct si_compute *program)
 924 {
 925    struct si_shader_selector *sel = &program->sel;
 926
 927    if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
 928       util_queue_drop_job(&sel->screen->shader_compiler_queue, &sel->ready);
 929       util_queue_fence_destroy(&sel->ready);
 930    }
 931
 932    for (unsigned i = 0; i < program->max_global_buffers; i++)
 933       pipe_resource_reference(&program->global_buffers[i], NULL);
 934    FREE(program->global_buffers);
 935
 936    si_shader_destroy(&program->shader);
 937    ralloc_free(program->sel.nir);
 938    FREE(program);
 939 }
 940
 941 static void si_delete_compute_state(struct pipe_context *ctx, void *state)
 942 {
 943    struct si_compute *program = (struct si_compute *)state;
 944    struct si_context *sctx = (struct si_context *)ctx;
 945
 946    if (!state)
 947       return;
 948
 949    if (program == sctx->cs_shader_state.program)
 950       sctx->cs_shader_state.program = NULL;
 951
 952    if (program == sctx->cs_shader_state.emitted_program)
 953       sctx->cs_shader_state.emitted_program = NULL;
 954
 955    si_compute_reference(&program, NULL);
 956 }
 957
 958 static void si_set_compute_resources(struct pipe_context *ctx_, unsigned start, unsigned count,
 959                                      struct pipe_surface **surfaces)
 960 {
 961 }
 962
 963 void si_init_compute_functions(struct si_context *sctx)
 964 {
 965    sctx->b.create_compute_state = si_create_compute_state;
 966    sctx->b.delete_compute_state = si_delete_compute_state;
 967    sctx->b.bind_compute_state = si_bind_compute_state;
 968    sctx->b.set_compute_resources = si_set_compute_resources;
 969    sctx->b.set_global_binding = si_set_global_binding;
 970    sctx->b.launch_grid = si_launch_grid;
 971 }