2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "nir/tgsi_to_nir.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
32 #include "amd_kernel_code_t.h"
33 #include "si_build_pm4.h"
34 #include "si_compute.h"
36 #define COMPUTE_DBG(sscreen, fmt, args...) \
38 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
41 struct dispatch_packet
{
44 uint16_t workgroup_size_x
;
45 uint16_t workgroup_size_y
;
46 uint16_t workgroup_size_z
;
51 uint32_t private_segment_size
;
52 uint32_t group_segment_size
;
53 uint64_t kernel_object
;
54 uint64_t kernarg_address
;
58 static const amd_kernel_code_t
*si_compute_get_code_object(
59 const struct si_compute
*program
,
60 uint64_t symbol_offset
)
62 const struct si_shader_selector
*sel
= &program
->sel
;
64 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
)
67 struct ac_rtld_binary rtld
;
68 if (!ac_rtld_open(&rtld
, (struct ac_rtld_open_info
){
69 .info
= &sel
->screen
->info
,
70 .shader_type
= MESA_SHADER_COMPUTE
,
71 .wave_size
= sel
->screen
->compute_wave_size
,
73 .elf_ptrs
= &program
->shader
.binary
.elf_buffer
,
74 .elf_sizes
= &program
->shader
.binary
.elf_size
}))
77 const amd_kernel_code_t
*result
= NULL
;
80 if (!ac_rtld_get_section_by_name(&rtld
, ".text", &text
, &size
))
83 if (symbol_offset
+ sizeof(amd_kernel_code_t
) > size
)
86 result
= (const amd_kernel_code_t
*)(text
+ symbol_offset
);
93 static void code_object_to_config(const amd_kernel_code_t
*code_object
,
94 struct ac_shader_config
*out_config
) {
96 uint32_t rsrc1
= code_object
->compute_pgm_resource_registers
;
97 uint32_t rsrc2
= code_object
->compute_pgm_resource_registers
>> 32;
98 out_config
->num_sgprs
= code_object
->wavefront_sgpr_count
;
99 out_config
->num_vgprs
= code_object
->workitem_vgpr_count
;
100 out_config
->float_mode
= G_00B028_FLOAT_MODE(rsrc1
);
101 out_config
->rsrc1
= rsrc1
;
102 out_config
->lds_size
= MAX2(out_config
->lds_size
, G_00B84C_LDS_SIZE(rsrc2
));
103 out_config
->rsrc2
= rsrc2
;
104 out_config
->scratch_bytes_per_wave
=
105 align(code_object
->workitem_private_segment_byte_size
* 64, 1024);
108 /* Asynchronous compute shader compilation. */
109 static void si_create_compute_state_async(void *job
, int thread_index
)
111 struct si_compute
*program
= (struct si_compute
*)job
;
112 struct si_shader_selector
*sel
= &program
->sel
;
113 struct si_shader
*shader
= &program
->shader
;
114 struct ac_llvm_compiler
*compiler
;
115 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
116 struct si_screen
*sscreen
= sel
->screen
;
118 assert(!debug
->debug_message
|| debug
->async
);
119 assert(thread_index
>= 0);
120 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
121 compiler
= &sscreen
->compiler
[thread_index
];
123 if (!compiler
->passes
)
124 si_init_compiler(sscreen
, compiler
);
126 assert(program
->ir_type
== PIPE_SHADER_IR_NIR
);
127 si_nir_scan_shader(sel
->nir
, &sel
->info
);
129 /* Store the declared LDS size into si_shader_info for the shader
130 * cache to include it.
132 sel
->info
.properties
[TGSI_PROPERTY_CS_LOCAL_SIZE
] = program
->local_size
;
134 si_get_active_slot_masks(&sel
->info
,
135 &sel
->active_const_and_shader_buffers
,
136 &sel
->active_samplers_and_images
);
138 program
->shader
.is_monolithic
= true;
139 program
->reads_variable_block_size
=
140 sel
->info
.uses_block_size
&&
141 sel
->info
.properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0;
142 program
->num_cs_user_data_dwords
=
143 sel
->info
.properties
[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD
];
145 unsigned char ir_sha1_cache_key
[20];
146 si_get_ir_cache_key(sel
, false, false, ir_sha1_cache_key
);
148 /* Try to load the shader from the shader cache. */
149 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
151 if (si_shader_cache_load_shader(sscreen
, ir_sha1_cache_key
, shader
)) {
152 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
154 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
155 si_shader_dump(sscreen
, shader
, debug
, stderr
, true);
157 if (!si_shader_binary_upload(sscreen
, shader
, 0))
158 program
->shader
.compilation_failed
= true;
160 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
162 if (!si_shader_create(sscreen
, compiler
, &program
->shader
, debug
)) {
163 program
->shader
.compilation_failed
= true;
167 bool scratch_enabled
= shader
->config
.scratch_bytes_per_wave
> 0;
168 unsigned user_sgprs
= SI_NUM_RESOURCE_SGPRS
+
169 (sel
->info
.uses_grid_size
? 3 : 0) +
170 (program
->reads_variable_block_size
? 3 : 0) +
171 program
->num_cs_user_data_dwords
;
173 shader
->config
.rsrc1
=
174 S_00B848_VGPRS((shader
->config
.num_vgprs
- 1) /
175 (sscreen
->compute_wave_size
== 32 ? 8 : 4)) |
176 S_00B848_DX10_CLAMP(1) |
177 S_00B848_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
178 S_00B848_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
179 S_00B848_FLOAT_MODE(shader
->config
.float_mode
);
181 if (sscreen
->info
.chip_class
< GFX10
) {
182 shader
->config
.rsrc1
|=
183 S_00B848_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
186 shader
->config
.rsrc2
=
187 S_00B84C_USER_SGPR(user_sgprs
) |
188 S_00B84C_SCRATCH_EN(scratch_enabled
) |
189 S_00B84C_TGID_X_EN(sel
->info
.uses_block_id
[0]) |
190 S_00B84C_TGID_Y_EN(sel
->info
.uses_block_id
[1]) |
191 S_00B84C_TGID_Z_EN(sel
->info
.uses_block_id
[2]) |
192 S_00B84C_TG_SIZE_EN(sel
->info
.uses_subgroup_info
) |
193 S_00B84C_TIDIG_COMP_CNT(sel
->info
.uses_thread_id
[2] ? 2 :
194 sel
->info
.uses_thread_id
[1] ? 1 : 0) |
195 S_00B84C_LDS_SIZE(shader
->config
.lds_size
);
197 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
198 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
,
200 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
203 ralloc_free(sel
->nir
);
207 static void *si_create_compute_state(
208 struct pipe_context
*ctx
,
209 const struct pipe_compute_state
*cso
)
211 struct si_context
*sctx
= (struct si_context
*)ctx
;
212 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
213 struct si_compute
*program
= CALLOC_STRUCT(si_compute
);
214 struct si_shader_selector
*sel
= &program
->sel
;
216 pipe_reference_init(&sel
->reference
, 1);
217 sel
->type
= PIPE_SHADER_COMPUTE
;
218 sel
->screen
= sscreen
;
219 program
->shader
.selector
= &program
->sel
;
220 program
->ir_type
= cso
->ir_type
;
221 program
->local_size
= cso
->req_local_mem
;
222 program
->private_size
= cso
->req_private_mem
;
223 program
->input_size
= cso
->req_input_mem
;
225 if (cso
->ir_type
!= PIPE_SHADER_IR_NATIVE
) {
226 if (cso
->ir_type
== PIPE_SHADER_IR_TGSI
) {
227 program
->ir_type
= PIPE_SHADER_IR_NIR
;
228 sel
->nir
= tgsi_to_nir(cso
->prog
, ctx
->screen
);
230 assert(cso
->ir_type
== PIPE_SHADER_IR_NIR
);
231 sel
->nir
= (struct nir_shader
*) cso
->prog
;
234 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
235 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
236 p_atomic_inc(&sscreen
->num_shaders_created
);
238 si_schedule_initial_compile(sctx
, PIPE_SHADER_COMPUTE
,
240 &sel
->compiler_ctx_state
,
241 program
, si_create_compute_state_async
);
243 const struct pipe_binary_program_header
*header
;
246 program
->shader
.binary
.elf_size
= header
->num_bytes
;
247 program
->shader
.binary
.elf_buffer
= malloc(header
->num_bytes
);
248 if (!program
->shader
.binary
.elf_buffer
) {
252 memcpy((void *)program
->shader
.binary
.elf_buffer
, header
->blob
, header
->num_bytes
);
254 const amd_kernel_code_t
*code_object
=
255 si_compute_get_code_object(program
, 0);
256 code_object_to_config(code_object
, &program
->shader
.config
);
258 si_shader_dump(sctx
->screen
, &program
->shader
, &sctx
->debug
, stderr
, true);
259 if (!si_shader_binary_upload(sctx
->screen
, &program
->shader
, 0)) {
260 fprintf(stderr
, "LLVM failed to upload shader\n");
261 free((void *)program
->shader
.binary
.elf_buffer
);
270 static void si_bind_compute_state(struct pipe_context
*ctx
, void *state
)
272 struct si_context
*sctx
= (struct si_context
*)ctx
;
273 struct si_compute
*program
= (struct si_compute
*)state
;
274 struct si_shader_selector
*sel
= &program
->sel
;
276 sctx
->cs_shader_state
.program
= program
;
280 /* Wait because we need active slot usage masks. */
281 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
)
282 util_queue_fence_wait(&sel
->ready
);
284 si_set_active_descriptors(sctx
,
285 SI_DESCS_FIRST_COMPUTE
+
286 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
,
287 sel
->active_const_and_shader_buffers
);
288 si_set_active_descriptors(sctx
,
289 SI_DESCS_FIRST_COMPUTE
+
290 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
,
291 sel
->active_samplers_and_images
);
294 static void si_set_global_binding(
295 struct pipe_context
*ctx
, unsigned first
, unsigned n
,
296 struct pipe_resource
**resources
,
300 struct si_context
*sctx
= (struct si_context
*)ctx
;
301 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
303 if (first
+ n
> program
->max_global_buffers
) {
304 unsigned old_max
= program
->max_global_buffers
;
305 program
->max_global_buffers
= first
+ n
;
306 program
->global_buffers
=
307 realloc(program
->global_buffers
,
308 program
->max_global_buffers
*
309 sizeof(program
->global_buffers
[0]));
310 if (!program
->global_buffers
) {
311 fprintf(stderr
, "radeonsi: failed to allocate compute global_buffers\n");
315 memset(&program
->global_buffers
[old_max
], 0,
316 (program
->max_global_buffers
- old_max
) *
317 sizeof(program
->global_buffers
[0]));
321 for (i
= 0; i
< n
; i
++) {
322 pipe_resource_reference(&program
->global_buffers
[first
+ i
], NULL
);
327 for (i
= 0; i
< n
; i
++) {
330 pipe_resource_reference(&program
->global_buffers
[first
+ i
], resources
[i
]);
331 va
= si_resource(resources
[i
])->gpu_address
;
332 offset
= util_le32_to_cpu(*handles
[i
]);
334 va
= util_cpu_to_le64(va
);
335 memcpy(handles
[i
], &va
, sizeof(va
));
339 void si_emit_initial_compute_regs(struct si_context
*sctx
, struct radeon_cmdbuf
*cs
)
343 radeon_set_sh_reg_seq(cs
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
, 2);
344 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
345 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
346 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
347 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
349 if (sctx
->chip_class
>= GFX7
) {
350 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
351 radeon_set_sh_reg_seq(cs
,
352 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
353 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) |
354 S_00B858_SH1_CU_EN(0xffff));
355 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) |
356 S_00B858_SH1_CU_EN(0xffff));
359 if (sctx
->chip_class
>= GFX10
)
360 radeon_set_sh_reg(cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, 0);
362 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
363 * and is now per pipe, so it should be handled in the
364 * kernel if we want to use something other than the default value,
365 * which is now 0x22f.
367 if (sctx
->chip_class
<= GFX6
) {
368 /* XXX: This should be:
369 * (number of compute units) * 4 * (waves per simd) - 1 */
371 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
372 0x190 /* Default value */);
375 /* Set the pointer to border colors. */
376 bc_va
= sctx
->border_color_buffer
->gpu_address
;
378 if (sctx
->chip_class
>= GFX7
) {
379 radeon_set_uconfig_reg_seq(cs
, R_030E00_TA_CS_BC_BASE_ADDR
, 2);
380 radeon_emit(cs
, bc_va
>> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
381 radeon_emit(cs
, S_030E04_ADDRESS(bc_va
>> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
383 if (sctx
->screen
->info
.si_TA_CS_BC_BASE_ADDR_allowed
) {
384 radeon_set_config_reg(cs
, R_00950C_TA_CS_BC_BASE_ADDR
,
390 static bool si_setup_compute_scratch_buffer(struct si_context
*sctx
,
391 struct si_shader
*shader
,
392 struct ac_shader_config
*config
)
394 uint64_t scratch_bo_size
, scratch_needed
;
396 scratch_needed
= config
->scratch_bytes_per_wave
* sctx
->scratch_waves
;
397 if (sctx
->compute_scratch_buffer
)
398 scratch_bo_size
= sctx
->compute_scratch_buffer
->b
.b
.width0
;
400 if (scratch_bo_size
< scratch_needed
) {
401 si_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
403 sctx
->compute_scratch_buffer
=
404 si_aligned_buffer_create(&sctx
->screen
->b
,
405 SI_RESOURCE_FLAG_UNMAPPABLE
,
408 sctx
->screen
->info
.pte_fragment_size
);
410 if (!sctx
->compute_scratch_buffer
)
414 if (sctx
->compute_scratch_buffer
!= shader
->scratch_bo
&& scratch_needed
) {
415 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
417 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
))
420 si_resource_reference(&shader
->scratch_bo
,
421 sctx
->compute_scratch_buffer
);
427 static bool si_switch_compute_shader(struct si_context
*sctx
,
428 struct si_compute
*program
,
429 struct si_shader
*shader
,
430 const amd_kernel_code_t
*code_object
,
433 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
434 struct ac_shader_config inline_config
= {0};
435 struct ac_shader_config
*config
;
438 if (sctx
->cs_shader_state
.emitted_program
== program
&&
439 sctx
->cs_shader_state
.offset
== offset
)
442 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
) {
443 config
= &shader
->config
;
447 config
= &inline_config
;
448 code_object_to_config(code_object
, config
);
450 lds_blocks
= config
->lds_size
;
451 /* XXX: We are over allocating LDS. For GFX6, the shader reports
452 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
453 * allocated in the shader and 4 bytes allocated by the state
454 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
456 if (sctx
->chip_class
<= GFX6
) {
457 lds_blocks
+= align(program
->local_size
, 256) >> 8;
459 lds_blocks
+= align(program
->local_size
, 512) >> 9;
462 /* TODO: use si_multiwave_lds_size_workaround */
463 assert(lds_blocks
<= 0xFF);
465 config
->rsrc2
&= C_00B84C_LDS_SIZE
;
466 config
->rsrc2
|= S_00B84C_LDS_SIZE(lds_blocks
);
469 if (!si_setup_compute_scratch_buffer(sctx
, shader
, config
))
472 if (shader
->scratch_bo
) {
473 COMPUTE_DBG(sctx
->screen
, "Waves: %u; Scratch per wave: %u bytes; "
474 "Total Scratch: %u bytes\n", sctx
->scratch_waves
,
475 config
->scratch_bytes_per_wave
,
476 config
->scratch_bytes_per_wave
*
477 sctx
->scratch_waves
);
479 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
480 shader
->scratch_bo
, RADEON_USAGE_READWRITE
,
481 RADEON_PRIO_SCRATCH_BUFFER
);
484 /* Prefetch the compute shader to TC L2.
486 * We should also prefetch graphics shaders if a compute dispatch was
487 * the last command, and the compute shader if a draw call was the last
488 * command. However, that would add more complexity and we're likely
489 * to get a shader state change in that case anyway.
491 if (sctx
->chip_class
>= GFX7
) {
492 cik_prefetch_TC_L2_async(sctx
, &program
->shader
.bo
->b
.b
,
493 0, program
->shader
.bo
->b
.b
.width0
);
496 shader_va
= shader
->bo
->gpu_address
+ offset
;
497 if (program
->ir_type
== PIPE_SHADER_IR_NATIVE
) {
498 /* Shader code is placed after the amd_kernel_code_t
500 shader_va
+= sizeof(amd_kernel_code_t
);
503 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, shader
->bo
,
504 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
506 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
507 radeon_emit(cs
, shader_va
>> 8);
508 radeon_emit(cs
, S_00B834_DATA(shader_va
>> 40));
510 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
511 radeon_emit(cs
, config
->rsrc1
);
512 radeon_emit(cs
, config
->rsrc2
);
514 COMPUTE_DBG(sctx
->screen
, "COMPUTE_PGM_RSRC1: 0x%08x "
515 "COMPUTE_PGM_RSRC2: 0x%08x\n", config
->rsrc1
, config
->rsrc2
);
517 sctx
->max_seen_compute_scratch_bytes_per_wave
=
518 MAX2(sctx
->max_seen_compute_scratch_bytes_per_wave
,
519 config
->scratch_bytes_per_wave
);
521 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
522 S_00B860_WAVES(sctx
->scratch_waves
)
523 | S_00B860_WAVESIZE(sctx
->max_seen_compute_scratch_bytes_per_wave
>> 10));
525 sctx
->cs_shader_state
.emitted_program
= program
;
526 sctx
->cs_shader_state
.offset
= offset
;
527 sctx
->cs_shader_state
.uses_scratch
=
528 config
->scratch_bytes_per_wave
!= 0;
533 static void setup_scratch_rsrc_user_sgprs(struct si_context
*sctx
,
534 const amd_kernel_code_t
*code_object
,
537 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
538 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
540 unsigned max_private_element_size
= AMD_HSA_BITS_GET(
541 code_object
->code_properties
,
542 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE
);
544 uint32_t scratch_dword0
= scratch_va
& 0xffffffff;
545 uint32_t scratch_dword1
=
546 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
547 S_008F04_SWIZZLE_ENABLE(1);
549 /* Disable address clamping */
550 uint32_t scratch_dword2
= 0xffffffff;
551 uint32_t scratch_dword3
=
552 S_008F0C_INDEX_STRIDE(3) |
553 S_008F0C_ADD_TID_ENABLE(1);
555 if (sctx
->chip_class
>= GFX9
) {
556 assert(max_private_element_size
== 1); /* always 4 bytes on GFX9 */
558 scratch_dword3
|= S_008F0C_ELEMENT_SIZE(max_private_element_size
);
560 if (sctx
->chip_class
< GFX8
) {
561 /* BUF_DATA_FORMAT is ignored, but it cannot be
562 * BUF_DATA_FORMAT_INVALID. */
564 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8
);
568 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
570 radeon_emit(cs
, scratch_dword0
);
571 radeon_emit(cs
, scratch_dword1
);
572 radeon_emit(cs
, scratch_dword2
);
573 radeon_emit(cs
, scratch_dword3
);
576 static void si_setup_user_sgprs_co_v2(struct si_context
*sctx
,
577 const amd_kernel_code_t
*code_object
,
578 const struct pipe_grid_info
*info
,
579 uint64_t kernel_args_va
)
581 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
582 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
584 static const enum amd_code_property_mask_t workgroup_count_masks
[] = {
585 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X
,
586 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y
,
587 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
590 unsigned i
, user_sgpr
= 0;
591 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
592 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER
)) {
593 if (code_object
->workitem_private_segment_byte_size
> 0) {
594 setup_scratch_rsrc_user_sgprs(sctx
, code_object
,
600 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
601 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR
)) {
602 struct dispatch_packet dispatch
;
603 unsigned dispatch_offset
;
604 struct si_resource
*dispatch_buf
= NULL
;
605 uint64_t dispatch_va
;
607 /* Upload dispatch ptr */
608 memset(&dispatch
, 0, sizeof(dispatch
));
610 dispatch
.workgroup_size_x
= util_cpu_to_le16(info
->block
[0]);
611 dispatch
.workgroup_size_y
= util_cpu_to_le16(info
->block
[1]);
612 dispatch
.workgroup_size_z
= util_cpu_to_le16(info
->block
[2]);
614 dispatch
.grid_size_x
= util_cpu_to_le32(info
->grid
[0] * info
->block
[0]);
615 dispatch
.grid_size_y
= util_cpu_to_le32(info
->grid
[1] * info
->block
[1]);
616 dispatch
.grid_size_z
= util_cpu_to_le32(info
->grid
[2] * info
->block
[2]);
618 dispatch
.private_segment_size
= util_cpu_to_le32(program
->private_size
);
619 dispatch
.group_segment_size
= util_cpu_to_le32(program
->local_size
);
621 dispatch
.kernarg_address
= util_cpu_to_le64(kernel_args_va
);
623 u_upload_data(sctx
->b
.const_uploader
, 0, sizeof(dispatch
),
624 256, &dispatch
, &dispatch_offset
,
625 (struct pipe_resource
**)&dispatch_buf
);
628 fprintf(stderr
, "Error: Failed to allocate dispatch "
631 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, dispatch_buf
,
632 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
634 dispatch_va
= dispatch_buf
->gpu_address
+ dispatch_offset
;
636 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
638 radeon_emit(cs
, dispatch_va
);
639 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(dispatch_va
>> 32) |
642 si_resource_reference(&dispatch_buf
, NULL
);
646 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
647 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR
)) {
648 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
650 radeon_emit(cs
, kernel_args_va
);
651 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) |
656 for (i
= 0; i
< 3 && user_sgpr
< 16; i
++) {
657 if (code_object
->code_properties
& workgroup_count_masks
[i
]) {
658 radeon_set_sh_reg_seq(cs
,
659 R_00B900_COMPUTE_USER_DATA_0
+
661 radeon_emit(cs
, info
->grid
[i
]);
667 static bool si_upload_compute_input(struct si_context
*sctx
,
668 const amd_kernel_code_t
*code_object
,
669 const struct pipe_grid_info
*info
)
671 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
672 struct si_resource
*input_buffer
= NULL
;
673 uint32_t kernel_args_offset
= 0;
674 uint32_t *kernel_args
;
675 void *kernel_args_ptr
;
676 uint64_t kernel_args_va
;
678 u_upload_alloc(sctx
->b
.const_uploader
, 0, program
->input_size
,
679 sctx
->screen
->info
.tcc_cache_line_size
,
681 (struct pipe_resource
**)&input_buffer
, &kernel_args_ptr
);
683 if (unlikely(!kernel_args_ptr
))
686 kernel_args
= (uint32_t*)kernel_args_ptr
;
687 kernel_args_va
= input_buffer
->gpu_address
+ kernel_args_offset
;
689 memcpy(kernel_args
, info
->input
, program
->input_size
);
691 for (unsigned i
= 0; i
< program
->input_size
/ 4; i
++) {
692 COMPUTE_DBG(sctx
->screen
, "input %u : %u\n", i
,
696 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, input_buffer
,
697 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
699 si_setup_user_sgprs_co_v2(sctx
, code_object
, info
, kernel_args_va
);
700 si_resource_reference(&input_buffer
, NULL
);
704 static void si_setup_nir_user_data(struct si_context
*sctx
,
705 const struct pipe_grid_info
*info
)
707 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
708 struct si_shader_selector
*sel
= &program
->sel
;
709 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
710 unsigned grid_size_reg
= R_00B900_COMPUTE_USER_DATA_0
+
711 4 * SI_NUM_RESOURCE_SGPRS
;
712 unsigned block_size_reg
= grid_size_reg
+
713 /* 12 bytes = 3 dwords. */
714 12 * sel
->info
.uses_grid_size
;
715 unsigned cs_user_data_reg
= block_size_reg
+
716 12 * program
->reads_variable_block_size
;
718 if (info
->indirect
) {
719 if (sel
->info
.uses_grid_size
) {
720 for (unsigned i
= 0; i
< 3; ++i
) {
721 si_cp_copy_data(sctx
, sctx
->gfx_cs
,
722 COPY_DATA_REG
, NULL
, (grid_size_reg
>> 2) + i
,
723 COPY_DATA_SRC_MEM
, si_resource(info
->indirect
),
724 info
->indirect_offset
+ 4 * i
);
728 if (sel
->info
.uses_grid_size
) {
729 radeon_set_sh_reg_seq(cs
, grid_size_reg
, 3);
730 radeon_emit(cs
, info
->grid
[0]);
731 radeon_emit(cs
, info
->grid
[1]);
732 radeon_emit(cs
, info
->grid
[2]);
734 if (program
->reads_variable_block_size
) {
735 radeon_set_sh_reg_seq(cs
, block_size_reg
, 3);
736 radeon_emit(cs
, info
->block
[0]);
737 radeon_emit(cs
, info
->block
[1]);
738 radeon_emit(cs
, info
->block
[2]);
742 if (program
->num_cs_user_data_dwords
) {
743 radeon_set_sh_reg_seq(cs
, cs_user_data_reg
, program
->num_cs_user_data_dwords
);
744 radeon_emit_array(cs
, sctx
->cs_user_data
, program
->num_cs_user_data_dwords
);
748 static void si_emit_dispatch_packets(struct si_context
*sctx
,
749 const struct pipe_grid_info
*info
)
751 struct si_screen
*sscreen
= sctx
->screen
;
752 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
753 bool render_cond_bit
= sctx
->render_cond
&& !sctx
->render_cond_force_off
;
754 unsigned threads_per_threadgroup
=
755 info
->block
[0] * info
->block
[1] * info
->block
[2];
756 unsigned waves_per_threadgroup
=
757 DIV_ROUND_UP(threads_per_threadgroup
, sscreen
->compute_wave_size
);
758 unsigned threadgroups_per_cu
= 1;
760 if (sctx
->chip_class
>= GFX10
&& waves_per_threadgroup
== 1)
761 threadgroups_per_cu
= 2;
763 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
764 ac_get_compute_resource_limits(&sscreen
->info
,
765 waves_per_threadgroup
,
766 sctx
->cs_max_waves_per_sh
,
767 threadgroups_per_cu
));
769 unsigned dispatch_initiator
=
770 S_00B800_COMPUTE_SHADER_EN(1) |
771 S_00B800_FORCE_START_AT_000(1) |
772 /* If the KMD allows it (there is a KMD hw register for it),
773 * allow launching waves out-of-order. (same as Vulkan) */
774 S_00B800_ORDER_MODE(sctx
->chip_class
>= GFX7
) |
775 S_00B800_CS_W32_EN(sscreen
->compute_wave_size
== 32);
777 const uint
*last_block
= info
->last_block
;
778 bool partial_block_en
= last_block
[0] || last_block
[1] || last_block
[2];
780 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
782 if (partial_block_en
) {
785 /* If no partial_block, these should be an entire block size, not 0. */
786 partial
[0] = last_block
[0] ? last_block
[0] : info
->block
[0];
787 partial
[1] = last_block
[1] ? last_block
[1] : info
->block
[1];
788 partial
[2] = last_block
[2] ? last_block
[2] : info
->block
[2];
790 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(info
->block
[0]) |
791 S_00B81C_NUM_THREAD_PARTIAL(partial
[0]));
792 radeon_emit(cs
, S_00B820_NUM_THREAD_FULL(info
->block
[1]) |
793 S_00B820_NUM_THREAD_PARTIAL(partial
[1]));
794 radeon_emit(cs
, S_00B824_NUM_THREAD_FULL(info
->block
[2]) |
795 S_00B824_NUM_THREAD_PARTIAL(partial
[2]));
797 dispatch_initiator
|= S_00B800_PARTIAL_TG_EN(1);
799 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(info
->block
[0]));
800 radeon_emit(cs
, S_00B820_NUM_THREAD_FULL(info
->block
[1]));
801 radeon_emit(cs
, S_00B824_NUM_THREAD_FULL(info
->block
[2]));
804 if (info
->indirect
) {
805 uint64_t base_va
= si_resource(info
->indirect
)->gpu_address
;
807 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
808 si_resource(info
->indirect
),
809 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
811 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
812 PKT3_SHADER_TYPE_S(1));
814 radeon_emit(cs
, base_va
);
815 radeon_emit(cs
, base_va
>> 32);
817 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, render_cond_bit
) |
818 PKT3_SHADER_TYPE_S(1));
819 radeon_emit(cs
, info
->indirect_offset
);
820 radeon_emit(cs
, dispatch_initiator
);
822 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, render_cond_bit
) |
823 PKT3_SHADER_TYPE_S(1));
824 radeon_emit(cs
, info
->grid
[0]);
825 radeon_emit(cs
, info
->grid
[1]);
826 radeon_emit(cs
, info
->grid
[2]);
827 radeon_emit(cs
, dispatch_initiator
);
832 static void si_launch_grid(
833 struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
835 struct si_context
*sctx
= (struct si_context
*)ctx
;
836 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
837 const amd_kernel_code_t
*code_object
=
838 si_compute_get_code_object(program
, info
->pc
);
840 /* HW bug workaround when CS threadgroups > 256 threads and async
841 * compute isn't used, i.e. only one compute job can run at a time.
842 * If async compute is possible, the threadgroup size must be limited
843 * to 256 threads on all queues to avoid the bug.
844 * Only GFX6 and certain GFX7 chips are affected.
846 bool cs_regalloc_hang
=
847 (sctx
->chip_class
== GFX6
||
848 sctx
->family
== CHIP_BONAIRE
||
849 sctx
->family
== CHIP_KABINI
) &&
850 info
->block
[0] * info
->block
[1] * info
->block
[2] > 256;
852 if (cs_regalloc_hang
)
853 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
854 SI_CONTEXT_CS_PARTIAL_FLUSH
;
856 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
&&
857 program
->shader
.compilation_failed
)
860 if (sctx
->has_graphics
) {
861 if (sctx
->last_num_draw_calls
!= sctx
->num_draw_calls
) {
862 si_update_fb_dirtiness_after_rendering(sctx
);
863 sctx
->last_num_draw_calls
= sctx
->num_draw_calls
;
866 si_decompress_textures(sctx
, 1 << PIPE_SHADER_COMPUTE
);
869 /* Add buffer sizes for memory checking in need_cs_space. */
870 si_context_add_resource_size(sctx
, &program
->shader
.bo
->b
.b
);
871 /* TODO: add the scratch buffer */
873 if (info
->indirect
) {
874 si_context_add_resource_size(sctx
, info
->indirect
);
876 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
877 if (sctx
->chip_class
<= GFX8
&&
878 si_resource(info
->indirect
)->TC_L2_dirty
) {
879 sctx
->flags
|= SI_CONTEXT_WB_L2
;
880 si_resource(info
->indirect
)->TC_L2_dirty
= false;
884 si_need_gfx_cs_space(sctx
);
886 if (sctx
->bo_list_add_all_compute_resources
)
887 si_compute_resources_add_all_to_bo_list(sctx
);
889 if (!sctx
->cs_shader_state
.initialized
) {
890 si_emit_initial_compute_regs(sctx
, sctx
->gfx_cs
);
892 sctx
->cs_shader_state
.emitted_program
= NULL
;
893 sctx
->cs_shader_state
.initialized
= true;
897 sctx
->emit_cache_flush(sctx
);
899 if (!si_switch_compute_shader(sctx
, program
, &program
->shader
,
900 code_object
, info
->pc
))
903 si_upload_compute_shader_descriptors(sctx
);
904 si_emit_compute_shader_pointers(sctx
);
906 if (sctx
->has_graphics
&&
907 si_is_atom_dirty(sctx
, &sctx
->atoms
.s
.render_cond
)) {
908 sctx
->atoms
.s
.render_cond
.emit(sctx
);
909 si_set_atom_dirty(sctx
, &sctx
->atoms
.s
.render_cond
, false);
912 if (program
->ir_type
== PIPE_SHADER_IR_NATIVE
&&
913 unlikely(!si_upload_compute_input(sctx
, code_object
, info
)))
917 for (i
= 0; i
< program
->max_global_buffers
; i
++) {
918 struct si_resource
*buffer
=
919 si_resource(program
->global_buffers
[i
]);
923 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, buffer
,
924 RADEON_USAGE_READWRITE
,
925 RADEON_PRIO_COMPUTE_GLOBAL
);
928 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
)
929 si_setup_nir_user_data(sctx
, info
);
931 si_emit_dispatch_packets(sctx
, info
);
933 if (unlikely(sctx
->current_saved_cs
)) {
935 si_log_compute_state(sctx
, sctx
->log
);
938 sctx
->compute_is_busy
= true;
939 sctx
->num_compute_calls
++;
940 if (sctx
->cs_shader_state
.uses_scratch
)
941 sctx
->num_spill_compute_calls
++;
943 if (cs_regalloc_hang
)
944 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
947 void si_destroy_compute(struct si_compute
*program
)
949 struct si_shader_selector
*sel
= &program
->sel
;
951 if (program
->ir_type
!= PIPE_SHADER_IR_NATIVE
) {
952 util_queue_drop_job(&sel
->screen
->shader_compiler_queue
,
954 util_queue_fence_destroy(&sel
->ready
);
957 for (unsigned i
= 0; i
< program
->max_global_buffers
; i
++)
958 pipe_resource_reference(&program
->global_buffers
[i
], NULL
);
959 FREE(program
->global_buffers
);
961 si_shader_destroy(&program
->shader
);
962 ralloc_free(program
->sel
.nir
);
966 static void si_delete_compute_state(struct pipe_context
*ctx
, void* state
){
967 struct si_compute
*program
= (struct si_compute
*)state
;
968 struct si_context
*sctx
= (struct si_context
*)ctx
;
973 if (program
== sctx
->cs_shader_state
.program
)
974 sctx
->cs_shader_state
.program
= NULL
;
976 if (program
== sctx
->cs_shader_state
.emitted_program
)
977 sctx
->cs_shader_state
.emitted_program
= NULL
;
979 si_compute_reference(&program
, NULL
);
982 static void si_set_compute_resources(struct pipe_context
* ctx_
,
983 unsigned start
, unsigned count
,
984 struct pipe_surface
** surfaces
) { }
986 void si_init_compute_functions(struct si_context
*sctx
)
988 sctx
->b
.create_compute_state
= si_create_compute_state
;
989 sctx
->b
.delete_compute_state
= si_delete_compute_state
;
990 sctx
->b
.bind_compute_state
= si_bind_compute_state
;
991 sctx
->b
.set_compute_resources
= si_set_compute_resources
;
992 sctx
->b
.set_global_binding
= si_set_global_binding
;
993 sctx
->b
.launch_grid
= si_launch_grid
;