src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "util/u_memory.h"
  26 #include "radeon/r600_pipe_common.h"
  27 #include "radeon/radeon_elf_util.h"
  28 #include "radeon/radeon_llvm_util.h"
  29
  30 #include "radeon/r600_cs.h"
  31 #include "si_pipe.h"
  32 #include "si_shader.h"
  33 #include "sid.h"
  34
  35 #define MAX_GLOBAL_BUFFERS 20
  36
  37 struct si_compute {
  38         struct si_context *ctx;
  39
  40         unsigned local_size;
  41         unsigned private_size;
  42         unsigned input_size;
  43         struct si_shader shader;
  44         unsigned num_user_sgprs;
  45
  46         struct r600_resource *input_buffer;
  47         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  48 };
  49
  50 static void init_scratch_buffer(struct si_context *sctx, struct si_compute *program)
  51 {
  52         unsigned scratch_bytes = 0;
  53         uint64_t scratch_buffer_va;
  54         unsigned i;
  55
  56         /* Compute the scratch buffer size using the maximum number of waves.
  57          * This way we don't need to recompute it for each kernel launch. */
  58         unsigned scratch_waves = 32 * sctx->screen->b.info.num_good_compute_units;
  59         for (i = 0; i < program->shader.binary.global_symbol_count; i++) {
  60                 unsigned offset =
  61                                 program->shader.binary.global_symbol_offsets[i];
  62                 unsigned scratch_bytes_needed;
  63
  64                 si_shader_binary_read_config(&program->shader.binary,
  65                                              &program->shader.config, offset);
  66                 scratch_bytes_needed = program->shader.config.scratch_bytes_per_wave;
  67                 scratch_bytes = MAX2(scratch_bytes, scratch_bytes_needed);
  68         }
  69
  70         if (scratch_bytes == 0)
  71                 return;
  72
  73         program->shader.scratch_bo =
  74                                 si_resource_create_custom(sctx->b.b.screen,
  75                                 PIPE_USAGE_DEFAULT,
  76                                 scratch_bytes * scratch_waves);
  77
  78         scratch_buffer_va = program->shader.scratch_bo->gpu_address;
  79
  80         /* apply_scratch_relocs needs scratch_bytes_per_wave to be set
  81          * to the maximum bytes needed, so it can compute the stride
  82          * correctly.
  83          */
  84         program->shader.config.scratch_bytes_per_wave = scratch_bytes;
  85
  86         /* Patch the shader with the scratch buffer address. */
  87         si_shader_apply_scratch_relocs(sctx,
  88                                 &program->shader, scratch_buffer_va);
  89 }
  90
  91 static void *si_create_compute_state(
  92         struct pipe_context *ctx,
  93         const struct pipe_compute_state *cso)
  94 {
  95         struct si_context *sctx = (struct si_context *)ctx;
  96         struct si_compute *program = CALLOC_STRUCT(si_compute);
  97         const struct pipe_llvm_program_header *header;
  98         const char *code;
  99
 100         header = cso->prog;
 101         code = cso->prog + sizeof(struct pipe_llvm_program_header);
 102
 103         program->ctx = sctx;
 104         program->local_size = cso->req_local_mem;
 105         program->private_size = cso->req_private_mem;
 106         program->input_size = cso->req_input_mem;
 107
 108         radeon_elf_read(code, header->num_bytes, &program->shader.binary);
 109
 110         /* init_scratch_buffer patches the shader code with the scratch address,
 111          * so we need to call it before si_shader_binary_read() which uploads
 112          * the shader code to the GPU.
 113          */
 114         init_scratch_buffer(sctx, program);
 115         si_shader_binary_read_config(&program->shader.binary,
 116                                      &program->shader.config, 0);
 117         si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
 118                        TGSI_PROCESSOR_COMPUTE);
 119         si_shader_binary_upload(sctx->screen, &program->shader);
 120
 121         program->input_buffer = si_resource_create_custom(sctx->b.b.screen,
 122                 PIPE_USAGE_IMMUTABLE, program->input_size);
 123
 124         return program;
 125 }
 126
 127 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 128 {
 129         struct si_context *sctx = (struct si_context*)ctx;
 130         sctx->cs_shader_state.program = (struct si_compute*)state;
 131 }
 132
 133 static void si_set_global_binding(
 134         struct pipe_context *ctx, unsigned first, unsigned n,
 135         struct pipe_resource **resources,
 136         uint32_t **handles)
 137 {
 138         unsigned i;
 139         struct si_context *sctx = (struct si_context*)ctx;
 140         struct si_compute *program = sctx->cs_shader_state.program;
 141
 142         if (!resources) {
 143                 for (i = first; i < first + n; i++) {
 144                         pipe_resource_reference(&program->global_buffers[i], NULL);
 145                 }
 146                 return;
 147         }
 148
 149         for (i = first; i < first + n; i++) {
 150                 uint64_t va;
 151                 uint32_t offset;
 152                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 153                 va = r600_resource(resources[i])->gpu_address;
 154                 offset = util_le32_to_cpu(*handles[i]);
 155                 va += offset;
 156                 va = util_cpu_to_le64(va);
 157                 memcpy(handles[i], &va, sizeof(va));
 158         }
 159 }
 160
 161 /**
 162  * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
 163  * /p block_layout is the number of threads in each work group.
 164  * /p grid layout is the number of work groups.
 165  */
 166 static unsigned compute_num_waves_for_scratch(
 167                 const struct radeon_info *info,
 168                 const uint *block_layout,
 169                 const uint *grid_layout)
 170 {
 171         unsigned num_sh = MAX2(info->max_sh_per_se, 1);
 172         unsigned num_se = MAX2(info->max_se, 1);
 173         unsigned num_blocks = 1;
 174         unsigned threads_per_block = 1;
 175         unsigned waves_per_block;
 176         unsigned waves_per_sh;
 177         unsigned waves;
 178         unsigned scratch_waves;
 179         unsigned i;
 180
 181         for (i = 0; i < 3; i++) {
 182                 threads_per_block *= block_layout[i];
 183                 num_blocks *= grid_layout[i];
 184         }
 185
 186         waves_per_block = align(threads_per_block, 64) / 64;
 187         waves = waves_per_block * num_blocks;
 188         waves_per_sh = align(waves, num_sh * num_se) / (num_sh * num_se);
 189         scratch_waves = waves_per_sh * num_sh * num_se;
 190
 191         if (waves_per_block > waves_per_sh) {
 192                 scratch_waves = waves_per_block * num_sh * num_se;
 193         }
 194
 195         return scratch_waves;
 196 }
 197
 198 static void si_launch_grid(
 199                 struct pipe_context *ctx,
 200                 const uint *block_layout, const uint *grid_layout,
 201                 uint32_t pc, const void *input)
 202 {
 203         struct si_context *sctx = (struct si_context*)ctx;
 204         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 205         struct si_compute *program = sctx->cs_shader_state.program;
 206         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 207         struct r600_resource *input_buffer = program->input_buffer;
 208         unsigned kernel_args_size;
 209         unsigned num_work_size_bytes = 36;
 210         uint32_t kernel_args_offset = 0;
 211         uint32_t *kernel_args;
 212         uint64_t kernel_args_va;
 213         uint64_t scratch_buffer_va = 0;
 214         uint64_t shader_va;
 215         unsigned i;
 216         struct si_shader *shader = &program->shader;
 217         unsigned lds_blocks;
 218         unsigned num_waves_for_scratch;
 219
 220         radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1));
 221         radeon_emit(cs, 0x80000000);
 222         radeon_emit(cs, 0x80000000);
 223
 224         sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
 225                          SI_CONTEXT_INV_GLOBAL_L2 |
 226                          SI_CONTEXT_INV_ICACHE |
 227                          SI_CONTEXT_INV_SMEM_L1 |
 228                          SI_CONTEXT_FLUSH_WITH_INV_L2 |
 229                          SI_CONTEXT_FLAG_COMPUTE;
 230         si_emit_cache_flush(sctx, NULL);
 231
 232         pm4->compute_pkt = true;
 233
 234         /* Read the config information */
 235         si_shader_binary_read_config(&shader->binary, &shader->config, pc);
 236
 237         /* Upload the kernel arguments */
 238
 239         /* The extra num_work_size_bytes are for work group / work item size information */
 240         kernel_args_size = program->input_size + num_work_size_bytes + 8 /* For scratch va */;
 241
 242         kernel_args = sctx->b.ws->buffer_map(input_buffer->buf,
 243                         sctx->b.gfx.cs, PIPE_TRANSFER_WRITE);
 244         for (i = 0; i < 3; i++) {
 245                 kernel_args[i] = grid_layout[i];
 246                 kernel_args[i + 3] = grid_layout[i] * block_layout[i];
 247                 kernel_args[i + 6] = block_layout[i];
 248         }
 249
 250         num_waves_for_scratch = compute_num_waves_for_scratch(
 251                 &sctx->screen->b.info, block_layout, grid_layout);
 252
 253         memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size);
 254
 255         if (shader->config.scratch_bytes_per_wave > 0) {
 256
 257                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 258                             "Total Scratch: %u bytes\n", num_waves_for_scratch,
 259                             shader->config.scratch_bytes_per_wave,
 260                             shader->config.scratch_bytes_per_wave *
 261                             num_waves_for_scratch);
 262
 263                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 264                                           shader->scratch_bo,
 265                                           RADEON_USAGE_READWRITE,
 266                                           RADEON_PRIO_SCRATCH_BUFFER);
 267
 268                 scratch_buffer_va = shader->scratch_bo->gpu_address;
 269         }
 270
 271         for (i = 0; i < (kernel_args_size / 4); i++) {
 272                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 273                         kernel_args[i]);
 274         }
 275
 276         kernel_args_va = input_buffer->gpu_address;
 277         kernel_args_va += kernel_args_offset;
 278
 279         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
 280                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 281
 282         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
 283         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
 284         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 8, scratch_buffer_va);
 285         si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 12,
 286                 S_008F04_BASE_ADDRESS_HI(scratch_buffer_va >> 32)
 287                 |  S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64));
 288
 289         si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
 290         si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
 291         si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
 292
 293         si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
 294                                 S_00B81C_NUM_THREAD_FULL(block_layout[0]));
 295         si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
 296                                 S_00B820_NUM_THREAD_FULL(block_layout[1]));
 297         si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
 298                                 S_00B824_NUM_THREAD_FULL(block_layout[2]));
 299
 300         /* Global buffers */
 301         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 302                 struct r600_resource *buffer =
 303                                 (struct r600_resource*)program->global_buffers[i];
 304                 if (!buffer) {
 305                         continue;
 306                 }
 307                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
 308                                           RADEON_USAGE_READWRITE,
 309                                           RADEON_PRIO_COMPUTE_GLOBAL);
 310         }
 311
 312         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 313          * and is now per pipe, so it should be handled in the
 314          * kernel if we want to use something other than the default value,
 315          * which is now 0x22f.
 316          */
 317         if (sctx->b.chip_class <= SI) {
 318                 /* XXX: This should be:
 319                  * (number of compute units) * 4 * (waves per simd) - 1 */
 320
 321                 si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID,
 322                                                 0x190 /* Default value */);
 323         }
 324
 325         shader_va = shader->bo->gpu_address;
 326         shader_va += pc;
 327
 328         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 329                                   RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
 330         si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
 331         si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
 332
 333         si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1, shader->config.rsrc1);
 334
 335         lds_blocks = shader->config.lds_size;
 336         /* XXX: We are over allocating LDS.  For SI, the shader reports LDS in
 337          * blocks of 256 bytes, so if there are 4 bytes lds allocated in
 338          * the shader and 4 bytes allocated by the state tracker, then
 339          * we will set LDS_SIZE to 512 bytes rather than 256.
 340          */
 341         if (sctx->b.chip_class <= SI) {
 342                 lds_blocks += align(program->local_size, 256) >> 8;
 343         } else {
 344                 lds_blocks += align(program->local_size, 512) >> 9;
 345         }
 346
 347         assert(lds_blocks <= 0xFF);
 348
 349         shader->config.rsrc2 &= C_00B84C_LDS_SIZE;
 350         shader->config.rsrc2 |=  S_00B84C_LDS_SIZE(lds_blocks);
 351
 352         si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2, shader->config.rsrc2);
 353         si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
 354
 355         si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
 356                 S_00B858_SH0_CU_EN(0xffff /* Default value */)
 357                 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
 358                 ;
 359
 360         si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
 361                 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
 362                 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
 363                 ;
 364
 365         num_waves_for_scratch =
 366                 MIN2(num_waves_for_scratch,
 367                      32 * sctx->screen->b.info.num_good_compute_units);
 368         si_pm4_set_reg(pm4, R_00B860_COMPUTE_TMPRING_SIZE,
 369                 /* The maximum value for WAVES is 32 * num CU.
 370                  * If you program this value incorrectly, the GPU will hang if
 371                  * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
 372                  */
 373                 S_00B860_WAVES(num_waves_for_scratch)
 374                 | S_00B860_WAVESIZE(shader->config.scratch_bytes_per_wave >> 10))
 375                 ;
 376
 377         si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
 378         si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
 379         si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
 380         si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
 381         si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
 382         si_pm4_cmd_end(pm4, false);
 383
 384         si_pm4_emit(sctx, pm4);
 385
 386 #if 0
 387         fprintf(stderr, "cdw: %i\n", sctx->cs->cdw);
 388         for (i = 0; i < sctx->cs->cdw; i++) {
 389                 fprintf(stderr, "%4i : 0x%08X\n", i, sctx->cs->buf[i]);
 390         }
 391 #endif
 392
 393         si_pm4_free_state(sctx, pm4, ~0);
 394
 395         sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 396                          SI_CONTEXT_INV_VMEM_L1 |
 397                          SI_CONTEXT_INV_GLOBAL_L2 |
 398                          SI_CONTEXT_INV_ICACHE |
 399                          SI_CONTEXT_INV_SMEM_L1 |
 400                          SI_CONTEXT_FLAG_COMPUTE;
 401         si_emit_cache_flush(sctx, NULL);
 402 }
 403
 404
 405 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 406         struct si_compute *program = (struct si_compute *)state;
 407
 408         if (!state) {
 409                 return;
 410         }
 411
 412         si_shader_destroy(&program->shader);
 413         pipe_resource_reference(
 414                 (struct pipe_resource **)&program->input_buffer, NULL);
 415         FREE(program);
 416 }
 417
 418 static void si_set_compute_resources(struct pipe_context * ctx_,
 419                 unsigned start, unsigned count,
 420                 struct pipe_surface ** surfaces) { }
 421
 422 void si_init_compute_functions(struct si_context *sctx)
 423 {
 424         sctx->b.b.create_compute_state = si_create_compute_state;
 425         sctx->b.b.delete_compute_state = si_delete_compute_state;
 426         sctx->b.b.bind_compute_state = si_bind_compute_state;
 427 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 428         sctx->b.b.set_compute_resources = si_set_compute_resources;
 429         sctx->b.b.set_global_binding = si_set_global_binding;
 430         sctx->b.b.launch_grid = si_launch_grid;
 431 }