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radeonsi: enable shader caching for compute shaders
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "tgsi/tgsi_parse.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30
31 #include "amd_kernel_code_t.h"
32 #include "si_build_pm4.h"
33 #include "si_compute.h"
34
35 #define COMPUTE_DBG(rscreen, fmt, args...) \
36 do { \
37 if ((rscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
38 } while (0);
39
40 struct dispatch_packet {
41 uint16_t header;
42 uint16_t setup;
43 uint16_t workgroup_size_x;
44 uint16_t workgroup_size_y;
45 uint16_t workgroup_size_z;
46 uint16_t reserved0;
47 uint32_t grid_size_x;
48 uint32_t grid_size_y;
49 uint32_t grid_size_z;
50 uint32_t private_segment_size;
51 uint32_t group_segment_size;
52 uint64_t kernel_object;
53 uint64_t kernarg_address;
54 uint64_t reserved2;
55 };
56
57 static const amd_kernel_code_t *si_compute_get_code_object(
58 const struct si_compute *program,
59 uint64_t symbol_offset)
60 {
61 if (!program->use_code_object_v2) {
62 return NULL;
63 }
64 return (const amd_kernel_code_t*)
65 (program->shader.binary.code + symbol_offset);
66 }
67
68 static void code_object_to_config(const amd_kernel_code_t *code_object,
69 struct si_shader_config *out_config) {
70
71 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
72 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
73 out_config->num_sgprs = code_object->wavefront_sgpr_count;
74 out_config->num_vgprs = code_object->workitem_vgpr_count;
75 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
76 out_config->rsrc1 = rsrc1;
77 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
78 out_config->rsrc2 = rsrc2;
79 out_config->scratch_bytes_per_wave =
80 align(code_object->workitem_private_segment_byte_size * 64, 1024);
81 }
82
83 /* Asynchronous compute shader compilation. */
84 static void si_create_compute_state_async(void *job, int thread_index)
85 {
86 struct si_compute *program = (struct si_compute *)job;
87 struct si_shader *shader = &program->shader;
88 struct si_shader_selector sel;
89 struct si_compiler *compiler;
90 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
91 struct si_screen *sscreen = program->screen;
92
93 assert(!debug->debug_message || debug->async);
94 assert(thread_index >= 0);
95 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
96 compiler = &sscreen->compiler[thread_index];
97
98 memset(&sel, 0, sizeof(sel));
99
100 sel.screen = sscreen;
101
102 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
103 tgsi_scan_shader(program->ir.tgsi, &sel.info);
104 sel.tokens = program->ir.tgsi;
105 } else {
106 assert(program->ir_type == PIPE_SHADER_IR_NIR);
107 sel.nir = program->ir.nir;
108
109 si_nir_scan_shader(sel.nir, &sel.info);
110 si_lower_nir(&sel);
111 }
112
113 /* Store the declared LDS size into tgsi_shader_info for the shader
114 * cache to include it.
115 */
116 sel.info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
117
118 sel.type = PIPE_SHADER_COMPUTE;
119 si_get_active_slot_masks(&sel.info,
120 &program->active_const_and_shader_buffers,
121 &program->active_samplers_and_images);
122
123 program->shader.selector = &sel;
124 program->shader.is_monolithic = true;
125 program->uses_grid_size = sel.info.uses_grid_size;
126 program->uses_block_size = sel.info.uses_block_size;
127 program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
128 program->uses_bindless_images = sel.info.uses_bindless_images;
129 program->variable_group_size =
130 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
131
132 void *ir_binary = si_get_ir_binary(&sel);
133
134 /* Try to load the shader from the shader cache. */
135 mtx_lock(&sscreen->shader_cache_mutex);
136
137 if (ir_binary &&
138 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
139 mtx_unlock(&sscreen->shader_cache_mutex);
140
141 si_shader_dump_stats_for_shader_db(shader, debug);
142 si_shader_dump(sscreen, shader, debug, PIPE_SHADER_COMPUTE,
143 stderr, true);
144
145 if (si_shader_binary_upload(sscreen, shader))
146 program->shader.compilation_failed = true;
147 } else {
148 mtx_unlock(&sscreen->shader_cache_mutex);
149
150 if (si_shader_create(sscreen, compiler, &program->shader, debug)) {
151 program->shader.compilation_failed = true;
152
153 if (program->ir_type == PIPE_SHADER_IR_TGSI)
154 FREE(program->ir.tgsi);
155 program->shader.selector = NULL;
156 return;
157 }
158
159 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
160 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
161 (sel.info.uses_grid_size ? 3 : 0) +
162 (sel.info.uses_block_size ? 3 : 0);
163
164 shader->config.rsrc1 =
165 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
166 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
167 S_00B848_DX10_CLAMP(1) |
168 S_00B848_FLOAT_MODE(shader->config.float_mode);
169
170 shader->config.rsrc2 =
171 S_00B84C_USER_SGPR(user_sgprs) |
172 S_00B84C_SCRATCH_EN(scratch_enabled) |
173 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
174 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
175 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
176 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
177 sel.info.uses_thread_id[1] ? 1 : 0) |
178 S_00B84C_LDS_SIZE(shader->config.lds_size);
179
180 if (ir_binary) {
181 mtx_lock(&sscreen->shader_cache_mutex);
182 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
183 FREE(ir_binary);
184 mtx_unlock(&sscreen->shader_cache_mutex);
185 }
186 }
187
188 if (program->ir_type == PIPE_SHADER_IR_TGSI)
189 FREE(program->ir.tgsi);
190
191 program->shader.selector = NULL;
192 }
193
194 static void *si_create_compute_state(
195 struct pipe_context *ctx,
196 const struct pipe_compute_state *cso)
197 {
198 struct si_context *sctx = (struct si_context *)ctx;
199 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
200 struct si_compute *program = CALLOC_STRUCT(si_compute);
201
202 pipe_reference_init(&program->reference, 1);
203 program->screen = (struct si_screen *)ctx->screen;
204 program->ir_type = cso->ir_type;
205 program->local_size = cso->req_local_mem;
206 program->private_size = cso->req_private_mem;
207 program->input_size = cso->req_input_mem;
208 program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
209
210 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
211 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
212 program->ir.tgsi = tgsi_dup_tokens(cso->prog);
213 if (!program->ir.tgsi) {
214 FREE(program);
215 return NULL;
216 }
217 } else {
218 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
219 program->ir.nir = (struct nir_shader *) cso->prog;
220 }
221
222 program->compiler_ctx_state.debug = sctx->debug;
223 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
224 p_atomic_inc(&sscreen->num_shaders_created);
225
226 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
227 &program->ready,
228 &program->compiler_ctx_state,
229 program, si_create_compute_state_async);
230 } else {
231 const struct pipe_llvm_program_header *header;
232 const char *code;
233 header = cso->prog;
234 code = cso->prog + sizeof(struct pipe_llvm_program_header);
235
236 ac_elf_read(code, header->num_bytes, &program->shader.binary);
237 if (program->use_code_object_v2) {
238 const amd_kernel_code_t *code_object =
239 si_compute_get_code_object(program, 0);
240 code_object_to_config(code_object, &program->shader.config);
241 } else {
242 si_shader_binary_read_config(&program->shader.binary,
243 &program->shader.config, 0);
244 }
245 si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
246 PIPE_SHADER_COMPUTE, stderr, true);
247 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
248 fprintf(stderr, "LLVM failed to upload shader\n");
249 FREE(program);
250 return NULL;
251 }
252 }
253
254 return program;
255 }
256
257 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
258 {
259 struct si_context *sctx = (struct si_context*)ctx;
260 struct si_compute *program = (struct si_compute*)state;
261
262 sctx->cs_shader_state.program = program;
263 if (!program)
264 return;
265
266 /* Wait because we need active slot usage masks. */
267 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
268 util_queue_fence_wait(&program->ready);
269
270 si_set_active_descriptors(sctx,
271 SI_DESCS_FIRST_COMPUTE +
272 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
273 program->active_const_and_shader_buffers);
274 si_set_active_descriptors(sctx,
275 SI_DESCS_FIRST_COMPUTE +
276 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
277 program->active_samplers_and_images);
278 }
279
280 static void si_set_global_binding(
281 struct pipe_context *ctx, unsigned first, unsigned n,
282 struct pipe_resource **resources,
283 uint32_t **handles)
284 {
285 unsigned i;
286 struct si_context *sctx = (struct si_context*)ctx;
287 struct si_compute *program = sctx->cs_shader_state.program;
288
289 assert(first + n <= MAX_GLOBAL_BUFFERS);
290
291 if (!resources) {
292 for (i = 0; i < n; i++) {
293 pipe_resource_reference(&program->global_buffers[first + i], NULL);
294 }
295 return;
296 }
297
298 for (i = 0; i < n; i++) {
299 uint64_t va;
300 uint32_t offset;
301 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
302 va = r600_resource(resources[i])->gpu_address;
303 offset = util_le32_to_cpu(*handles[i]);
304 va += offset;
305 va = util_cpu_to_le64(va);
306 memcpy(handles[i], &va, sizeof(va));
307 }
308 }
309
310 static void si_initialize_compute(struct si_context *sctx)
311 {
312 struct radeon_cmdbuf *cs = sctx->gfx_cs;
313 uint64_t bc_va;
314
315 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
316 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
317 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
318 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
319
320 if (sctx->chip_class >= CIK) {
321 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
322 radeon_set_sh_reg_seq(cs,
323 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
324 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
325 S_00B864_SH1_CU_EN(0xffff));
326 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
327 S_00B868_SH1_CU_EN(0xffff));
328 }
329
330 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
331 * and is now per pipe, so it should be handled in the
332 * kernel if we want to use something other than the default value,
333 * which is now 0x22f.
334 */
335 if (sctx->chip_class <= SI) {
336 /* XXX: This should be:
337 * (number of compute units) * 4 * (waves per simd) - 1 */
338
339 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
340 0x190 /* Default value */);
341 }
342
343 /* Set the pointer to border colors. */
344 bc_va = sctx->border_color_buffer->gpu_address;
345
346 if (sctx->chip_class >= CIK) {
347 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
348 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
349 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
350 } else {
351 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
352 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
353 bc_va >> 8);
354 }
355 }
356
357 sctx->cs_shader_state.emitted_program = NULL;
358 sctx->cs_shader_state.initialized = true;
359 }
360
361 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
362 struct si_shader *shader,
363 struct si_shader_config *config)
364 {
365 uint64_t scratch_bo_size, scratch_needed;
366 scratch_bo_size = 0;
367 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
368 if (sctx->compute_scratch_buffer)
369 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
370
371 if (scratch_bo_size < scratch_needed) {
372 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
373
374 sctx->compute_scratch_buffer =
375 si_aligned_buffer_create(&sctx->screen->b,
376 SI_RESOURCE_FLAG_UNMAPPABLE,
377 PIPE_USAGE_DEFAULT,
378 scratch_needed, 256);
379
380 if (!sctx->compute_scratch_buffer)
381 return false;
382 }
383
384 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
385 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
386
387 si_shader_apply_scratch_relocs(shader, scratch_va);
388
389 if (si_shader_binary_upload(sctx->screen, shader))
390 return false;
391
392 r600_resource_reference(&shader->scratch_bo,
393 sctx->compute_scratch_buffer);
394 }
395
396 return true;
397 }
398
399 static bool si_switch_compute_shader(struct si_context *sctx,
400 struct si_compute *program,
401 struct si_shader *shader,
402 const amd_kernel_code_t *code_object,
403 unsigned offset)
404 {
405 struct radeon_cmdbuf *cs = sctx->gfx_cs;
406 struct si_shader_config inline_config = {0};
407 struct si_shader_config *config;
408 uint64_t shader_va;
409
410 if (sctx->cs_shader_state.emitted_program == program &&
411 sctx->cs_shader_state.offset == offset)
412 return true;
413
414 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
415 config = &shader->config;
416 } else {
417 unsigned lds_blocks;
418
419 config = &inline_config;
420 if (code_object) {
421 code_object_to_config(code_object, config);
422 } else {
423 si_shader_binary_read_config(&shader->binary, config, offset);
424 }
425
426 lds_blocks = config->lds_size;
427 /* XXX: We are over allocating LDS. For SI, the shader reports
428 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
429 * allocated in the shader and 4 bytes allocated by the state
430 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
431 */
432 if (sctx->chip_class <= SI) {
433 lds_blocks += align(program->local_size, 256) >> 8;
434 } else {
435 lds_blocks += align(program->local_size, 512) >> 9;
436 }
437
438 /* TODO: use si_multiwave_lds_size_workaround */
439 assert(lds_blocks <= 0xFF);
440
441 config->rsrc2 &= C_00B84C_LDS_SIZE;
442 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
443 }
444
445 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
446 return false;
447
448 if (shader->scratch_bo) {
449 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
450 "Total Scratch: %u bytes\n", sctx->scratch_waves,
451 config->scratch_bytes_per_wave,
452 config->scratch_bytes_per_wave *
453 sctx->scratch_waves);
454
455 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
456 shader->scratch_bo, RADEON_USAGE_READWRITE,
457 RADEON_PRIO_SCRATCH_BUFFER);
458 }
459
460 /* Prefetch the compute shader to TC L2.
461 *
462 * We should also prefetch graphics shaders if a compute dispatch was
463 * the last command, and the compute shader if a draw call was the last
464 * command. However, that would add more complexity and we're likely
465 * to get a shader state change in that case anyway.
466 */
467 if (sctx->chip_class >= CIK) {
468 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
469 0, program->shader.bo->b.b.width0);
470 }
471
472 shader_va = shader->bo->gpu_address + offset;
473 if (program->use_code_object_v2) {
474 /* Shader code is placed after the amd_kernel_code_t
475 * struct. */
476 shader_va += sizeof(amd_kernel_code_t);
477 }
478
479 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
480 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
481
482 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
483 radeon_emit(cs, shader_va >> 8);
484 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
485
486 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
487 radeon_emit(cs, config->rsrc1);
488 radeon_emit(cs, config->rsrc2);
489
490 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
491 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
492
493 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
494 S_00B860_WAVES(sctx->scratch_waves)
495 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
496
497 sctx->cs_shader_state.emitted_program = program;
498 sctx->cs_shader_state.offset = offset;
499 sctx->cs_shader_state.uses_scratch =
500 config->scratch_bytes_per_wave != 0;
501
502 return true;
503 }
504
505 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
506 const amd_kernel_code_t *code_object,
507 unsigned user_sgpr)
508 {
509 struct radeon_cmdbuf *cs = sctx->gfx_cs;
510 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
511
512 unsigned max_private_element_size = AMD_HSA_BITS_GET(
513 code_object->code_properties,
514 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
515
516 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
517 uint32_t scratch_dword1 =
518 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
519 S_008F04_SWIZZLE_ENABLE(1);
520
521 /* Disable address clamping */
522 uint32_t scratch_dword2 = 0xffffffff;
523 uint32_t scratch_dword3 =
524 S_008F0C_INDEX_STRIDE(3) |
525 S_008F0C_ADD_TID_ENABLE(1);
526
527 if (sctx->chip_class >= GFX9) {
528 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
529 } else {
530 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
531
532 if (sctx->chip_class < VI) {
533 /* BUF_DATA_FORMAT is ignored, but it cannot be
534 * BUF_DATA_FORMAT_INVALID. */
535 scratch_dword3 |=
536 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
537 }
538 }
539
540 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
541 (user_sgpr * 4), 4);
542 radeon_emit(cs, scratch_dword0);
543 radeon_emit(cs, scratch_dword1);
544 radeon_emit(cs, scratch_dword2);
545 radeon_emit(cs, scratch_dword3);
546 }
547
548 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
549 const amd_kernel_code_t *code_object,
550 const struct pipe_grid_info *info,
551 uint64_t kernel_args_va)
552 {
553 struct si_compute *program = sctx->cs_shader_state.program;
554 struct radeon_cmdbuf *cs = sctx->gfx_cs;
555
556 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
557 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
558 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
559 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
560 };
561
562 unsigned i, user_sgpr = 0;
563 if (AMD_HSA_BITS_GET(code_object->code_properties,
564 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
565 if (code_object->workitem_private_segment_byte_size > 0) {
566 setup_scratch_rsrc_user_sgprs(sctx, code_object,
567 user_sgpr);
568 }
569 user_sgpr += 4;
570 }
571
572 if (AMD_HSA_BITS_GET(code_object->code_properties,
573 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
574 struct dispatch_packet dispatch;
575 unsigned dispatch_offset;
576 struct r600_resource *dispatch_buf = NULL;
577 uint64_t dispatch_va;
578
579 /* Upload dispatch ptr */
580 memset(&dispatch, 0, sizeof(dispatch));
581
582 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
583 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
584 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
585
586 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
587 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
588 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
589
590 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
591 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
592
593 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
594
595 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
596 256, &dispatch, &dispatch_offset,
597 (struct pipe_resource**)&dispatch_buf);
598
599 if (!dispatch_buf) {
600 fprintf(stderr, "Error: Failed to allocate dispatch "
601 "packet.");
602 }
603 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
604 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
605
606 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
607
608 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
609 (user_sgpr * 4), 2);
610 radeon_emit(cs, dispatch_va);
611 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
612 S_008F04_STRIDE(0));
613
614 r600_resource_reference(&dispatch_buf, NULL);
615 user_sgpr += 2;
616 }
617
618 if (AMD_HSA_BITS_GET(code_object->code_properties,
619 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
620 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
621 (user_sgpr * 4), 2);
622 radeon_emit(cs, kernel_args_va);
623 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
624 S_008F04_STRIDE(0));
625 user_sgpr += 2;
626 }
627
628 for (i = 0; i < 3 && user_sgpr < 16; i++) {
629 if (code_object->code_properties & workgroup_count_masks[i]) {
630 radeon_set_sh_reg_seq(cs,
631 R_00B900_COMPUTE_USER_DATA_0 +
632 (user_sgpr * 4), 1);
633 radeon_emit(cs, info->grid[i]);
634 user_sgpr += 1;
635 }
636 }
637 }
638
639 static bool si_upload_compute_input(struct si_context *sctx,
640 const amd_kernel_code_t *code_object,
641 const struct pipe_grid_info *info)
642 {
643 struct radeon_cmdbuf *cs = sctx->gfx_cs;
644 struct si_compute *program = sctx->cs_shader_state.program;
645 struct r600_resource *input_buffer = NULL;
646 unsigned kernel_args_size;
647 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
648 uint32_t kernel_args_offset = 0;
649 uint32_t *kernel_args;
650 void *kernel_args_ptr;
651 uint64_t kernel_args_va;
652 unsigned i;
653
654 /* The extra num_work_size_bytes are for work group / work item size information */
655 kernel_args_size = program->input_size + num_work_size_bytes;
656
657 u_upload_alloc(sctx->b.const_uploader, 0, kernel_args_size,
658 sctx->screen->info.tcc_cache_line_size,
659 &kernel_args_offset,
660 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
661
662 if (unlikely(!kernel_args_ptr))
663 return false;
664
665 kernel_args = (uint32_t*)kernel_args_ptr;
666 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
667
668 if (!code_object) {
669 for (i = 0; i < 3; i++) {
670 kernel_args[i] = util_cpu_to_le32(info->grid[i]);
671 kernel_args[i + 3] = util_cpu_to_le32(info->grid[i] * info->block[i]);
672 kernel_args[i + 6] = util_cpu_to_le32(info->block[i]);
673 }
674 }
675
676 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
677 program->input_size);
678
679
680 for (i = 0; i < (kernel_args_size / 4); i++) {
681 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
682 kernel_args[i]);
683 }
684
685
686 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
687 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
688
689 if (code_object) {
690 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
691 } else {
692 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
693 radeon_emit(cs, kernel_args_va);
694 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
695 S_008F04_STRIDE(0));
696 }
697
698 r600_resource_reference(&input_buffer, NULL);
699
700 return true;
701 }
702
703 static void si_setup_tgsi_grid(struct si_context *sctx,
704 const struct pipe_grid_info *info)
705 {
706 struct si_compute *program = sctx->cs_shader_state.program;
707 struct radeon_cmdbuf *cs = sctx->gfx_cs;
708 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
709 4 * SI_NUM_RESOURCE_SGPRS;
710 unsigned block_size_reg = grid_size_reg +
711 /* 12 bytes = 3 dwords. */
712 12 * program->uses_grid_size;
713
714 if (info->indirect) {
715 if (program->uses_grid_size) {
716 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
717 uint64_t va = base_va + info->indirect_offset;
718 int i;
719
720 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
721 r600_resource(info->indirect),
722 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
723
724 for (i = 0; i < 3; ++i) {
725 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
726 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
727 COPY_DATA_DST_SEL(COPY_DATA_REG));
728 radeon_emit(cs, (va + 4 * i));
729 radeon_emit(cs, (va + 4 * i) >> 32);
730 radeon_emit(cs, (grid_size_reg >> 2) + i);
731 radeon_emit(cs, 0);
732 }
733 }
734 } else {
735 if (program->uses_grid_size) {
736 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
737 radeon_emit(cs, info->grid[0]);
738 radeon_emit(cs, info->grid[1]);
739 radeon_emit(cs, info->grid[2]);
740 }
741 if (program->variable_group_size && program->uses_block_size) {
742 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
743 radeon_emit(cs, info->block[0]);
744 radeon_emit(cs, info->block[1]);
745 radeon_emit(cs, info->block[2]);
746 }
747 }
748 }
749
750 static void si_emit_dispatch_packets(struct si_context *sctx,
751 const struct pipe_grid_info *info)
752 {
753 struct si_screen *sscreen = sctx->screen;
754 struct radeon_cmdbuf *cs = sctx->gfx_cs;
755 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
756 unsigned waves_per_threadgroup =
757 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
758 unsigned compute_resource_limits =
759 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
760
761 if (sctx->chip_class >= CIK) {
762 unsigned num_cu_per_se = sscreen->info.num_good_compute_units /
763 sscreen->info.max_se;
764
765 /* Force even distribution on all SIMDs in CU if the workgroup
766 * size is 64. This has shown some good improvements if # of CUs
767 * per SE is not a multiple of 4.
768 */
769 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
770 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
771 }
772
773 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
774 compute_resource_limits);
775
776 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
777 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
778 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
779 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
780
781 unsigned dispatch_initiator =
782 S_00B800_COMPUTE_SHADER_EN(1) |
783 S_00B800_FORCE_START_AT_000(1) |
784 /* If the KMD allows it (there is a KMD hw register for it),
785 * allow launching waves out-of-order. (same as Vulkan) */
786 S_00B800_ORDER_MODE(sctx->chip_class >= CIK);
787
788 if (info->indirect) {
789 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
790
791 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
792 r600_resource(info->indirect),
793 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
794
795 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
796 PKT3_SHADER_TYPE_S(1));
797 radeon_emit(cs, 1);
798 radeon_emit(cs, base_va);
799 radeon_emit(cs, base_va >> 32);
800
801 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
802 PKT3_SHADER_TYPE_S(1));
803 radeon_emit(cs, info->indirect_offset);
804 radeon_emit(cs, dispatch_initiator);
805 } else {
806 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
807 PKT3_SHADER_TYPE_S(1));
808 radeon_emit(cs, info->grid[0]);
809 radeon_emit(cs, info->grid[1]);
810 radeon_emit(cs, info->grid[2]);
811 radeon_emit(cs, dispatch_initiator);
812 }
813 }
814
815
816 static void si_launch_grid(
817 struct pipe_context *ctx, const struct pipe_grid_info *info)
818 {
819 struct si_context *sctx = (struct si_context*)ctx;
820 struct si_compute *program = sctx->cs_shader_state.program;
821 const amd_kernel_code_t *code_object =
822 si_compute_get_code_object(program, info->pc);
823 int i;
824 /* HW bug workaround when CS threadgroups > 256 threads and async
825 * compute isn't used, i.e. only one compute job can run at a time.
826 * If async compute is possible, the threadgroup size must be limited
827 * to 256 threads on all queues to avoid the bug.
828 * Only SI and certain CIK chips are affected.
829 */
830 bool cs_regalloc_hang =
831 (sctx->chip_class == SI ||
832 sctx->family == CHIP_BONAIRE ||
833 sctx->family == CHIP_KABINI) &&
834 info->block[0] * info->block[1] * info->block[2] > 256;
835
836 if (cs_regalloc_hang)
837 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
838 SI_CONTEXT_CS_PARTIAL_FLUSH;
839
840 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
841 program->shader.compilation_failed)
842 return;
843
844 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
845 si_update_fb_dirtiness_after_rendering(sctx);
846 sctx->last_num_draw_calls = sctx->num_draw_calls;
847 }
848
849 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
850
851 /* Add buffer sizes for memory checking in need_cs_space. */
852 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
853 /* TODO: add the scratch buffer */
854
855 if (info->indirect) {
856 si_context_add_resource_size(sctx, info->indirect);
857
858 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
859 if (sctx->chip_class <= VI &&
860 r600_resource(info->indirect)->TC_L2_dirty) {
861 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
862 r600_resource(info->indirect)->TC_L2_dirty = false;
863 }
864 }
865
866 si_need_gfx_cs_space(sctx);
867
868 if (!sctx->cs_shader_state.initialized)
869 si_initialize_compute(sctx);
870
871 if (sctx->flags)
872 si_emit_cache_flush(sctx);
873
874 if (!si_switch_compute_shader(sctx, program, &program->shader,
875 code_object, info->pc))
876 return;
877
878 si_upload_compute_shader_descriptors(sctx);
879 si_emit_compute_shader_pointers(sctx);
880
881 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
882 sctx->atoms.s.render_cond.emit(sctx);
883 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
884 }
885
886 if ((program->input_size ||
887 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
888 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
889 return;
890 }
891
892 /* Global buffers */
893 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
894 struct r600_resource *buffer =
895 r600_resource(program->global_buffers[i]);
896 if (!buffer) {
897 continue;
898 }
899 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
900 RADEON_USAGE_READWRITE,
901 RADEON_PRIO_COMPUTE_GLOBAL);
902 }
903
904 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
905 si_setup_tgsi_grid(sctx, info);
906
907 si_emit_dispatch_packets(sctx, info);
908
909 if (unlikely(sctx->current_saved_cs)) {
910 si_trace_emit(sctx);
911 si_log_compute_state(sctx, sctx->log);
912 }
913
914 sctx->compute_is_busy = true;
915 sctx->num_compute_calls++;
916 if (sctx->cs_shader_state.uses_scratch)
917 sctx->num_spill_compute_calls++;
918
919 if (cs_regalloc_hang)
920 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
921 }
922
923 void si_destroy_compute(struct si_compute *program)
924 {
925 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
926 util_queue_drop_job(&program->screen->shader_compiler_queue,
927 &program->ready);
928 util_queue_fence_destroy(&program->ready);
929 }
930
931 si_shader_destroy(&program->shader);
932 FREE(program);
933 }
934
935 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
936 struct si_compute *program = (struct si_compute *)state;
937 struct si_context *sctx = (struct si_context*)ctx;
938
939 if (!state)
940 return;
941
942 if (program == sctx->cs_shader_state.program)
943 sctx->cs_shader_state.program = NULL;
944
945 if (program == sctx->cs_shader_state.emitted_program)
946 sctx->cs_shader_state.emitted_program = NULL;
947
948 si_compute_reference(&program, NULL);
949 }
950
951 static void si_set_compute_resources(struct pipe_context * ctx_,
952 unsigned start, unsigned count,
953 struct pipe_surface ** surfaces) { }
954
955 void si_init_compute_functions(struct si_context *sctx)
956 {
957 sctx->b.create_compute_state = si_create_compute_state;
958 sctx->b.delete_compute_state = si_delete_compute_state;
959 sctx->b.bind_compute_state = si_bind_compute_state;
960 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
961 sctx->b.set_compute_resources = si_set_compute_resources;
962 sctx->b.set_global_binding = si_set_global_binding;
963 sctx->b.launch_grid = si_launch_grid;
964 }