2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
28 #include "radeon/radeon_elf_util.h"
30 #include "amd_kernel_code_t.h"
31 #include "radeon/r600_cs.h"
35 #define MAX_GLOBAL_BUFFERS 22
40 unsigned private_size
;
42 struct si_shader shader
;
44 struct pipe_resource
*global_buffers
[MAX_GLOBAL_BUFFERS
];
45 unsigned use_code_object_v2
: 1;
46 unsigned variable_group_size
: 1;
49 struct dispatch_packet
{
52 uint16_t workgroup_size_x
;
53 uint16_t workgroup_size_y
;
54 uint16_t workgroup_size_z
;
59 uint32_t private_segment_size
;
60 uint32_t group_segment_size
;
61 uint64_t kernel_object
;
62 uint64_t kernarg_address
;
66 static const amd_kernel_code_t
*si_compute_get_code_object(
67 const struct si_compute
*program
,
68 uint64_t symbol_offset
)
70 if (!program
->use_code_object_v2
) {
73 return (const amd_kernel_code_t
*)
74 (program
->shader
.binary
.code
+ symbol_offset
);
77 static void code_object_to_config(const amd_kernel_code_t
*code_object
,
78 struct si_shader_config
*out_config
) {
80 uint32_t rsrc1
= code_object
->compute_pgm_resource_registers
;
81 uint32_t rsrc2
= code_object
->compute_pgm_resource_registers
>> 32;
82 out_config
->num_sgprs
= code_object
->wavefront_sgpr_count
;
83 out_config
->num_vgprs
= code_object
->workitem_vgpr_count
;
84 out_config
->float_mode
= G_00B028_FLOAT_MODE(rsrc1
);
85 out_config
->rsrc1
= rsrc1
;
86 out_config
->lds_size
= MAX2(out_config
->lds_size
, G_00B84C_LDS_SIZE(rsrc2
));
87 out_config
->rsrc2
= rsrc2
;
88 out_config
->scratch_bytes_per_wave
=
89 align(code_object
->workitem_private_segment_byte_size
* 64, 1024);
92 static void *si_create_compute_state(
93 struct pipe_context
*ctx
,
94 const struct pipe_compute_state
*cso
)
96 struct si_context
*sctx
= (struct si_context
*)ctx
;
97 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
98 struct si_compute
*program
= CALLOC_STRUCT(si_compute
);
99 struct si_shader
*shader
= &program
->shader
;
102 program
->ir_type
= cso
->ir_type
;
103 program
->local_size
= cso
->req_local_mem
;
104 program
->private_size
= cso
->req_private_mem
;
105 program
->input_size
= cso
->req_input_mem
;
106 program
->use_code_object_v2
= HAVE_LLVM
>= 0x0400 &&
107 cso
->ir_type
== PIPE_SHADER_IR_NATIVE
;
110 if (cso
->ir_type
== PIPE_SHADER_IR_TGSI
) {
111 struct si_shader_selector sel
;
112 bool scratch_enabled
;
114 memset(&sel
, 0, sizeof(sel
));
116 sel
.tokens
= tgsi_dup_tokens(cso
->prog
);
122 tgsi_scan_shader(cso
->prog
, &sel
.info
);
123 sel
.type
= PIPE_SHADER_COMPUTE
;
124 sel
.local_size
= cso
->req_local_mem
;
126 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
128 program
->shader
.selector
= &sel
;
129 program
->shader
.is_monolithic
= true;
131 if (si_shader_create(sscreen
, sctx
->tm
, &program
->shader
,
138 scratch_enabled
= shader
->config
.scratch_bytes_per_wave
> 0;
140 shader
->config
.rsrc1
=
141 S_00B848_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
142 S_00B848_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
143 S_00B848_DX10_CLAMP(1) |
144 S_00B848_FLOAT_MODE(shader
->config
.float_mode
);
146 shader
->config
.rsrc2
= S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR
) |
147 S_00B84C_SCRATCH_EN(scratch_enabled
) |
148 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
149 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
150 S_00B84C_LDS_SIZE(shader
->config
.lds_size
);
152 program
->variable_group_size
=
153 sel
.info
.properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0;
156 program
->shader
.selector
= NULL
;
158 const struct pipe_llvm_program_header
*header
;
161 code
= cso
->prog
+ sizeof(struct pipe_llvm_program_header
);
163 radeon_elf_read(code
, header
->num_bytes
, &program
->shader
.binary
);
164 if (program
->use_code_object_v2
) {
165 const amd_kernel_code_t
*code_object
=
166 si_compute_get_code_object(program
, 0);
167 code_object_to_config(code_object
, &program
->shader
.config
);
169 si_shader_binary_read_config(&program
->shader
.binary
,
170 &program
->shader
.config
, 0);
172 si_shader_dump(sctx
->screen
, &program
->shader
, &sctx
->b
.debug
,
173 PIPE_SHADER_COMPUTE
, stderr
, true);
174 if (si_shader_binary_upload(sctx
->screen
, &program
->shader
) < 0) {
175 fprintf(stderr
, "LLVM failed to upload shader\n");
184 static void si_bind_compute_state(struct pipe_context
*ctx
, void *state
)
186 struct si_context
*sctx
= (struct si_context
*)ctx
;
187 sctx
->cs_shader_state
.program
= (struct si_compute
*)state
;
190 static void si_set_global_binding(
191 struct pipe_context
*ctx
, unsigned first
, unsigned n
,
192 struct pipe_resource
**resources
,
196 struct si_context
*sctx
= (struct si_context
*)ctx
;
197 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
199 assert(first
+ n
<= MAX_GLOBAL_BUFFERS
);
202 for (i
= 0; i
< n
; i
++) {
203 pipe_resource_reference(&program
->global_buffers
[first
+ i
], NULL
);
208 for (i
= 0; i
< n
; i
++) {
211 pipe_resource_reference(&program
->global_buffers
[first
+ i
], resources
[i
]);
212 va
= r600_resource(resources
[i
])->gpu_address
;
213 offset
= util_le32_to_cpu(*handles
[i
]);
215 va
= util_cpu_to_le64(va
);
216 memcpy(handles
[i
], &va
, sizeof(va
));
220 static void si_initialize_compute(struct si_context
*sctx
)
222 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
225 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
230 radeon_set_sh_reg_seq(cs
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
, 2);
231 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
232 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
233 radeon_emit(cs
, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
235 if (sctx
->b
.chip_class
>= CIK
) {
236 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
237 radeon_set_sh_reg_seq(cs
,
238 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
239 radeon_emit(cs
, S_00B864_SH0_CU_EN(0xffff) |
240 S_00B864_SH1_CU_EN(0xffff));
241 radeon_emit(cs
, S_00B868_SH0_CU_EN(0xffff) |
242 S_00B868_SH1_CU_EN(0xffff));
245 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
246 * and is now per pipe, so it should be handled in the
247 * kernel if we want to use something other than the default value,
248 * which is now 0x22f.
250 if (sctx
->b
.chip_class
<= SI
) {
251 /* XXX: This should be:
252 * (number of compute units) * 4 * (waves per simd) - 1 */
254 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
255 0x190 /* Default value */);
258 /* Set the pointer to border colors. */
259 bc_va
= sctx
->border_color_buffer
->gpu_address
;
261 if (sctx
->b
.chip_class
>= CIK
) {
262 radeon_set_uconfig_reg_seq(cs
, R_030E00_TA_CS_BC_BASE_ADDR
, 2);
263 radeon_emit(cs
, bc_va
>> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
264 radeon_emit(cs
, bc_va
>> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
266 if (sctx
->screen
->b
.info
.drm_major
== 3 ||
267 (sctx
->screen
->b
.info
.drm_major
== 2 &&
268 sctx
->screen
->b
.info
.drm_minor
>= 48)) {
269 radeon_set_config_reg(cs
, R_00950C_TA_CS_BC_BASE_ADDR
,
274 sctx
->cs_shader_state
.emitted_program
= NULL
;
275 sctx
->cs_shader_state
.initialized
= true;
278 static bool si_setup_compute_scratch_buffer(struct si_context
*sctx
,
279 struct si_shader
*shader
,
280 struct si_shader_config
*config
)
282 uint64_t scratch_bo_size
, scratch_needed
;
284 scratch_needed
= config
->scratch_bytes_per_wave
* sctx
->scratch_waves
;
285 if (sctx
->compute_scratch_buffer
)
286 scratch_bo_size
= sctx
->compute_scratch_buffer
->b
.b
.width0
;
288 if (scratch_bo_size
< scratch_needed
) {
289 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
291 sctx
->compute_scratch_buffer
= (struct r600_resource
*)
292 pipe_buffer_create(&sctx
->screen
->b
.b
, 0,
293 PIPE_USAGE_DEFAULT
, scratch_needed
);
295 if (!sctx
->compute_scratch_buffer
)
299 if (sctx
->compute_scratch_buffer
!= shader
->scratch_bo
&& scratch_needed
) {
300 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
302 si_shader_apply_scratch_relocs(sctx
, shader
, config
, scratch_va
);
304 if (si_shader_binary_upload(sctx
->screen
, shader
))
307 r600_resource_reference(&shader
->scratch_bo
,
308 sctx
->compute_scratch_buffer
);
314 static bool si_switch_compute_shader(struct si_context
*sctx
,
315 struct si_compute
*program
,
316 struct si_shader
*shader
,
317 const amd_kernel_code_t
*code_object
,
320 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
321 struct si_shader_config inline_config
= {0};
322 struct si_shader_config
*config
;
325 if (sctx
->cs_shader_state
.emitted_program
== program
&&
326 sctx
->cs_shader_state
.offset
== offset
)
329 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
) {
330 config
= &shader
->config
;
334 config
= &inline_config
;
336 code_object_to_config(code_object
, config
);
338 si_shader_binary_read_config(&shader
->binary
, config
, offset
);
341 lds_blocks
= config
->lds_size
;
342 /* XXX: We are over allocating LDS. For SI, the shader reports
343 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
344 * allocated in the shader and 4 bytes allocated by the state
345 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
347 if (sctx
->b
.chip_class
<= SI
) {
348 lds_blocks
+= align(program
->local_size
, 256) >> 8;
350 lds_blocks
+= align(program
->local_size
, 512) >> 9;
353 /* TODO: use si_multiwave_lds_size_workaround */
354 assert(lds_blocks
<= 0xFF);
356 config
->rsrc2
&= C_00B84C_LDS_SIZE
;
357 config
->rsrc2
|= S_00B84C_LDS_SIZE(lds_blocks
);
360 if (!si_setup_compute_scratch_buffer(sctx
, shader
, config
))
363 if (shader
->scratch_bo
) {
364 COMPUTE_DBG(sctx
->screen
, "Waves: %u; Scratch per wave: %u bytes; "
365 "Total Scratch: %u bytes\n", sctx
->scratch_waves
,
366 config
->scratch_bytes_per_wave
,
367 config
->scratch_bytes_per_wave
*
368 sctx
->scratch_waves
);
370 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
371 shader
->scratch_bo
, RADEON_USAGE_READWRITE
,
372 RADEON_PRIO_SCRATCH_BUFFER
);
375 /* Prefetch the compute shader to TC L2.
377 * We should also prefetch graphics shaders if a compute dispatch was
378 * the last command, and the compute shader if a draw call was the last
379 * command. However, that would add more complexity and we're likely
380 * to get a shader state change in that case anyway.
382 if (sctx
->b
.chip_class
>= CIK
) {
383 cik_prefetch_TC_L2_async(sctx
, &program
->shader
.bo
->b
.b
,
384 0, program
->shader
.bo
->b
.b
.width0
);
387 shader_va
= shader
->bo
->gpu_address
+ offset
;
388 if (program
->use_code_object_v2
) {
389 /* Shader code is placed after the amd_kernel_code_t
391 shader_va
+= sizeof(amd_kernel_code_t
);
394 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, shader
->bo
,
395 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
397 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
398 radeon_emit(cs
, shader_va
>> 8);
399 radeon_emit(cs
, shader_va
>> 40);
401 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
402 radeon_emit(cs
, config
->rsrc1
);
403 radeon_emit(cs
, config
->rsrc2
);
405 COMPUTE_DBG(sctx
->screen
, "COMPUTE_PGM_RSRC1: 0x%08x "
406 "COMPUTE_PGM_RSRC2: 0x%08x\n", config
->rsrc1
, config
->rsrc2
);
408 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
409 S_00B860_WAVES(sctx
->scratch_waves
)
410 | S_00B860_WAVESIZE(config
->scratch_bytes_per_wave
>> 10));
412 sctx
->cs_shader_state
.emitted_program
= program
;
413 sctx
->cs_shader_state
.offset
= offset
;
414 sctx
->cs_shader_state
.uses_scratch
=
415 config
->scratch_bytes_per_wave
!= 0;
420 static void setup_scratch_rsrc_user_sgprs(struct si_context
*sctx
,
421 const amd_kernel_code_t
*code_object
,
424 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
425 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
427 unsigned max_private_element_size
= AMD_HSA_BITS_GET(
428 code_object
->code_properties
,
429 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE
);
431 uint32_t scratch_dword0
= scratch_va
& 0xffffffff;
432 uint32_t scratch_dword1
=
433 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
434 S_008F04_SWIZZLE_ENABLE(1);
436 /* Disable address clamping */
437 uint32_t scratch_dword2
= 0xffffffff;
438 uint32_t scratch_dword3
=
439 S_008F0C_ELEMENT_SIZE(max_private_element_size
) |
440 S_008F0C_INDEX_STRIDE(3) |
441 S_008F0C_ADD_TID_ENABLE(1);
444 if (sctx
->screen
->b
.chip_class
< VI
) {
445 /* BUF_DATA_FORMAT is ignored, but it cannot be
446 BUF_DATA_FORMAT_INVALID. */
448 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8
);
451 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
453 radeon_emit(cs
, scratch_dword0
);
454 radeon_emit(cs
, scratch_dword1
);
455 radeon_emit(cs
, scratch_dword2
);
456 radeon_emit(cs
, scratch_dword3
);
459 static void si_setup_user_sgprs_co_v2(struct si_context
*sctx
,
460 const amd_kernel_code_t
*code_object
,
461 const struct pipe_grid_info
*info
,
462 uint64_t kernel_args_va
)
464 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
465 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
467 static const enum amd_code_property_mask_t workgroup_count_masks
[] = {
468 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X
,
469 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y
,
470 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
473 unsigned i
, user_sgpr
= 0;
474 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
475 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER
)) {
476 if (code_object
->workitem_private_segment_byte_size
> 0) {
477 setup_scratch_rsrc_user_sgprs(sctx
, code_object
,
483 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
484 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR
)) {
485 struct dispatch_packet dispatch
;
486 unsigned dispatch_offset
;
487 struct r600_resource
*dispatch_buf
= NULL
;
488 uint64_t dispatch_va
;
490 /* Upload dispatch ptr */
491 memset(&dispatch
, 0, sizeof(dispatch
));
493 dispatch
.workgroup_size_x
= info
->block
[0];
494 dispatch
.workgroup_size_y
= info
->block
[1];
495 dispatch
.workgroup_size_z
= info
->block
[2];
497 dispatch
.grid_size_x
= info
->grid
[0] * info
->block
[0];
498 dispatch
.grid_size_y
= info
->grid
[1] * info
->block
[1];
499 dispatch
.grid_size_z
= info
->grid
[2] * info
->block
[2];
501 dispatch
.private_segment_size
= program
->private_size
;
502 dispatch
.group_segment_size
= program
->local_size
;
504 dispatch
.kernarg_address
= kernel_args_va
;
506 u_upload_data(sctx
->b
.b
.stream_uploader
, 0, sizeof(dispatch
),
507 256, &dispatch
, &dispatch_offset
,
508 (struct pipe_resource
**)&dispatch_buf
);
511 fprintf(stderr
, "Error: Failed to allocate dispatch "
514 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, dispatch_buf
,
515 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
517 dispatch_va
= dispatch_buf
->gpu_address
+ dispatch_offset
;
519 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
521 radeon_emit(cs
, dispatch_va
);
522 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(dispatch_va
>> 32) |
525 r600_resource_reference(&dispatch_buf
, NULL
);
529 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
530 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR
)) {
531 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
533 radeon_emit(cs
, kernel_args_va
);
534 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) |
539 for (i
= 0; i
< 3 && user_sgpr
< 16; i
++) {
540 if (code_object
->code_properties
& workgroup_count_masks
[i
]) {
541 radeon_set_sh_reg_seq(cs
,
542 R_00B900_COMPUTE_USER_DATA_0
+
544 radeon_emit(cs
, info
->grid
[i
]);
550 static void si_upload_compute_input(struct si_context
*sctx
,
551 const amd_kernel_code_t
*code_object
,
552 const struct pipe_grid_info
*info
)
554 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
555 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
556 struct r600_resource
*input_buffer
= NULL
;
557 unsigned kernel_args_size
;
558 unsigned num_work_size_bytes
= program
->use_code_object_v2
? 0 : 36;
559 uint32_t kernel_args_offset
= 0;
560 uint32_t *kernel_args
;
561 void *kernel_args_ptr
;
562 uint64_t kernel_args_va
;
565 /* The extra num_work_size_bytes are for work group / work item size information */
566 kernel_args_size
= program
->input_size
+ num_work_size_bytes
;
568 u_upload_alloc(sctx
->b
.b
.stream_uploader
, 0, kernel_args_size
, 256,
570 (struct pipe_resource
**)&input_buffer
, &kernel_args_ptr
);
572 kernel_args
= (uint32_t*)kernel_args_ptr
;
573 kernel_args_va
= input_buffer
->gpu_address
+ kernel_args_offset
;
576 for (i
= 0; i
< 3; i
++) {
577 kernel_args
[i
] = info
->grid
[i
];
578 kernel_args
[i
+ 3] = info
->grid
[i
] * info
->block
[i
];
579 kernel_args
[i
+ 6] = info
->block
[i
];
583 memcpy(kernel_args
+ (num_work_size_bytes
/ 4), info
->input
,
584 program
->input_size
);
587 for (i
= 0; i
< (kernel_args_size
/ 4); i
++) {
588 COMPUTE_DBG(sctx
->screen
, "input %u : %u\n", i
,
593 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, input_buffer
,
594 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
597 si_setup_user_sgprs_co_v2(sctx
, code_object
, info
, kernel_args_va
);
599 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
600 radeon_emit(cs
, kernel_args_va
);
601 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) |
605 r600_resource_reference(&input_buffer
, NULL
);
608 static void si_setup_tgsi_grid(struct si_context
*sctx
,
609 const struct pipe_grid_info
*info
)
611 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
612 unsigned grid_size_reg
= R_00B900_COMPUTE_USER_DATA_0
+
613 4 * SI_SGPR_GRID_SIZE
;
615 if (info
->indirect
) {
616 uint64_t base_va
= r600_resource(info
->indirect
)->gpu_address
;
617 uint64_t va
= base_va
+ info
->indirect_offset
;
620 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
621 (struct r600_resource
*)info
->indirect
,
622 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
624 for (i
= 0; i
< 3; ++i
) {
625 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
626 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
627 COPY_DATA_DST_SEL(COPY_DATA_REG
));
628 radeon_emit(cs
, (va
+ 4 * i
));
629 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
630 radeon_emit(cs
, (grid_size_reg
>> 2) + i
);
634 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
636 radeon_set_sh_reg_seq(cs
, grid_size_reg
, program
->variable_group_size
? 6 : 3);
637 radeon_emit(cs
, info
->grid
[0]);
638 radeon_emit(cs
, info
->grid
[1]);
639 radeon_emit(cs
, info
->grid
[2]);
640 if (program
->variable_group_size
) {
641 radeon_emit(cs
, info
->block
[0]);
642 radeon_emit(cs
, info
->block
[1]);
643 radeon_emit(cs
, info
->block
[2]);
648 static void si_emit_dispatch_packets(struct si_context
*sctx
,
649 const struct pipe_grid_info
*info
)
651 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
652 bool render_cond_bit
= sctx
->b
.render_cond
&& !sctx
->b
.render_cond_force_off
;
653 unsigned waves_per_threadgroup
=
654 DIV_ROUND_UP(info
->block
[0] * info
->block
[1] * info
->block
[2], 64);
656 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
657 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0));
659 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
660 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(info
->block
[0]));
661 radeon_emit(cs
, S_00B820_NUM_THREAD_FULL(info
->block
[1]));
662 radeon_emit(cs
, S_00B824_NUM_THREAD_FULL(info
->block
[2]));
664 if (info
->indirect
) {
665 uint64_t base_va
= r600_resource(info
->indirect
)->gpu_address
;
667 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
668 (struct r600_resource
*)info
->indirect
,
669 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
671 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
672 PKT3_SHADER_TYPE_S(1));
674 radeon_emit(cs
, base_va
);
675 radeon_emit(cs
, base_va
>> 32);
677 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, render_cond_bit
) |
678 PKT3_SHADER_TYPE_S(1));
679 radeon_emit(cs
, info
->indirect_offset
);
682 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, render_cond_bit
) |
683 PKT3_SHADER_TYPE_S(1));
684 radeon_emit(cs
, info
->grid
[0]);
685 radeon_emit(cs
, info
->grid
[1]);
686 radeon_emit(cs
, info
->grid
[2]);
692 static void si_launch_grid(
693 struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
695 struct si_context
*sctx
= (struct si_context
*)ctx
;
696 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
697 const amd_kernel_code_t
*code_object
=
698 si_compute_get_code_object(program
, info
->pc
);
700 /* HW bug workaround when CS threadgroups > 256 threads and async
701 * compute isn't used, i.e. only one compute job can run at a time.
702 * If async compute is possible, the threadgroup size must be limited
703 * to 256 threads on all queues to avoid the bug.
704 * Only SI and certain CIK chips are affected.
706 bool cs_regalloc_hang
=
707 (sctx
->b
.chip_class
== SI
||
708 sctx
->b
.family
== CHIP_BONAIRE
||
709 sctx
->b
.family
== CHIP_KABINI
) &&
710 info
->block
[0] * info
->block
[1] * info
->block
[2] > 256;
712 if (cs_regalloc_hang
)
713 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
714 SI_CONTEXT_CS_PARTIAL_FLUSH
;
716 si_decompress_compute_textures(sctx
);
718 /* Add buffer sizes for memory checking in need_cs_space. */
719 r600_context_add_resource_size(ctx
, &program
->shader
.bo
->b
.b
);
720 /* TODO: add the scratch buffer */
722 if (info
->indirect
) {
723 r600_context_add_resource_size(ctx
, info
->indirect
);
725 /* The hw doesn't read the indirect buffer via TC L2. */
726 if (r600_resource(info
->indirect
)->TC_L2_dirty
) {
727 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
728 r600_resource(info
->indirect
)->TC_L2_dirty
= false;
732 si_need_cs_space(sctx
);
734 if (!sctx
->cs_shader_state
.initialized
)
735 si_initialize_compute(sctx
);
738 si_emit_cache_flush(sctx
);
740 if (!si_switch_compute_shader(sctx
, program
, &program
->shader
,
741 code_object
, info
->pc
))
744 si_upload_compute_shader_descriptors(sctx
);
745 si_emit_compute_shader_userdata(sctx
);
747 if (si_is_atom_dirty(sctx
, sctx
->atoms
.s
.render_cond
)) {
748 sctx
->atoms
.s
.render_cond
->emit(&sctx
->b
,
749 sctx
->atoms
.s
.render_cond
);
750 si_set_atom_dirty(sctx
, sctx
->atoms
.s
.render_cond
, false);
753 if (program
->input_size
|| program
->ir_type
== PIPE_SHADER_IR_NATIVE
)
754 si_upload_compute_input(sctx
, code_object
, info
);
757 for (i
= 0; i
< MAX_GLOBAL_BUFFERS
; i
++) {
758 struct r600_resource
*buffer
=
759 (struct r600_resource
*)program
->global_buffers
[i
];
763 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, buffer
,
764 RADEON_USAGE_READWRITE
,
765 RADEON_PRIO_COMPUTE_GLOBAL
);
768 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
)
769 si_setup_tgsi_grid(sctx
, info
);
771 si_ce_pre_draw_synchronization(sctx
);
773 si_emit_dispatch_packets(sctx
, info
);
775 si_ce_post_draw_synchronization(sctx
);
777 sctx
->compute_is_busy
= true;
778 sctx
->b
.num_compute_calls
++;
779 if (sctx
->cs_shader_state
.uses_scratch
)
780 sctx
->b
.num_spill_compute_calls
++;
782 if (cs_regalloc_hang
)
783 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
787 static void si_delete_compute_state(struct pipe_context
*ctx
, void* state
){
788 struct si_compute
*program
= (struct si_compute
*)state
;
789 struct si_context
*sctx
= (struct si_context
*)ctx
;
795 if (program
== sctx
->cs_shader_state
.program
)
796 sctx
->cs_shader_state
.program
= NULL
;
798 if (program
== sctx
->cs_shader_state
.emitted_program
)
799 sctx
->cs_shader_state
.emitted_program
= NULL
;
801 si_shader_destroy(&program
->shader
);
805 static void si_set_compute_resources(struct pipe_context
* ctx_
,
806 unsigned start
, unsigned count
,
807 struct pipe_surface
** surfaces
) { }
809 void si_init_compute_functions(struct si_context
*sctx
)
811 sctx
->b
.b
.create_compute_state
= si_create_compute_state
;
812 sctx
->b
.b
.delete_compute_state
= si_delete_compute_state
;
813 sctx
->b
.b
.bind_compute_state
= si_bind_compute_state
;
814 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
815 sctx
->b
.b
.set_compute_resources
= si_set_compute_resources
;
816 sctx
->b
.b
.set_global_binding
= si_set_global_binding
;
817 sctx
->b
.b
.launch_grid
= si_launch_grid
;