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radeonsi: remove unused atom parameter from si_atom::emit
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "tgsi/tgsi_parse.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30
31 #include "amd_kernel_code_t.h"
32 #include "si_build_pm4.h"
33 #include "si_compute.h"
34
35 #define COMPUTE_DBG(rscreen, fmt, args...) \
36 do { \
37 if ((rscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
38 } while (0);
39
40 struct dispatch_packet {
41 uint16_t header;
42 uint16_t setup;
43 uint16_t workgroup_size_x;
44 uint16_t workgroup_size_y;
45 uint16_t workgroup_size_z;
46 uint16_t reserved0;
47 uint32_t grid_size_x;
48 uint32_t grid_size_y;
49 uint32_t grid_size_z;
50 uint32_t private_segment_size;
51 uint32_t group_segment_size;
52 uint64_t kernel_object;
53 uint64_t kernarg_address;
54 uint64_t reserved2;
55 };
56
57 static const amd_kernel_code_t *si_compute_get_code_object(
58 const struct si_compute *program,
59 uint64_t symbol_offset)
60 {
61 if (!program->use_code_object_v2) {
62 return NULL;
63 }
64 return (const amd_kernel_code_t*)
65 (program->shader.binary.code + symbol_offset);
66 }
67
68 static void code_object_to_config(const amd_kernel_code_t *code_object,
69 struct si_shader_config *out_config) {
70
71 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
72 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
73 out_config->num_sgprs = code_object->wavefront_sgpr_count;
74 out_config->num_vgprs = code_object->workitem_vgpr_count;
75 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
76 out_config->rsrc1 = rsrc1;
77 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
78 out_config->rsrc2 = rsrc2;
79 out_config->scratch_bytes_per_wave =
80 align(code_object->workitem_private_segment_byte_size * 64, 1024);
81 }
82
83 /* Asynchronous compute shader compilation. */
84 static void si_create_compute_state_async(void *job, int thread_index)
85 {
86 struct si_compute *program = (struct si_compute *)job;
87 struct si_shader *shader = &program->shader;
88 struct si_shader_selector sel;
89 LLVMTargetMachineRef tm;
90 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
91
92 assert(!debug->debug_message || debug->async);
93 assert(thread_index >= 0);
94 assert(thread_index < ARRAY_SIZE(program->screen->tm));
95 tm = program->screen->tm[thread_index];
96
97 memset(&sel, 0, sizeof(sel));
98
99 sel.screen = program->screen;
100
101 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
102 tgsi_scan_shader(program->ir.tgsi, &sel.info);
103 sel.tokens = program->ir.tgsi;
104 } else {
105 assert(program->ir_type == PIPE_SHADER_IR_NIR);
106 sel.nir = program->ir.nir;
107
108 si_nir_scan_shader(sel.nir, &sel.info);
109 si_lower_nir(&sel);
110 }
111
112
113 sel.type = PIPE_SHADER_COMPUTE;
114 sel.local_size = program->local_size;
115 si_get_active_slot_masks(&sel.info,
116 &program->active_const_and_shader_buffers,
117 &program->active_samplers_and_images);
118
119 program->shader.selector = &sel;
120 program->shader.is_monolithic = true;
121 program->uses_grid_size = sel.info.uses_grid_size;
122 program->uses_block_size = sel.info.uses_block_size;
123 program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
124 program->uses_bindless_images = sel.info.uses_bindless_images;
125
126 if (si_shader_create(program->screen, tm, &program->shader, debug)) {
127 program->shader.compilation_failed = true;
128 } else {
129 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
130 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
131 (sel.info.uses_grid_size ? 3 : 0) +
132 (sel.info.uses_block_size ? 3 : 0);
133
134 shader->config.rsrc1 =
135 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
136 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
137 S_00B848_DX10_CLAMP(1) |
138 S_00B848_FLOAT_MODE(shader->config.float_mode);
139
140 shader->config.rsrc2 =
141 S_00B84C_USER_SGPR(user_sgprs) |
142 S_00B84C_SCRATCH_EN(scratch_enabled) |
143 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
144 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
145 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
146 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
147 sel.info.uses_thread_id[1] ? 1 : 0) |
148 S_00B84C_LDS_SIZE(shader->config.lds_size);
149
150 program->variable_group_size =
151 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
152 }
153
154 if (program->ir_type == PIPE_SHADER_IR_TGSI)
155 FREE(program->ir.tgsi);
156
157 program->shader.selector = NULL;
158 }
159
160 static void *si_create_compute_state(
161 struct pipe_context *ctx,
162 const struct pipe_compute_state *cso)
163 {
164 struct si_context *sctx = (struct si_context *)ctx;
165 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
166 struct si_compute *program = CALLOC_STRUCT(si_compute);
167
168 pipe_reference_init(&program->reference, 1);
169 program->screen = (struct si_screen *)ctx->screen;
170 program->ir_type = cso->ir_type;
171 program->local_size = cso->req_local_mem;
172 program->private_size = cso->req_private_mem;
173 program->input_size = cso->req_input_mem;
174 program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
175
176 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
177 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
178 program->ir.tgsi = tgsi_dup_tokens(cso->prog);
179 if (!program->ir.tgsi) {
180 FREE(program);
181 return NULL;
182 }
183 } else {
184 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
185 program->ir.nir = (struct nir_shader *) cso->prog;
186 }
187
188 program->compiler_ctx_state.debug = sctx->debug;
189 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
190 p_atomic_inc(&sscreen->num_shaders_created);
191 util_queue_fence_init(&program->ready);
192
193 struct util_async_debug_callback async_debug;
194 bool wait =
195 (sctx->debug.debug_message && !sctx->debug.async) ||
196 sctx->is_debug ||
197 si_can_dump_shader(sscreen, PIPE_SHADER_COMPUTE);
198
199 if (wait) {
200 u_async_debug_init(&async_debug);
201 program->compiler_ctx_state.debug = async_debug.base;
202 }
203
204 util_queue_add_job(&sscreen->shader_compiler_queue,
205 program, &program->ready,
206 si_create_compute_state_async, NULL);
207
208 if (wait) {
209 util_queue_fence_wait(&program->ready);
210 u_async_debug_drain(&async_debug, &sctx->debug);
211 u_async_debug_cleanup(&async_debug);
212 }
213 } else {
214 const struct pipe_llvm_program_header *header;
215 const char *code;
216 header = cso->prog;
217 code = cso->prog + sizeof(struct pipe_llvm_program_header);
218
219 ac_elf_read(code, header->num_bytes, &program->shader.binary);
220 if (program->use_code_object_v2) {
221 const amd_kernel_code_t *code_object =
222 si_compute_get_code_object(program, 0);
223 code_object_to_config(code_object, &program->shader.config);
224 } else {
225 si_shader_binary_read_config(&program->shader.binary,
226 &program->shader.config, 0);
227 }
228 si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
229 PIPE_SHADER_COMPUTE, stderr, true);
230 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
231 fprintf(stderr, "LLVM failed to upload shader\n");
232 FREE(program);
233 return NULL;
234 }
235 }
236
237 return program;
238 }
239
240 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
241 {
242 struct si_context *sctx = (struct si_context*)ctx;
243 struct si_compute *program = (struct si_compute*)state;
244
245 sctx->cs_shader_state.program = program;
246 if (!program)
247 return;
248
249 /* Wait because we need active slot usage masks. */
250 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
251 util_queue_fence_wait(&program->ready);
252
253 si_set_active_descriptors(sctx,
254 SI_DESCS_FIRST_COMPUTE +
255 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
256 program->active_const_and_shader_buffers);
257 si_set_active_descriptors(sctx,
258 SI_DESCS_FIRST_COMPUTE +
259 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
260 program->active_samplers_and_images);
261 }
262
263 static void si_set_global_binding(
264 struct pipe_context *ctx, unsigned first, unsigned n,
265 struct pipe_resource **resources,
266 uint32_t **handles)
267 {
268 unsigned i;
269 struct si_context *sctx = (struct si_context*)ctx;
270 struct si_compute *program = sctx->cs_shader_state.program;
271
272 assert(first + n <= MAX_GLOBAL_BUFFERS);
273
274 if (!resources) {
275 for (i = 0; i < n; i++) {
276 pipe_resource_reference(&program->global_buffers[first + i], NULL);
277 }
278 return;
279 }
280
281 for (i = 0; i < n; i++) {
282 uint64_t va;
283 uint32_t offset;
284 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
285 va = r600_resource(resources[i])->gpu_address;
286 offset = util_le32_to_cpu(*handles[i]);
287 va += offset;
288 va = util_cpu_to_le64(va);
289 memcpy(handles[i], &va, sizeof(va));
290 }
291 }
292
293 static void si_initialize_compute(struct si_context *sctx)
294 {
295 struct radeon_winsys_cs *cs = sctx->gfx_cs;
296 uint64_t bc_va;
297
298 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
299 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
300 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
301 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
302
303 if (sctx->chip_class >= CIK) {
304 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
305 radeon_set_sh_reg_seq(cs,
306 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
307 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
308 S_00B864_SH1_CU_EN(0xffff));
309 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
310 S_00B868_SH1_CU_EN(0xffff));
311 }
312
313 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
314 * and is now per pipe, so it should be handled in the
315 * kernel if we want to use something other than the default value,
316 * which is now 0x22f.
317 */
318 if (sctx->chip_class <= SI) {
319 /* XXX: This should be:
320 * (number of compute units) * 4 * (waves per simd) - 1 */
321
322 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
323 0x190 /* Default value */);
324 }
325
326 /* Set the pointer to border colors. */
327 bc_va = sctx->border_color_buffer->gpu_address;
328
329 if (sctx->chip_class >= CIK) {
330 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
331 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
332 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
333 } else {
334 if (sctx->screen->info.drm_major == 3 ||
335 (sctx->screen->info.drm_major == 2 &&
336 sctx->screen->info.drm_minor >= 48)) {
337 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
338 bc_va >> 8);
339 }
340 }
341
342 sctx->cs_shader_state.emitted_program = NULL;
343 sctx->cs_shader_state.initialized = true;
344 }
345
346 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
347 struct si_shader *shader,
348 struct si_shader_config *config)
349 {
350 uint64_t scratch_bo_size, scratch_needed;
351 scratch_bo_size = 0;
352 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
353 if (sctx->compute_scratch_buffer)
354 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
355
356 if (scratch_bo_size < scratch_needed) {
357 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
358
359 sctx->compute_scratch_buffer = (struct r600_resource*)
360 si_aligned_buffer_create(&sctx->screen->b,
361 SI_RESOURCE_FLAG_UNMAPPABLE,
362 PIPE_USAGE_DEFAULT,
363 scratch_needed, 256);
364
365 if (!sctx->compute_scratch_buffer)
366 return false;
367 }
368
369 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
370 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
371
372 si_shader_apply_scratch_relocs(shader, scratch_va);
373
374 if (si_shader_binary_upload(sctx->screen, shader))
375 return false;
376
377 r600_resource_reference(&shader->scratch_bo,
378 sctx->compute_scratch_buffer);
379 }
380
381 return true;
382 }
383
384 static bool si_switch_compute_shader(struct si_context *sctx,
385 struct si_compute *program,
386 struct si_shader *shader,
387 const amd_kernel_code_t *code_object,
388 unsigned offset)
389 {
390 struct radeon_winsys_cs *cs = sctx->gfx_cs;
391 struct si_shader_config inline_config = {0};
392 struct si_shader_config *config;
393 uint64_t shader_va;
394
395 if (sctx->cs_shader_state.emitted_program == program &&
396 sctx->cs_shader_state.offset == offset)
397 return true;
398
399 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
400 config = &shader->config;
401 } else {
402 unsigned lds_blocks;
403
404 config = &inline_config;
405 if (code_object) {
406 code_object_to_config(code_object, config);
407 } else {
408 si_shader_binary_read_config(&shader->binary, config, offset);
409 }
410
411 lds_blocks = config->lds_size;
412 /* XXX: We are over allocating LDS. For SI, the shader reports
413 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
414 * allocated in the shader and 4 bytes allocated by the state
415 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
416 */
417 if (sctx->chip_class <= SI) {
418 lds_blocks += align(program->local_size, 256) >> 8;
419 } else {
420 lds_blocks += align(program->local_size, 512) >> 9;
421 }
422
423 /* TODO: use si_multiwave_lds_size_workaround */
424 assert(lds_blocks <= 0xFF);
425
426 config->rsrc2 &= C_00B84C_LDS_SIZE;
427 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
428 }
429
430 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
431 return false;
432
433 if (shader->scratch_bo) {
434 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
435 "Total Scratch: %u bytes\n", sctx->scratch_waves,
436 config->scratch_bytes_per_wave,
437 config->scratch_bytes_per_wave *
438 sctx->scratch_waves);
439
440 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
441 shader->scratch_bo, RADEON_USAGE_READWRITE,
442 RADEON_PRIO_SCRATCH_BUFFER);
443 }
444
445 /* Prefetch the compute shader to TC L2.
446 *
447 * We should also prefetch graphics shaders if a compute dispatch was
448 * the last command, and the compute shader if a draw call was the last
449 * command. However, that would add more complexity and we're likely
450 * to get a shader state change in that case anyway.
451 */
452 if (sctx->chip_class >= CIK) {
453 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
454 0, program->shader.bo->b.b.width0);
455 }
456
457 shader_va = shader->bo->gpu_address + offset;
458 if (program->use_code_object_v2) {
459 /* Shader code is placed after the amd_kernel_code_t
460 * struct. */
461 shader_va += sizeof(amd_kernel_code_t);
462 }
463
464 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
465 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
466
467 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
468 radeon_emit(cs, shader_va >> 8);
469 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
470
471 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
472 radeon_emit(cs, config->rsrc1);
473 radeon_emit(cs, config->rsrc2);
474
475 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
476 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
477
478 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
479 S_00B860_WAVES(sctx->scratch_waves)
480 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
481
482 sctx->cs_shader_state.emitted_program = program;
483 sctx->cs_shader_state.offset = offset;
484 sctx->cs_shader_state.uses_scratch =
485 config->scratch_bytes_per_wave != 0;
486
487 return true;
488 }
489
490 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
491 const amd_kernel_code_t *code_object,
492 unsigned user_sgpr)
493 {
494 struct radeon_winsys_cs *cs = sctx->gfx_cs;
495 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
496
497 unsigned max_private_element_size = AMD_HSA_BITS_GET(
498 code_object->code_properties,
499 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
500
501 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
502 uint32_t scratch_dword1 =
503 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
504 S_008F04_SWIZZLE_ENABLE(1);
505
506 /* Disable address clamping */
507 uint32_t scratch_dword2 = 0xffffffff;
508 uint32_t scratch_dword3 =
509 S_008F0C_INDEX_STRIDE(3) |
510 S_008F0C_ADD_TID_ENABLE(1);
511
512 if (sctx->chip_class >= GFX9) {
513 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
514 } else {
515 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
516
517 if (sctx->chip_class < VI) {
518 /* BUF_DATA_FORMAT is ignored, but it cannot be
519 * BUF_DATA_FORMAT_INVALID. */
520 scratch_dword3 |=
521 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
522 }
523 }
524
525 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
526 (user_sgpr * 4), 4);
527 radeon_emit(cs, scratch_dword0);
528 radeon_emit(cs, scratch_dword1);
529 radeon_emit(cs, scratch_dword2);
530 radeon_emit(cs, scratch_dword3);
531 }
532
533 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
534 const amd_kernel_code_t *code_object,
535 const struct pipe_grid_info *info,
536 uint64_t kernel_args_va)
537 {
538 struct si_compute *program = sctx->cs_shader_state.program;
539 struct radeon_winsys_cs *cs = sctx->gfx_cs;
540
541 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
542 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
543 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
544 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
545 };
546
547 unsigned i, user_sgpr = 0;
548 if (AMD_HSA_BITS_GET(code_object->code_properties,
549 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
550 if (code_object->workitem_private_segment_byte_size > 0) {
551 setup_scratch_rsrc_user_sgprs(sctx, code_object,
552 user_sgpr);
553 }
554 user_sgpr += 4;
555 }
556
557 if (AMD_HSA_BITS_GET(code_object->code_properties,
558 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
559 struct dispatch_packet dispatch;
560 unsigned dispatch_offset;
561 struct r600_resource *dispatch_buf = NULL;
562 uint64_t dispatch_va;
563
564 /* Upload dispatch ptr */
565 memset(&dispatch, 0, sizeof(dispatch));
566
567 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
568 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
569 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
570
571 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
572 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
573 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
574
575 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
576 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
577
578 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
579
580 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
581 256, &dispatch, &dispatch_offset,
582 (struct pipe_resource**)&dispatch_buf);
583
584 if (!dispatch_buf) {
585 fprintf(stderr, "Error: Failed to allocate dispatch "
586 "packet.");
587 }
588 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
589 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
590
591 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
592
593 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
594 (user_sgpr * 4), 2);
595 radeon_emit(cs, dispatch_va);
596 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
597 S_008F04_STRIDE(0));
598
599 r600_resource_reference(&dispatch_buf, NULL);
600 user_sgpr += 2;
601 }
602
603 if (AMD_HSA_BITS_GET(code_object->code_properties,
604 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
605 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
606 (user_sgpr * 4), 2);
607 radeon_emit(cs, kernel_args_va);
608 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
609 S_008F04_STRIDE(0));
610 user_sgpr += 2;
611 }
612
613 for (i = 0; i < 3 && user_sgpr < 16; i++) {
614 if (code_object->code_properties & workgroup_count_masks[i]) {
615 radeon_set_sh_reg_seq(cs,
616 R_00B900_COMPUTE_USER_DATA_0 +
617 (user_sgpr * 4), 1);
618 radeon_emit(cs, info->grid[i]);
619 user_sgpr += 1;
620 }
621 }
622 }
623
624 static bool si_upload_compute_input(struct si_context *sctx,
625 const amd_kernel_code_t *code_object,
626 const struct pipe_grid_info *info)
627 {
628 struct radeon_winsys_cs *cs = sctx->gfx_cs;
629 struct si_compute *program = sctx->cs_shader_state.program;
630 struct r600_resource *input_buffer = NULL;
631 unsigned kernel_args_size;
632 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
633 uint32_t kernel_args_offset = 0;
634 uint32_t *kernel_args;
635 void *kernel_args_ptr;
636 uint64_t kernel_args_va;
637 unsigned i;
638
639 /* The extra num_work_size_bytes are for work group / work item size information */
640 kernel_args_size = program->input_size + num_work_size_bytes;
641
642 u_upload_alloc(sctx->b.const_uploader, 0, kernel_args_size,
643 sctx->screen->info.tcc_cache_line_size,
644 &kernel_args_offset,
645 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
646
647 if (unlikely(!kernel_args_ptr))
648 return false;
649
650 kernel_args = (uint32_t*)kernel_args_ptr;
651 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
652
653 if (!code_object) {
654 for (i = 0; i < 3; i++) {
655 kernel_args[i] = util_cpu_to_le32(info->grid[i]);
656 kernel_args[i + 3] = util_cpu_to_le32(info->grid[i] * info->block[i]);
657 kernel_args[i + 6] = util_cpu_to_le32(info->block[i]);
658 }
659 }
660
661 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
662 program->input_size);
663
664
665 for (i = 0; i < (kernel_args_size / 4); i++) {
666 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
667 kernel_args[i]);
668 }
669
670
671 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
672 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
673
674 if (code_object) {
675 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
676 } else {
677 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
678 radeon_emit(cs, kernel_args_va);
679 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
680 S_008F04_STRIDE(0));
681 }
682
683 r600_resource_reference(&input_buffer, NULL);
684
685 return true;
686 }
687
688 static void si_setup_tgsi_grid(struct si_context *sctx,
689 const struct pipe_grid_info *info)
690 {
691 struct si_compute *program = sctx->cs_shader_state.program;
692 struct radeon_winsys_cs *cs = sctx->gfx_cs;
693 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
694 4 * SI_NUM_RESOURCE_SGPRS;
695 unsigned block_size_reg = grid_size_reg +
696 /* 12 bytes = 3 dwords. */
697 12 * program->uses_grid_size;
698
699 if (info->indirect) {
700 if (program->uses_grid_size) {
701 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
702 uint64_t va = base_va + info->indirect_offset;
703 int i;
704
705 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
706 (struct r600_resource *)info->indirect,
707 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
708
709 for (i = 0; i < 3; ++i) {
710 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
711 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
712 COPY_DATA_DST_SEL(COPY_DATA_REG));
713 radeon_emit(cs, (va + 4 * i));
714 radeon_emit(cs, (va + 4 * i) >> 32);
715 radeon_emit(cs, (grid_size_reg >> 2) + i);
716 radeon_emit(cs, 0);
717 }
718 }
719 } else {
720 if (program->uses_grid_size) {
721 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
722 radeon_emit(cs, info->grid[0]);
723 radeon_emit(cs, info->grid[1]);
724 radeon_emit(cs, info->grid[2]);
725 }
726 if (program->variable_group_size && program->uses_block_size) {
727 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
728 radeon_emit(cs, info->block[0]);
729 radeon_emit(cs, info->block[1]);
730 radeon_emit(cs, info->block[2]);
731 }
732 }
733 }
734
735 static void si_emit_dispatch_packets(struct si_context *sctx,
736 const struct pipe_grid_info *info)
737 {
738 struct si_screen *sscreen = sctx->screen;
739 struct radeon_winsys_cs *cs = sctx->gfx_cs;
740 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
741 unsigned waves_per_threadgroup =
742 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
743 unsigned compute_resource_limits =
744 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
745
746 if (sctx->chip_class >= CIK) {
747 unsigned num_cu_per_se = sscreen->info.num_good_compute_units /
748 sscreen->info.max_se;
749
750 /* Force even distribution on all SIMDs in CU if the workgroup
751 * size is 64. This has shown some good improvements if # of CUs
752 * per SE is not a multiple of 4.
753 */
754 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
755 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
756 }
757
758 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
759 compute_resource_limits);
760
761 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
762 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
763 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
764 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
765
766 unsigned dispatch_initiator =
767 S_00B800_COMPUTE_SHADER_EN(1) |
768 S_00B800_FORCE_START_AT_000(1) |
769 /* If the KMD allows it (there is a KMD hw register for it),
770 * allow launching waves out-of-order. (same as Vulkan) */
771 S_00B800_ORDER_MODE(sctx->chip_class >= CIK);
772
773 if (info->indirect) {
774 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
775
776 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
777 (struct r600_resource *)info->indirect,
778 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
779
780 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
781 PKT3_SHADER_TYPE_S(1));
782 radeon_emit(cs, 1);
783 radeon_emit(cs, base_va);
784 radeon_emit(cs, base_va >> 32);
785
786 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
787 PKT3_SHADER_TYPE_S(1));
788 radeon_emit(cs, info->indirect_offset);
789 radeon_emit(cs, dispatch_initiator);
790 } else {
791 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
792 PKT3_SHADER_TYPE_S(1));
793 radeon_emit(cs, info->grid[0]);
794 radeon_emit(cs, info->grid[1]);
795 radeon_emit(cs, info->grid[2]);
796 radeon_emit(cs, dispatch_initiator);
797 }
798 }
799
800
801 static void si_launch_grid(
802 struct pipe_context *ctx, const struct pipe_grid_info *info)
803 {
804 struct si_context *sctx = (struct si_context*)ctx;
805 struct si_compute *program = sctx->cs_shader_state.program;
806 const amd_kernel_code_t *code_object =
807 si_compute_get_code_object(program, info->pc);
808 int i;
809 /* HW bug workaround when CS threadgroups > 256 threads and async
810 * compute isn't used, i.e. only one compute job can run at a time.
811 * If async compute is possible, the threadgroup size must be limited
812 * to 256 threads on all queues to avoid the bug.
813 * Only SI and certain CIK chips are affected.
814 */
815 bool cs_regalloc_hang =
816 (sctx->chip_class == SI ||
817 sctx->family == CHIP_BONAIRE ||
818 sctx->family == CHIP_KABINI) &&
819 info->block[0] * info->block[1] * info->block[2] > 256;
820
821 if (cs_regalloc_hang)
822 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
823 SI_CONTEXT_CS_PARTIAL_FLUSH;
824
825 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
826 program->shader.compilation_failed)
827 return;
828
829 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
830 si_update_fb_dirtiness_after_rendering(sctx);
831 sctx->last_num_draw_calls = sctx->num_draw_calls;
832 }
833
834 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
835
836 /* Add buffer sizes for memory checking in need_cs_space. */
837 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
838 /* TODO: add the scratch buffer */
839
840 if (info->indirect) {
841 si_context_add_resource_size(sctx, info->indirect);
842
843 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
844 if (sctx->chip_class <= VI &&
845 r600_resource(info->indirect)->TC_L2_dirty) {
846 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
847 r600_resource(info->indirect)->TC_L2_dirty = false;
848 }
849 }
850
851 si_need_gfx_cs_space(sctx);
852
853 if (!sctx->cs_shader_state.initialized)
854 si_initialize_compute(sctx);
855
856 if (sctx->flags)
857 si_emit_cache_flush(sctx);
858
859 if (!si_switch_compute_shader(sctx, program, &program->shader,
860 code_object, info->pc))
861 return;
862
863 si_upload_compute_shader_descriptors(sctx);
864 si_emit_compute_shader_pointers(sctx);
865
866 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
867 sctx->atoms.s.render_cond.emit(sctx);
868 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
869 }
870
871 if ((program->input_size ||
872 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
873 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
874 return;
875 }
876
877 /* Global buffers */
878 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
879 struct r600_resource *buffer =
880 (struct r600_resource*)program->global_buffers[i];
881 if (!buffer) {
882 continue;
883 }
884 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
885 RADEON_USAGE_READWRITE,
886 RADEON_PRIO_COMPUTE_GLOBAL);
887 }
888
889 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
890 si_setup_tgsi_grid(sctx, info);
891
892 si_emit_dispatch_packets(sctx, info);
893
894 if (unlikely(sctx->current_saved_cs)) {
895 si_trace_emit(sctx);
896 si_log_compute_state(sctx, sctx->log);
897 }
898
899 sctx->compute_is_busy = true;
900 sctx->num_compute_calls++;
901 if (sctx->cs_shader_state.uses_scratch)
902 sctx->num_spill_compute_calls++;
903
904 if (cs_regalloc_hang)
905 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
906 }
907
908 void si_destroy_compute(struct si_compute *program)
909 {
910 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
911 util_queue_drop_job(&program->screen->shader_compiler_queue,
912 &program->ready);
913 util_queue_fence_destroy(&program->ready);
914 }
915
916 si_shader_destroy(&program->shader);
917 FREE(program);
918 }
919
920 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
921 struct si_compute *program = (struct si_compute *)state;
922 struct si_context *sctx = (struct si_context*)ctx;
923
924 if (!state)
925 return;
926
927 if (program == sctx->cs_shader_state.program)
928 sctx->cs_shader_state.program = NULL;
929
930 if (program == sctx->cs_shader_state.emitted_program)
931 sctx->cs_shader_state.emitted_program = NULL;
932
933 si_compute_reference(&program, NULL);
934 }
935
936 static void si_set_compute_resources(struct pipe_context * ctx_,
937 unsigned start, unsigned count,
938 struct pipe_surface ** surfaces) { }
939
940 void si_init_compute_functions(struct si_context *sctx)
941 {
942 sctx->b.create_compute_state = si_create_compute_state;
943 sctx->b.delete_compute_state = si_delete_compute_state;
944 sctx->b.bind_compute_state = si_bind_compute_state;
945 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
946 sctx->b.set_compute_resources = si_set_compute_resources;
947 sctx->b.set_global_binding = si_set_global_binding;
948 sctx->b.launch_grid = si_launch_grid;
949 }