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radeonsi: switch r600_atom::emit parameter to si_context
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_async_debug.h"
27 #include "util/u_memory.h"
28 #include "util/u_upload_mgr.h"
29
30 #include "amd_kernel_code_t.h"
31 #include "radeon/r600_cs.h"
32 #include "si_pipe.h"
33 #include "si_compute.h"
34 #include "sid.h"
35
36 #define COMPUTE_DBG(rscreen, fmt, args...) \
37 do { \
38 if ((rscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
39 } while (0);
40
41 struct dispatch_packet {
42 uint16_t header;
43 uint16_t setup;
44 uint16_t workgroup_size_x;
45 uint16_t workgroup_size_y;
46 uint16_t workgroup_size_z;
47 uint16_t reserved0;
48 uint32_t grid_size_x;
49 uint32_t grid_size_y;
50 uint32_t grid_size_z;
51 uint32_t private_segment_size;
52 uint32_t group_segment_size;
53 uint64_t kernel_object;
54 uint64_t kernarg_address;
55 uint64_t reserved2;
56 };
57
58 static const amd_kernel_code_t *si_compute_get_code_object(
59 const struct si_compute *program,
60 uint64_t symbol_offset)
61 {
62 if (!program->use_code_object_v2) {
63 return NULL;
64 }
65 return (const amd_kernel_code_t*)
66 (program->shader.binary.code + symbol_offset);
67 }
68
69 static void code_object_to_config(const amd_kernel_code_t *code_object,
70 struct si_shader_config *out_config) {
71
72 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
73 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
74 out_config->num_sgprs = code_object->wavefront_sgpr_count;
75 out_config->num_vgprs = code_object->workitem_vgpr_count;
76 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
77 out_config->rsrc1 = rsrc1;
78 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
79 out_config->rsrc2 = rsrc2;
80 out_config->scratch_bytes_per_wave =
81 align(code_object->workitem_private_segment_byte_size * 64, 1024);
82 }
83
84 /* Asynchronous compute shader compilation. */
85 static void si_create_compute_state_async(void *job, int thread_index)
86 {
87 struct si_compute *program = (struct si_compute *)job;
88 struct si_shader *shader = &program->shader;
89 struct si_shader_selector sel;
90 LLVMTargetMachineRef tm;
91 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
92
93 assert(!debug->debug_message || debug->async);
94 assert(thread_index >= 0);
95 assert(thread_index < ARRAY_SIZE(program->screen->tm));
96 tm = program->screen->tm[thread_index];
97
98 memset(&sel, 0, sizeof(sel));
99
100 sel.screen = program->screen;
101
102 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
103 tgsi_scan_shader(program->ir.tgsi, &sel.info);
104 sel.tokens = program->ir.tgsi;
105 } else {
106 assert(program->ir_type == PIPE_SHADER_IR_NIR);
107 sel.nir = program->ir.nir;
108
109 si_nir_scan_shader(sel.nir, &sel.info);
110 si_lower_nir(&sel);
111 }
112
113
114 sel.type = PIPE_SHADER_COMPUTE;
115 sel.local_size = program->local_size;
116 si_get_active_slot_masks(&sel.info,
117 &program->active_const_and_shader_buffers,
118 &program->active_samplers_and_images);
119
120 program->shader.selector = &sel;
121 program->shader.is_monolithic = true;
122 program->uses_grid_size = sel.info.uses_grid_size;
123 program->uses_block_size = sel.info.uses_block_size;
124 program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
125 program->uses_bindless_images = sel.info.uses_bindless_images;
126
127 if (si_shader_create(program->screen, tm, &program->shader, debug)) {
128 program->shader.compilation_failed = true;
129 } else {
130 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
131 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
132 (sel.info.uses_grid_size ? 3 : 0) +
133 (sel.info.uses_block_size ? 3 : 0);
134
135 shader->config.rsrc1 =
136 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
137 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
138 S_00B848_DX10_CLAMP(1) |
139 S_00B848_FLOAT_MODE(shader->config.float_mode);
140
141 shader->config.rsrc2 =
142 S_00B84C_USER_SGPR(user_sgprs) |
143 S_00B84C_SCRATCH_EN(scratch_enabled) |
144 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
145 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
146 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
147 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
148 sel.info.uses_thread_id[1] ? 1 : 0) |
149 S_00B84C_LDS_SIZE(shader->config.lds_size);
150
151 program->variable_group_size =
152 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
153 }
154
155 if (program->ir_type == PIPE_SHADER_IR_TGSI)
156 FREE(program->ir.tgsi);
157
158 program->shader.selector = NULL;
159 }
160
161 static void *si_create_compute_state(
162 struct pipe_context *ctx,
163 const struct pipe_compute_state *cso)
164 {
165 struct si_context *sctx = (struct si_context *)ctx;
166 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
167 struct si_compute *program = CALLOC_STRUCT(si_compute);
168
169 pipe_reference_init(&program->reference, 1);
170 program->screen = (struct si_screen *)ctx->screen;
171 program->ir_type = cso->ir_type;
172 program->local_size = cso->req_local_mem;
173 program->private_size = cso->req_private_mem;
174 program->input_size = cso->req_input_mem;
175 program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
176
177 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
178 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
179 program->ir.tgsi = tgsi_dup_tokens(cso->prog);
180 if (!program->ir.tgsi) {
181 FREE(program);
182 return NULL;
183 }
184 } else {
185 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
186 program->ir.nir = (struct nir_shader *) cso->prog;
187 }
188
189 program->compiler_ctx_state.debug = sctx->debug;
190 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
191 p_atomic_inc(&sscreen->num_shaders_created);
192 util_queue_fence_init(&program->ready);
193
194 struct util_async_debug_callback async_debug;
195 bool wait =
196 (sctx->debug.debug_message && !sctx->debug.async) ||
197 sctx->is_debug ||
198 si_can_dump_shader(sscreen, PIPE_SHADER_COMPUTE);
199
200 if (wait) {
201 u_async_debug_init(&async_debug);
202 program->compiler_ctx_state.debug = async_debug.base;
203 }
204
205 util_queue_add_job(&sscreen->shader_compiler_queue,
206 program, &program->ready,
207 si_create_compute_state_async, NULL);
208
209 if (wait) {
210 util_queue_fence_wait(&program->ready);
211 u_async_debug_drain(&async_debug, &sctx->debug);
212 u_async_debug_cleanup(&async_debug);
213 }
214 } else {
215 const struct pipe_llvm_program_header *header;
216 const char *code;
217 header = cso->prog;
218 code = cso->prog + sizeof(struct pipe_llvm_program_header);
219
220 ac_elf_read(code, header->num_bytes, &program->shader.binary);
221 if (program->use_code_object_v2) {
222 const amd_kernel_code_t *code_object =
223 si_compute_get_code_object(program, 0);
224 code_object_to_config(code_object, &program->shader.config);
225 } else {
226 si_shader_binary_read_config(&program->shader.binary,
227 &program->shader.config, 0);
228 }
229 si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
230 PIPE_SHADER_COMPUTE, stderr, true);
231 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
232 fprintf(stderr, "LLVM failed to upload shader\n");
233 FREE(program);
234 return NULL;
235 }
236 }
237
238 return program;
239 }
240
241 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
242 {
243 struct si_context *sctx = (struct si_context*)ctx;
244 struct si_compute *program = (struct si_compute*)state;
245
246 sctx->cs_shader_state.program = program;
247 if (!program)
248 return;
249
250 /* Wait because we need active slot usage masks. */
251 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
252 util_queue_fence_wait(&program->ready);
253
254 si_set_active_descriptors(sctx,
255 SI_DESCS_FIRST_COMPUTE +
256 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
257 program->active_const_and_shader_buffers);
258 si_set_active_descriptors(sctx,
259 SI_DESCS_FIRST_COMPUTE +
260 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
261 program->active_samplers_and_images);
262 }
263
264 static void si_set_global_binding(
265 struct pipe_context *ctx, unsigned first, unsigned n,
266 struct pipe_resource **resources,
267 uint32_t **handles)
268 {
269 unsigned i;
270 struct si_context *sctx = (struct si_context*)ctx;
271 struct si_compute *program = sctx->cs_shader_state.program;
272
273 assert(first + n <= MAX_GLOBAL_BUFFERS);
274
275 if (!resources) {
276 for (i = 0; i < n; i++) {
277 pipe_resource_reference(&program->global_buffers[first + i], NULL);
278 }
279 return;
280 }
281
282 for (i = 0; i < n; i++) {
283 uint64_t va;
284 uint32_t offset;
285 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
286 va = r600_resource(resources[i])->gpu_address;
287 offset = util_le32_to_cpu(*handles[i]);
288 va += offset;
289 va = util_cpu_to_le64(va);
290 memcpy(handles[i], &va, sizeof(va));
291 }
292 }
293
294 static void si_initialize_compute(struct si_context *sctx)
295 {
296 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
297 uint64_t bc_va;
298
299 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
300 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
301 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
302 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
303
304 if (sctx->b.chip_class >= CIK) {
305 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
306 radeon_set_sh_reg_seq(cs,
307 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
308 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
309 S_00B864_SH1_CU_EN(0xffff));
310 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
311 S_00B868_SH1_CU_EN(0xffff));
312 }
313
314 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
315 * and is now per pipe, so it should be handled in the
316 * kernel if we want to use something other than the default value,
317 * which is now 0x22f.
318 */
319 if (sctx->b.chip_class <= SI) {
320 /* XXX: This should be:
321 * (number of compute units) * 4 * (waves per simd) - 1 */
322
323 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
324 0x190 /* Default value */);
325 }
326
327 /* Set the pointer to border colors. */
328 bc_va = sctx->border_color_buffer->gpu_address;
329
330 if (sctx->b.chip_class >= CIK) {
331 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
332 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
333 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
334 } else {
335 if (sctx->screen->info.drm_major == 3 ||
336 (sctx->screen->info.drm_major == 2 &&
337 sctx->screen->info.drm_minor >= 48)) {
338 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
339 bc_va >> 8);
340 }
341 }
342
343 sctx->cs_shader_state.emitted_program = NULL;
344 sctx->cs_shader_state.initialized = true;
345 }
346
347 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
348 struct si_shader *shader,
349 struct si_shader_config *config)
350 {
351 uint64_t scratch_bo_size, scratch_needed;
352 scratch_bo_size = 0;
353 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
354 if (sctx->compute_scratch_buffer)
355 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
356
357 if (scratch_bo_size < scratch_needed) {
358 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
359
360 sctx->compute_scratch_buffer = (struct r600_resource*)
361 si_aligned_buffer_create(&sctx->screen->b,
362 R600_RESOURCE_FLAG_UNMAPPABLE,
363 PIPE_USAGE_DEFAULT,
364 scratch_needed, 256);
365
366 if (!sctx->compute_scratch_buffer)
367 return false;
368 }
369
370 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
371 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
372
373 si_shader_apply_scratch_relocs(shader, scratch_va);
374
375 if (si_shader_binary_upload(sctx->screen, shader))
376 return false;
377
378 r600_resource_reference(&shader->scratch_bo,
379 sctx->compute_scratch_buffer);
380 }
381
382 return true;
383 }
384
385 static bool si_switch_compute_shader(struct si_context *sctx,
386 struct si_compute *program,
387 struct si_shader *shader,
388 const amd_kernel_code_t *code_object,
389 unsigned offset)
390 {
391 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
392 struct si_shader_config inline_config = {0};
393 struct si_shader_config *config;
394 uint64_t shader_va;
395
396 if (sctx->cs_shader_state.emitted_program == program &&
397 sctx->cs_shader_state.offset == offset)
398 return true;
399
400 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
401 config = &shader->config;
402 } else {
403 unsigned lds_blocks;
404
405 config = &inline_config;
406 if (code_object) {
407 code_object_to_config(code_object, config);
408 } else {
409 si_shader_binary_read_config(&shader->binary, config, offset);
410 }
411
412 lds_blocks = config->lds_size;
413 /* XXX: We are over allocating LDS. For SI, the shader reports
414 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
415 * allocated in the shader and 4 bytes allocated by the state
416 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
417 */
418 if (sctx->b.chip_class <= SI) {
419 lds_blocks += align(program->local_size, 256) >> 8;
420 } else {
421 lds_blocks += align(program->local_size, 512) >> 9;
422 }
423
424 /* TODO: use si_multiwave_lds_size_workaround */
425 assert(lds_blocks <= 0xFF);
426
427 config->rsrc2 &= C_00B84C_LDS_SIZE;
428 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
429 }
430
431 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
432 return false;
433
434 if (shader->scratch_bo) {
435 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
436 "Total Scratch: %u bytes\n", sctx->scratch_waves,
437 config->scratch_bytes_per_wave,
438 config->scratch_bytes_per_wave *
439 sctx->scratch_waves);
440
441 radeon_add_to_buffer_list(&sctx->b, sctx->b.gfx_cs,
442 shader->scratch_bo, RADEON_USAGE_READWRITE,
443 RADEON_PRIO_SCRATCH_BUFFER);
444 }
445
446 /* Prefetch the compute shader to TC L2.
447 *
448 * We should also prefetch graphics shaders if a compute dispatch was
449 * the last command, and the compute shader if a draw call was the last
450 * command. However, that would add more complexity and we're likely
451 * to get a shader state change in that case anyway.
452 */
453 if (sctx->b.chip_class >= CIK) {
454 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
455 0, program->shader.bo->b.b.width0);
456 }
457
458 shader_va = shader->bo->gpu_address + offset;
459 if (program->use_code_object_v2) {
460 /* Shader code is placed after the amd_kernel_code_t
461 * struct. */
462 shader_va += sizeof(amd_kernel_code_t);
463 }
464
465 radeon_add_to_buffer_list(&sctx->b, sctx->b.gfx_cs, shader->bo,
466 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
467
468 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
469 radeon_emit(cs, shader_va >> 8);
470 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
471
472 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
473 radeon_emit(cs, config->rsrc1);
474 radeon_emit(cs, config->rsrc2);
475
476 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
477 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
478
479 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
480 S_00B860_WAVES(sctx->scratch_waves)
481 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
482
483 sctx->cs_shader_state.emitted_program = program;
484 sctx->cs_shader_state.offset = offset;
485 sctx->cs_shader_state.uses_scratch =
486 config->scratch_bytes_per_wave != 0;
487
488 return true;
489 }
490
491 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
492 const amd_kernel_code_t *code_object,
493 unsigned user_sgpr)
494 {
495 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
496 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
497
498 unsigned max_private_element_size = AMD_HSA_BITS_GET(
499 code_object->code_properties,
500 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
501
502 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
503 uint32_t scratch_dword1 =
504 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
505 S_008F04_SWIZZLE_ENABLE(1);
506
507 /* Disable address clamping */
508 uint32_t scratch_dword2 = 0xffffffff;
509 uint32_t scratch_dword3 =
510 S_008F0C_INDEX_STRIDE(3) |
511 S_008F0C_ADD_TID_ENABLE(1);
512
513 if (sctx->b.chip_class >= GFX9) {
514 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
515 } else {
516 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
517
518 if (sctx->b.chip_class < VI) {
519 /* BUF_DATA_FORMAT is ignored, but it cannot be
520 * BUF_DATA_FORMAT_INVALID. */
521 scratch_dword3 |=
522 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
523 }
524 }
525
526 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
527 (user_sgpr * 4), 4);
528 radeon_emit(cs, scratch_dword0);
529 radeon_emit(cs, scratch_dword1);
530 radeon_emit(cs, scratch_dword2);
531 radeon_emit(cs, scratch_dword3);
532 }
533
534 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
535 const amd_kernel_code_t *code_object,
536 const struct pipe_grid_info *info,
537 uint64_t kernel_args_va)
538 {
539 struct si_compute *program = sctx->cs_shader_state.program;
540 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
541
542 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
543 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
544 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
545 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
546 };
547
548 unsigned i, user_sgpr = 0;
549 if (AMD_HSA_BITS_GET(code_object->code_properties,
550 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
551 if (code_object->workitem_private_segment_byte_size > 0) {
552 setup_scratch_rsrc_user_sgprs(sctx, code_object,
553 user_sgpr);
554 }
555 user_sgpr += 4;
556 }
557
558 if (AMD_HSA_BITS_GET(code_object->code_properties,
559 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
560 struct dispatch_packet dispatch;
561 unsigned dispatch_offset;
562 struct r600_resource *dispatch_buf = NULL;
563 uint64_t dispatch_va;
564
565 /* Upload dispatch ptr */
566 memset(&dispatch, 0, sizeof(dispatch));
567
568 dispatch.workgroup_size_x = info->block[0];
569 dispatch.workgroup_size_y = info->block[1];
570 dispatch.workgroup_size_z = info->block[2];
571
572 dispatch.grid_size_x = info->grid[0] * info->block[0];
573 dispatch.grid_size_y = info->grid[1] * info->block[1];
574 dispatch.grid_size_z = info->grid[2] * info->block[2];
575
576 dispatch.private_segment_size = program->private_size;
577 dispatch.group_segment_size = program->local_size;
578
579 dispatch.kernarg_address = kernel_args_va;
580
581 u_upload_data(sctx->b.b.const_uploader, 0, sizeof(dispatch),
582 256, &dispatch, &dispatch_offset,
583 (struct pipe_resource**)&dispatch_buf);
584
585 if (!dispatch_buf) {
586 fprintf(stderr, "Error: Failed to allocate dispatch "
587 "packet.");
588 }
589 radeon_add_to_buffer_list(&sctx->b, sctx->b.gfx_cs, dispatch_buf,
590 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
591
592 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
593
594 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
595 (user_sgpr * 4), 2);
596 radeon_emit(cs, dispatch_va);
597 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
598 S_008F04_STRIDE(0));
599
600 r600_resource_reference(&dispatch_buf, NULL);
601 user_sgpr += 2;
602 }
603
604 if (AMD_HSA_BITS_GET(code_object->code_properties,
605 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
606 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
607 (user_sgpr * 4), 2);
608 radeon_emit(cs, kernel_args_va);
609 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
610 S_008F04_STRIDE(0));
611 user_sgpr += 2;
612 }
613
614 for (i = 0; i < 3 && user_sgpr < 16; i++) {
615 if (code_object->code_properties & workgroup_count_masks[i]) {
616 radeon_set_sh_reg_seq(cs,
617 R_00B900_COMPUTE_USER_DATA_0 +
618 (user_sgpr * 4), 1);
619 radeon_emit(cs, info->grid[i]);
620 user_sgpr += 1;
621 }
622 }
623 }
624
625 static bool si_upload_compute_input(struct si_context *sctx,
626 const amd_kernel_code_t *code_object,
627 const struct pipe_grid_info *info)
628 {
629 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
630 struct si_compute *program = sctx->cs_shader_state.program;
631 struct r600_resource *input_buffer = NULL;
632 unsigned kernel_args_size;
633 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
634 uint32_t kernel_args_offset = 0;
635 uint32_t *kernel_args;
636 void *kernel_args_ptr;
637 uint64_t kernel_args_va;
638 unsigned i;
639
640 /* The extra num_work_size_bytes are for work group / work item size information */
641 kernel_args_size = program->input_size + num_work_size_bytes;
642
643 u_upload_alloc(sctx->b.b.const_uploader, 0, kernel_args_size,
644 sctx->screen->info.tcc_cache_line_size,
645 &kernel_args_offset,
646 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
647
648 if (unlikely(!kernel_args_ptr))
649 return false;
650
651 kernel_args = (uint32_t*)kernel_args_ptr;
652 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
653
654 if (!code_object) {
655 for (i = 0; i < 3; i++) {
656 kernel_args[i] = info->grid[i];
657 kernel_args[i + 3] = info->grid[i] * info->block[i];
658 kernel_args[i + 6] = info->block[i];
659 }
660 }
661
662 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
663 program->input_size);
664
665
666 for (i = 0; i < (kernel_args_size / 4); i++) {
667 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
668 kernel_args[i]);
669 }
670
671
672 radeon_add_to_buffer_list(&sctx->b, sctx->b.gfx_cs, input_buffer,
673 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
674
675 if (code_object) {
676 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
677 } else {
678 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
679 radeon_emit(cs, kernel_args_va);
680 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
681 S_008F04_STRIDE(0));
682 }
683
684 r600_resource_reference(&input_buffer, NULL);
685
686 return true;
687 }
688
689 static void si_setup_tgsi_grid(struct si_context *sctx,
690 const struct pipe_grid_info *info)
691 {
692 struct si_compute *program = sctx->cs_shader_state.program;
693 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
694 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
695 4 * SI_NUM_RESOURCE_SGPRS;
696 unsigned block_size_reg = grid_size_reg +
697 /* 12 bytes = 3 dwords. */
698 12 * program->uses_grid_size;
699
700 if (info->indirect) {
701 if (program->uses_grid_size) {
702 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
703 uint64_t va = base_va + info->indirect_offset;
704 int i;
705
706 radeon_add_to_buffer_list(&sctx->b, sctx->b.gfx_cs,
707 (struct r600_resource *)info->indirect,
708 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
709
710 for (i = 0; i < 3; ++i) {
711 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
712 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
713 COPY_DATA_DST_SEL(COPY_DATA_REG));
714 radeon_emit(cs, (va + 4 * i));
715 radeon_emit(cs, (va + 4 * i) >> 32);
716 radeon_emit(cs, (grid_size_reg >> 2) + i);
717 radeon_emit(cs, 0);
718 }
719 }
720 } else {
721 if (program->uses_grid_size) {
722 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
723 radeon_emit(cs, info->grid[0]);
724 radeon_emit(cs, info->grid[1]);
725 radeon_emit(cs, info->grid[2]);
726 }
727 if (program->variable_group_size && program->uses_block_size) {
728 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
729 radeon_emit(cs, info->block[0]);
730 radeon_emit(cs, info->block[1]);
731 radeon_emit(cs, info->block[2]);
732 }
733 }
734 }
735
736 static void si_emit_dispatch_packets(struct si_context *sctx,
737 const struct pipe_grid_info *info)
738 {
739 struct si_screen *sscreen = sctx->screen;
740 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
741 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
742 unsigned waves_per_threadgroup =
743 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
744 unsigned compute_resource_limits =
745 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
746
747 if (sctx->b.chip_class >= CIK) {
748 unsigned num_cu_per_se = sscreen->info.num_good_compute_units /
749 sscreen->info.max_se;
750
751 /* Force even distribution on all SIMDs in CU if the workgroup
752 * size is 64. This has shown some good improvements if # of CUs
753 * per SE is not a multiple of 4.
754 */
755 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
756 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
757 }
758
759 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
760 compute_resource_limits);
761
762 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
763 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
764 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
765 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
766
767 unsigned dispatch_initiator =
768 S_00B800_COMPUTE_SHADER_EN(1) |
769 S_00B800_FORCE_START_AT_000(1) |
770 /* If the KMD allows it (there is a KMD hw register for it),
771 * allow launching waves out-of-order. (same as Vulkan) */
772 S_00B800_ORDER_MODE(sctx->b.chip_class >= CIK);
773
774 if (info->indirect) {
775 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
776
777 radeon_add_to_buffer_list(&sctx->b, sctx->b.gfx_cs,
778 (struct r600_resource *)info->indirect,
779 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
780
781 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
782 PKT3_SHADER_TYPE_S(1));
783 radeon_emit(cs, 1);
784 radeon_emit(cs, base_va);
785 radeon_emit(cs, base_va >> 32);
786
787 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
788 PKT3_SHADER_TYPE_S(1));
789 radeon_emit(cs, info->indirect_offset);
790 radeon_emit(cs, dispatch_initiator);
791 } else {
792 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
793 PKT3_SHADER_TYPE_S(1));
794 radeon_emit(cs, info->grid[0]);
795 radeon_emit(cs, info->grid[1]);
796 radeon_emit(cs, info->grid[2]);
797 radeon_emit(cs, dispatch_initiator);
798 }
799 }
800
801
802 static void si_launch_grid(
803 struct pipe_context *ctx, const struct pipe_grid_info *info)
804 {
805 struct si_context *sctx = (struct si_context*)ctx;
806 struct si_compute *program = sctx->cs_shader_state.program;
807 const amd_kernel_code_t *code_object =
808 si_compute_get_code_object(program, info->pc);
809 int i;
810 /* HW bug workaround when CS threadgroups > 256 threads and async
811 * compute isn't used, i.e. only one compute job can run at a time.
812 * If async compute is possible, the threadgroup size must be limited
813 * to 256 threads on all queues to avoid the bug.
814 * Only SI and certain CIK chips are affected.
815 */
816 bool cs_regalloc_hang =
817 (sctx->b.chip_class == SI ||
818 sctx->b.family == CHIP_BONAIRE ||
819 sctx->b.family == CHIP_KABINI) &&
820 info->block[0] * info->block[1] * info->block[2] > 256;
821
822 if (cs_regalloc_hang)
823 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
824 SI_CONTEXT_CS_PARTIAL_FLUSH;
825
826 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
827 program->shader.compilation_failed)
828 return;
829
830 if (sctx->b.last_num_draw_calls != sctx->b.num_draw_calls) {
831 si_update_fb_dirtiness_after_rendering(sctx);
832 sctx->b.last_num_draw_calls = sctx->b.num_draw_calls;
833 }
834
835 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
836
837 /* Add buffer sizes for memory checking in need_cs_space. */
838 si_context_add_resource_size(ctx, &program->shader.bo->b.b);
839 /* TODO: add the scratch buffer */
840
841 if (info->indirect) {
842 si_context_add_resource_size(ctx, info->indirect);
843
844 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
845 if (sctx->b.chip_class <= VI &&
846 r600_resource(info->indirect)->TC_L2_dirty) {
847 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
848 r600_resource(info->indirect)->TC_L2_dirty = false;
849 }
850 }
851
852 si_need_gfx_cs_space(sctx);
853
854 if (!sctx->cs_shader_state.initialized)
855 si_initialize_compute(sctx);
856
857 if (sctx->b.flags)
858 si_emit_cache_flush(sctx);
859
860 if (!si_switch_compute_shader(sctx, program, &program->shader,
861 code_object, info->pc))
862 return;
863
864 si_upload_compute_shader_descriptors(sctx);
865 si_emit_compute_shader_pointers(sctx);
866
867 if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
868 sctx->atoms.s.render_cond->emit(sctx,
869 sctx->atoms.s.render_cond);
870 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
871 }
872
873 if ((program->input_size ||
874 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
875 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
876 return;
877 }
878
879 /* Global buffers */
880 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
881 struct r600_resource *buffer =
882 (struct r600_resource*)program->global_buffers[i];
883 if (!buffer) {
884 continue;
885 }
886 radeon_add_to_buffer_list(&sctx->b, sctx->b.gfx_cs, buffer,
887 RADEON_USAGE_READWRITE,
888 RADEON_PRIO_COMPUTE_GLOBAL);
889 }
890
891 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
892 si_setup_tgsi_grid(sctx, info);
893
894 si_emit_dispatch_packets(sctx, info);
895
896 if (unlikely(sctx->current_saved_cs)) {
897 si_trace_emit(sctx);
898 si_log_compute_state(sctx, sctx->b.log);
899 }
900
901 sctx->compute_is_busy = true;
902 sctx->b.num_compute_calls++;
903 if (sctx->cs_shader_state.uses_scratch)
904 sctx->b.num_spill_compute_calls++;
905
906 if (cs_regalloc_hang)
907 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
908 }
909
910 void si_destroy_compute(struct si_compute *program)
911 {
912 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
913 util_queue_drop_job(&program->screen->shader_compiler_queue,
914 &program->ready);
915 util_queue_fence_destroy(&program->ready);
916 }
917
918 si_shader_destroy(&program->shader);
919 FREE(program);
920 }
921
922 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
923 struct si_compute *program = (struct si_compute *)state;
924 struct si_context *sctx = (struct si_context*)ctx;
925
926 if (!state)
927 return;
928
929 if (program == sctx->cs_shader_state.program)
930 sctx->cs_shader_state.program = NULL;
931
932 if (program == sctx->cs_shader_state.emitted_program)
933 sctx->cs_shader_state.emitted_program = NULL;
934
935 si_compute_reference(&program, NULL);
936 }
937
938 static void si_set_compute_resources(struct pipe_context * ctx_,
939 unsigned start, unsigned count,
940 struct pipe_surface ** surfaces) { }
941
942 void si_init_compute_functions(struct si_context *sctx)
943 {
944 sctx->b.b.create_compute_state = si_create_compute_state;
945 sctx->b.b.delete_compute_state = si_delete_compute_state;
946 sctx->b.b.bind_compute_state = si_bind_compute_state;
947 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
948 sctx->b.b.set_compute_resources = si_set_compute_resources;
949 sctx->b.b.set_global_binding = si_set_global_binding;
950 sctx->b.b.launch_grid = si_launch_grid;
951 }