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radeonsi: Add missing error-checking to si_create_compute_state (v2)
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
28 #include "radeon/radeon_elf_util.h"
29
30 #include "amd_kernel_code_t.h"
31 #include "radeon/r600_cs.h"
32 #include "si_pipe.h"
33 #include "sid.h"
34
35 #define MAX_GLOBAL_BUFFERS 20
36
37 struct si_compute {
38 unsigned ir_type;
39 unsigned local_size;
40 unsigned private_size;
41 unsigned input_size;
42 struct si_shader shader;
43
44 struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
45 unsigned use_code_object_v2 : 1;
46 unsigned variable_group_size : 1;
47 };
48
49 struct dispatch_packet {
50 uint16_t header;
51 uint16_t setup;
52 uint16_t workgroup_size_x;
53 uint16_t workgroup_size_y;
54 uint16_t workgroup_size_z;
55 uint16_t reserved0;
56 uint32_t grid_size_x;
57 uint32_t grid_size_y;
58 uint32_t grid_size_z;
59 uint32_t private_segment_size;
60 uint32_t group_segment_size;
61 uint64_t kernel_object;
62 uint64_t kernarg_address;
63 uint64_t reserved2;
64 };
65
66 static const amd_kernel_code_t *si_compute_get_code_object(
67 const struct si_compute *program,
68 uint64_t symbol_offset)
69 {
70 if (!program->use_code_object_v2) {
71 return NULL;
72 }
73 return (const amd_kernel_code_t*)
74 (program->shader.binary.code + symbol_offset);
75 }
76
77 static void code_object_to_config(const amd_kernel_code_t *code_object,
78 struct si_shader_config *out_config) {
79
80 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
81 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
82 out_config->num_sgprs = code_object->wavefront_sgpr_count;
83 out_config->num_vgprs = code_object->workitem_vgpr_count;
84 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
85 out_config->rsrc1 = rsrc1;
86 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
87 out_config->rsrc2 = rsrc2;
88 out_config->scratch_bytes_per_wave =
89 align(code_object->workitem_private_segment_byte_size * 64, 1024);
90 }
91
92 static void *si_create_compute_state(
93 struct pipe_context *ctx,
94 const struct pipe_compute_state *cso)
95 {
96 struct si_context *sctx = (struct si_context *)ctx;
97 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
98 struct si_compute *program = CALLOC_STRUCT(si_compute);
99 struct si_shader *shader = &program->shader;
100
101
102 program->ir_type = cso->ir_type;
103 program->local_size = cso->req_local_mem;
104 program->private_size = cso->req_private_mem;
105 program->input_size = cso->req_input_mem;
106 program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
107 cso->ir_type == PIPE_SHADER_IR_NATIVE;
108
109
110 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
111 struct si_shader_selector sel;
112 bool scratch_enabled;
113
114 memset(&sel, 0, sizeof(sel));
115
116 sel.tokens = tgsi_dup_tokens(cso->prog);
117 if (!sel.tokens) {
118 FREE(program);
119 return NULL;
120 }
121
122 tgsi_scan_shader(cso->prog, &sel.info);
123 sel.type = PIPE_SHADER_COMPUTE;
124 sel.local_size = cso->req_local_mem;
125
126 p_atomic_inc(&sscreen->b.num_shaders_created);
127
128 program->shader.selector = &sel;
129
130 if (si_shader_create(sscreen, sctx->tm, &program->shader,
131 &sctx->b.debug)) {
132 FREE(sel.tokens);
133 FREE(program);
134 return NULL;
135 }
136
137 scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
138
139 shader->config.rsrc1 =
140 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
141 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
142 S_00B848_DX10_CLAMP(1) |
143 S_00B848_FLOAT_MODE(shader->config.float_mode);
144
145 shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
146 S_00B84C_SCRATCH_EN(scratch_enabled) |
147 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
148 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
149 S_00B84C_LDS_SIZE(shader->config.lds_size);
150
151 program->variable_group_size =
152 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
153
154 FREE(sel.tokens);
155 program->shader.selector = NULL;
156 } else {
157 const struct pipe_llvm_program_header *header;
158 const char *code;
159 header = cso->prog;
160 code = cso->prog + sizeof(struct pipe_llvm_program_header);
161
162 radeon_elf_read(code, header->num_bytes, &program->shader.binary);
163 if (program->use_code_object_v2) {
164 const amd_kernel_code_t *code_object =
165 si_compute_get_code_object(program, 0);
166 code_object_to_config(code_object, &program->shader.config);
167 } else {
168 si_shader_binary_read_config(&program->shader.binary,
169 &program->shader.config, 0);
170 }
171 si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
172 PIPE_SHADER_COMPUTE, stderr);
173 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
174 fprintf(stderr, "LLVM failed to upload shader\n");
175 FREE(program);
176 return NULL;
177 }
178 }
179
180 return program;
181 }
182
183 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
184 {
185 struct si_context *sctx = (struct si_context*)ctx;
186 sctx->cs_shader_state.program = (struct si_compute*)state;
187 }
188
189 static void si_set_global_binding(
190 struct pipe_context *ctx, unsigned first, unsigned n,
191 struct pipe_resource **resources,
192 uint32_t **handles)
193 {
194 unsigned i;
195 struct si_context *sctx = (struct si_context*)ctx;
196 struct si_compute *program = sctx->cs_shader_state.program;
197
198 if (!resources) {
199 for (i = first; i < first + n; i++) {
200 pipe_resource_reference(&program->global_buffers[i], NULL);
201 }
202 return;
203 }
204
205 for (i = first; i < first + n; i++) {
206 uint64_t va;
207 uint32_t offset;
208 pipe_resource_reference(&program->global_buffers[i], resources[i]);
209 va = r600_resource(resources[i])->gpu_address;
210 offset = util_le32_to_cpu(*handles[i]);
211 va += offset;
212 va = util_cpu_to_le64(va);
213 memcpy(handles[i], &va, sizeof(va));
214 }
215 }
216
217 static void si_initialize_compute(struct si_context *sctx)
218 {
219 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
220 uint64_t bc_va;
221
222 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
223 radeon_emit(cs, 0);
224 radeon_emit(cs, 0);
225 radeon_emit(cs, 0);
226
227 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
228 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
229 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
230 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
231
232 if (sctx->b.chip_class >= CIK) {
233 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
234 radeon_set_sh_reg_seq(cs,
235 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
236 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
237 S_00B864_SH1_CU_EN(0xffff));
238 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
239 S_00B868_SH1_CU_EN(0xffff));
240 }
241
242 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
243 * and is now per pipe, so it should be handled in the
244 * kernel if we want to use something other than the default value,
245 * which is now 0x22f.
246 */
247 if (sctx->b.chip_class <= SI) {
248 /* XXX: This should be:
249 * (number of compute units) * 4 * (waves per simd) - 1 */
250
251 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
252 0x190 /* Default value */);
253 }
254
255 /* Set the pointer to border colors. */
256 bc_va = sctx->border_color_buffer->gpu_address;
257
258 if (sctx->b.chip_class >= CIK) {
259 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
260 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
261 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
262 } else {
263 if (sctx->screen->b.info.drm_major == 3 ||
264 (sctx->screen->b.info.drm_major == 2 &&
265 sctx->screen->b.info.drm_minor >= 48)) {
266 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
267 bc_va >> 8);
268 }
269 }
270
271 sctx->cs_shader_state.emitted_program = NULL;
272 sctx->cs_shader_state.initialized = true;
273 }
274
275 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
276 struct si_shader *shader,
277 struct si_shader_config *config)
278 {
279 uint64_t scratch_bo_size, scratch_needed;
280 scratch_bo_size = 0;
281 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
282 if (sctx->compute_scratch_buffer)
283 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
284
285 if (scratch_bo_size < scratch_needed) {
286 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
287
288 sctx->compute_scratch_buffer = (struct r600_resource*)
289 pipe_buffer_create(&sctx->screen->b.b, 0,
290 PIPE_USAGE_DEFAULT, scratch_needed);
291
292 if (!sctx->compute_scratch_buffer)
293 return false;
294 }
295
296 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
297 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
298
299 si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
300
301 if (si_shader_binary_upload(sctx->screen, shader))
302 return false;
303
304 r600_resource_reference(&shader->scratch_bo,
305 sctx->compute_scratch_buffer);
306 }
307
308 return true;
309 }
310
311 static bool si_switch_compute_shader(struct si_context *sctx,
312 struct si_compute *program,
313 struct si_shader *shader,
314 const amd_kernel_code_t *code_object,
315 unsigned offset)
316 {
317 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
318 struct si_shader_config inline_config = {0};
319 struct si_shader_config *config;
320 uint64_t shader_va;
321
322 if (sctx->cs_shader_state.emitted_program == program &&
323 sctx->cs_shader_state.offset == offset)
324 return true;
325
326 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
327 config = &shader->config;
328 } else {
329 unsigned lds_blocks;
330
331 config = &inline_config;
332 if (code_object) {
333 code_object_to_config(code_object, config);
334 } else {
335 si_shader_binary_read_config(&shader->binary, config, offset);
336 }
337
338 lds_blocks = config->lds_size;
339 /* XXX: We are over allocating LDS. For SI, the shader reports
340 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
341 * allocated in the shader and 4 bytes allocated by the state
342 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
343 */
344 if (sctx->b.chip_class <= SI) {
345 lds_blocks += align(program->local_size, 256) >> 8;
346 } else {
347 lds_blocks += align(program->local_size, 512) >> 9;
348 }
349
350 assert(lds_blocks <= 0xFF);
351
352 config->rsrc2 &= C_00B84C_LDS_SIZE;
353 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
354 }
355
356 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
357 return false;
358
359 if (shader->scratch_bo) {
360 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
361 "Total Scratch: %u bytes\n", sctx->scratch_waves,
362 config->scratch_bytes_per_wave,
363 config->scratch_bytes_per_wave *
364 sctx->scratch_waves);
365
366 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
367 shader->scratch_bo, RADEON_USAGE_READWRITE,
368 RADEON_PRIO_SCRATCH_BUFFER);
369 }
370
371 shader_va = shader->bo->gpu_address + offset;
372 if (program->use_code_object_v2) {
373 /* Shader code is placed after the amd_kernel_code_t
374 * struct. */
375 shader_va += sizeof(amd_kernel_code_t);
376 }
377
378 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
379 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
380
381 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
382 radeon_emit(cs, shader_va >> 8);
383 radeon_emit(cs, shader_va >> 40);
384
385 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
386 radeon_emit(cs, config->rsrc1);
387 radeon_emit(cs, config->rsrc2);
388
389 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
390 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
391
392 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
393 S_00B860_WAVES(sctx->scratch_waves)
394 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
395
396 sctx->cs_shader_state.emitted_program = program;
397 sctx->cs_shader_state.offset = offset;
398 sctx->cs_shader_state.uses_scratch =
399 config->scratch_bytes_per_wave != 0;
400
401 return true;
402 }
403
404 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
405 const amd_kernel_code_t *code_object,
406 unsigned user_sgpr)
407 {
408 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
409 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
410
411 unsigned max_private_element_size = AMD_HSA_BITS_GET(
412 code_object->code_properties,
413 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
414
415 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
416 uint32_t scratch_dword1 =
417 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
418 S_008F04_SWIZZLE_ENABLE(1);
419
420 /* Disable address clamping */
421 uint32_t scratch_dword2 = 0xffffffff;
422 uint32_t scratch_dword3 =
423 S_008F0C_ELEMENT_SIZE(max_private_element_size) |
424 S_008F0C_INDEX_STRIDE(3) |
425 S_008F0C_ADD_TID_ENABLE(1);
426
427
428 if (sctx->screen->b.chip_class < VI) {
429 /* BUF_DATA_FORMAT is ignored, but it cannot be
430 BUF_DATA_FORMAT_INVALID. */
431 scratch_dword3 |=
432 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
433 }
434
435 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
436 (user_sgpr * 4), 4);
437 radeon_emit(cs, scratch_dword0);
438 radeon_emit(cs, scratch_dword1);
439 radeon_emit(cs, scratch_dword2);
440 radeon_emit(cs, scratch_dword3);
441 }
442
443 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
444 const amd_kernel_code_t *code_object,
445 const struct pipe_grid_info *info,
446 uint64_t kernel_args_va)
447 {
448 struct si_compute *program = sctx->cs_shader_state.program;
449 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
450
451 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
452 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
453 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
454 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
455 };
456
457 unsigned i, user_sgpr = 0;
458 if (AMD_HSA_BITS_GET(code_object->code_properties,
459 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
460 if (code_object->workitem_private_segment_byte_size > 0) {
461 setup_scratch_rsrc_user_sgprs(sctx, code_object,
462 user_sgpr);
463 }
464 user_sgpr += 4;
465 }
466
467 if (AMD_HSA_BITS_GET(code_object->code_properties,
468 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
469 struct dispatch_packet dispatch;
470 unsigned dispatch_offset;
471 struct r600_resource *dispatch_buf = NULL;
472 uint64_t dispatch_va;
473
474 /* Upload dispatch ptr */
475 memset(&dispatch, 0, sizeof(dispatch));
476
477 dispatch.workgroup_size_x = info->block[0];
478 dispatch.workgroup_size_y = info->block[1];
479 dispatch.workgroup_size_z = info->block[2];
480
481 dispatch.grid_size_x = info->grid[0] * info->block[0];
482 dispatch.grid_size_y = info->grid[1] * info->block[1];
483 dispatch.grid_size_z = info->grid[2] * info->block[2];
484
485 dispatch.private_segment_size = program->private_size;
486 dispatch.group_segment_size = program->local_size;
487
488 dispatch.kernarg_address = kernel_args_va;
489
490 u_upload_data(sctx->b.uploader, 0, sizeof(dispatch), 256,
491 &dispatch, &dispatch_offset,
492 (struct pipe_resource**)&dispatch_buf);
493
494 if (!dispatch_buf) {
495 fprintf(stderr, "Error: Failed to allocate dispatch "
496 "packet.");
497 }
498 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
499 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
500
501 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
502
503 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
504 (user_sgpr * 4), 2);
505 radeon_emit(cs, dispatch_va);
506 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
507 S_008F04_STRIDE(0));
508
509 r600_resource_reference(&dispatch_buf, NULL);
510 user_sgpr += 2;
511 }
512
513 if (AMD_HSA_BITS_GET(code_object->code_properties,
514 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
515 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
516 (user_sgpr * 4), 2);
517 radeon_emit(cs, kernel_args_va);
518 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
519 S_008F04_STRIDE(0));
520 user_sgpr += 2;
521 }
522
523 for (i = 0; i < 3 && user_sgpr < 16; i++) {
524 if (code_object->code_properties & workgroup_count_masks[i]) {
525 radeon_set_sh_reg_seq(cs,
526 R_00B900_COMPUTE_USER_DATA_0 +
527 (user_sgpr * 4), 1);
528 radeon_emit(cs, info->grid[i]);
529 user_sgpr += 1;
530 }
531 }
532 }
533
534 static void si_upload_compute_input(struct si_context *sctx,
535 const amd_kernel_code_t *code_object,
536 const struct pipe_grid_info *info)
537 {
538 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
539 struct si_compute *program = sctx->cs_shader_state.program;
540 struct r600_resource *input_buffer = NULL;
541 unsigned kernel_args_size;
542 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
543 uint32_t kernel_args_offset = 0;
544 uint32_t *kernel_args;
545 void *kernel_args_ptr;
546 uint64_t kernel_args_va;
547 unsigned i;
548
549 /* The extra num_work_size_bytes are for work group / work item size information */
550 kernel_args_size = program->input_size + num_work_size_bytes;
551
552 u_upload_alloc(sctx->b.uploader, 0, kernel_args_size, 256,
553 &kernel_args_offset,
554 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
555
556 kernel_args = (uint32_t*)kernel_args_ptr;
557 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
558
559 if (!code_object) {
560 for (i = 0; i < 3; i++) {
561 kernel_args[i] = info->grid[i];
562 kernel_args[i + 3] = info->grid[i] * info->block[i];
563 kernel_args[i + 6] = info->block[i];
564 }
565 }
566
567 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
568 program->input_size);
569
570
571 for (i = 0; i < (kernel_args_size / 4); i++) {
572 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
573 kernel_args[i]);
574 }
575
576
577 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
578 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
579
580 if (code_object) {
581 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
582 } else {
583 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
584 radeon_emit(cs, kernel_args_va);
585 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
586 S_008F04_STRIDE(0));
587 }
588
589 r600_resource_reference(&input_buffer, NULL);
590 }
591
592 static void si_setup_tgsi_grid(struct si_context *sctx,
593 const struct pipe_grid_info *info)
594 {
595 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
596 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
597 4 * SI_SGPR_GRID_SIZE;
598
599 if (info->indirect) {
600 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
601 uint64_t va = base_va + info->indirect_offset;
602 int i;
603
604 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
605 (struct r600_resource *)info->indirect,
606 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
607
608 for (i = 0; i < 3; ++i) {
609 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
610 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
611 COPY_DATA_DST_SEL(COPY_DATA_REG));
612 radeon_emit(cs, (va + 4 * i));
613 radeon_emit(cs, (va + 4 * i) >> 32);
614 radeon_emit(cs, (grid_size_reg >> 2) + i);
615 radeon_emit(cs, 0);
616 }
617 } else {
618 struct si_compute *program = sctx->cs_shader_state.program;
619
620 radeon_set_sh_reg_seq(cs, grid_size_reg, program->variable_group_size ? 6 : 3);
621 radeon_emit(cs, info->grid[0]);
622 radeon_emit(cs, info->grid[1]);
623 radeon_emit(cs, info->grid[2]);
624 if (program->variable_group_size) {
625 radeon_emit(cs, info->block[0]);
626 radeon_emit(cs, info->block[1]);
627 radeon_emit(cs, info->block[2]);
628 }
629 }
630 }
631
632 static void si_emit_dispatch_packets(struct si_context *sctx,
633 const struct pipe_grid_info *info)
634 {
635 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
636 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
637 unsigned waves_per_threadgroup =
638 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
639
640 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
641 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
642
643 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
644 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
645 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
646 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
647
648 if (info->indirect) {
649 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
650
651 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
652 (struct r600_resource *)info->indirect,
653 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
654
655 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
656 PKT3_SHADER_TYPE_S(1));
657 radeon_emit(cs, 1);
658 radeon_emit(cs, base_va);
659 radeon_emit(cs, base_va >> 32);
660
661 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
662 PKT3_SHADER_TYPE_S(1));
663 radeon_emit(cs, info->indirect_offset);
664 radeon_emit(cs, 1);
665 } else {
666 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
667 PKT3_SHADER_TYPE_S(1));
668 radeon_emit(cs, info->grid[0]);
669 radeon_emit(cs, info->grid[1]);
670 radeon_emit(cs, info->grid[2]);
671 radeon_emit(cs, 1);
672 }
673 }
674
675
676 static void si_launch_grid(
677 struct pipe_context *ctx, const struct pipe_grid_info *info)
678 {
679 struct si_context *sctx = (struct si_context*)ctx;
680 struct si_compute *program = sctx->cs_shader_state.program;
681 const amd_kernel_code_t *code_object =
682 si_compute_get_code_object(program, info->pc);
683 int i;
684 /* HW bug workaround when CS threadgroups > 256 threads and async
685 * compute isn't used, i.e. only one compute job can run at a time.
686 * If async compute is possible, the threadgroup size must be limited
687 * to 256 threads on all queues to avoid the bug.
688 * Only SI and certain CIK chips are affected.
689 */
690 bool cs_regalloc_hang =
691 (sctx->b.chip_class == SI ||
692 sctx->b.family == CHIP_BONAIRE ||
693 sctx->b.family == CHIP_KABINI) &&
694 info->block[0] * info->block[1] * info->block[2] > 256;
695
696 if (cs_regalloc_hang)
697 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
698 SI_CONTEXT_CS_PARTIAL_FLUSH;
699
700 si_decompress_compute_textures(sctx);
701
702 /* Add buffer sizes for memory checking in need_cs_space. */
703 r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
704 /* TODO: add the scratch buffer */
705
706 if (info->indirect) {
707 r600_context_add_resource_size(ctx, info->indirect);
708
709 /* The hw doesn't read the indirect buffer via TC L2. */
710 if (r600_resource(info->indirect)->TC_L2_dirty) {
711 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
712 r600_resource(info->indirect)->TC_L2_dirty = false;
713 }
714 }
715
716 si_need_cs_space(sctx);
717
718 if (!sctx->cs_shader_state.initialized)
719 si_initialize_compute(sctx);
720
721 if (sctx->b.flags)
722 si_emit_cache_flush(sctx);
723
724 if (!si_switch_compute_shader(sctx, program, &program->shader,
725 code_object, info->pc))
726 return;
727
728 si_upload_compute_shader_descriptors(sctx);
729 si_emit_compute_shader_userdata(sctx);
730
731 if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
732 sctx->atoms.s.render_cond->emit(&sctx->b,
733 sctx->atoms.s.render_cond);
734 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
735 }
736
737 if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
738 si_upload_compute_input(sctx, code_object, info);
739
740 /* Global buffers */
741 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
742 struct r600_resource *buffer =
743 (struct r600_resource*)program->global_buffers[i];
744 if (!buffer) {
745 continue;
746 }
747 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
748 RADEON_USAGE_READWRITE,
749 RADEON_PRIO_COMPUTE_GLOBAL);
750 }
751
752 if (program->ir_type == PIPE_SHADER_IR_TGSI)
753 si_setup_tgsi_grid(sctx, info);
754
755 si_ce_pre_draw_synchronization(sctx);
756
757 si_emit_dispatch_packets(sctx, info);
758
759 si_ce_post_draw_synchronization(sctx);
760
761 sctx->compute_is_busy = true;
762 sctx->b.num_compute_calls++;
763 if (sctx->cs_shader_state.uses_scratch)
764 sctx->b.num_spill_compute_calls++;
765
766 if (cs_regalloc_hang)
767 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
768 }
769
770
771 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
772 struct si_compute *program = (struct si_compute *)state;
773 struct si_context *sctx = (struct si_context*)ctx;
774
775 if (!state) {
776 return;
777 }
778
779 if (program == sctx->cs_shader_state.program)
780 sctx->cs_shader_state.program = NULL;
781
782 if (program == sctx->cs_shader_state.emitted_program)
783 sctx->cs_shader_state.emitted_program = NULL;
784
785 si_shader_destroy(&program->shader);
786 FREE(program);
787 }
788
789 static void si_set_compute_resources(struct pipe_context * ctx_,
790 unsigned start, unsigned count,
791 struct pipe_surface ** surfaces) { }
792
793 void si_init_compute_functions(struct si_context *sctx)
794 {
795 sctx->b.b.create_compute_state = si_create_compute_state;
796 sctx->b.b.delete_compute_state = si_delete_compute_state;
797 sctx->b.b.bind_compute_state = si_bind_compute_state;
798 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
799 sctx->b.b.set_compute_resources = si_set_compute_resources;
800 sctx->b.b.set_global_binding = si_set_global_binding;
801 sctx->b.b.launch_grid = si_launch_grid;
802 }