2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "util/u_memory.h"
26 #include "radeon/r600_pipe_common.h"
27 #include "radeon/radeon_elf_util.h"
28 #include "radeon/radeon_llvm_util.h"
30 #include "radeon/r600_cs.h"
32 #include "si_shader.h"
35 #define MAX_GLOBAL_BUFFERS 20
38 struct si_context
*ctx
;
41 unsigned private_size
;
43 struct si_shader shader
;
44 unsigned num_user_sgprs
;
46 struct r600_resource
*input_buffer
;
47 struct pipe_resource
*global_buffers
[MAX_GLOBAL_BUFFERS
];
49 #if HAVE_LLVM < 0x0306
51 struct si_shader
*kernels
;
52 LLVMContextRef llvm_ctx
;
56 static void init_scratch_buffer(struct si_context
*sctx
, struct si_compute
*program
)
58 unsigned scratch_bytes
= 0;
59 uint64_t scratch_buffer_va
;
62 /* Compute the scratch buffer size using the maximum number of waves.
63 * This way we don't need to recompute it for each kernel launch. */
64 unsigned scratch_waves
= 32 * sctx
->screen
->b
.info
.max_compute_units
;
65 for (i
= 0; i
< program
->shader
.binary
.global_symbol_count
; i
++) {
67 program
->shader
.binary
.global_symbol_offsets
[i
];
68 unsigned scratch_bytes_needed
;
70 si_shader_binary_read_config(sctx
->screen
,
71 &program
->shader
, offset
);
72 scratch_bytes_needed
= program
->shader
.scratch_bytes_per_wave
;
73 scratch_bytes
= MAX2(scratch_bytes
, scratch_bytes_needed
);
76 if (scratch_bytes
== 0)
79 program
->shader
.scratch_bo
=
80 si_resource_create_custom(sctx
->b
.b
.screen
,
82 scratch_bytes
* scratch_waves
);
84 scratch_buffer_va
= program
->shader
.scratch_bo
->gpu_address
;
86 /* apply_scratch_relocs needs scratch_bytes_per_wave to be set
87 * to the maximum bytes needed, so it can compute the stride
90 program
->shader
.scratch_bytes_per_wave
= scratch_bytes
;
92 /* Patch the shader with the scratch buffer address. */
93 si_shader_apply_scratch_relocs(sctx
,
94 &program
->shader
, scratch_buffer_va
);
97 static void *si_create_compute_state(
98 struct pipe_context
*ctx
,
99 const struct pipe_compute_state
*cso
)
101 struct si_context
*sctx
= (struct si_context
*)ctx
;
102 struct si_compute
*program
= CALLOC_STRUCT(si_compute
);
103 const struct pipe_llvm_program_header
*header
;
107 code
= cso
->prog
+ sizeof(struct pipe_llvm_program_header
);
110 program
->local_size
= cso
->req_local_mem
;
111 program
->private_size
= cso
->req_private_mem
;
112 program
->input_size
= cso
->req_input_mem
;
114 #if HAVE_LLVM < 0x0306
117 program
->llvm_ctx
= LLVMContextCreate();
118 program
->num_kernels
= radeon_llvm_get_num_kernels(program
->llvm_ctx
,
119 code
, header
->num_bytes
);
120 program
->kernels
= CALLOC(sizeof(struct si_shader
),
121 program
->num_kernels
);
122 for (i
= 0; i
< program
->num_kernels
; i
++) {
123 LLVMModuleRef mod
= radeon_llvm_get_kernel_module(program
->llvm_ctx
, i
,
124 code
, header
->num_bytes
);
125 si_compile_llvm(sctx
->screen
, &program
->kernels
[i
], sctx
->tm
,
126 mod
, &sctx
->b
.debug
);
127 LLVMDisposeModule(mod
);
132 radeon_elf_read(code
, header
->num_bytes
, &program
->shader
.binary
);
134 /* init_scratch_buffer patches the shader code with the scratch address,
135 * so we need to call it before si_shader_binary_read() which uploads
136 * the shader code to the GPU.
138 init_scratch_buffer(sctx
, program
);
139 si_shader_binary_read(sctx
->screen
, &program
->shader
, &sctx
->b
.debug
);
142 program
->input_buffer
= si_resource_create_custom(sctx
->b
.b
.screen
,
143 PIPE_USAGE_IMMUTABLE
, program
->input_size
);
148 static void si_bind_compute_state(struct pipe_context
*ctx
, void *state
)
150 struct si_context
*sctx
= (struct si_context
*)ctx
;
151 sctx
->cs_shader_state
.program
= (struct si_compute
*)state
;
154 static void si_set_global_binding(
155 struct pipe_context
*ctx
, unsigned first
, unsigned n
,
156 struct pipe_resource
**resources
,
160 struct si_context
*sctx
= (struct si_context
*)ctx
;
161 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
164 for (i
= first
; i
< first
+ n
; i
++) {
165 pipe_resource_reference(&program
->global_buffers
[i
], NULL
);
170 for (i
= first
; i
< first
+ n
; i
++) {
173 pipe_resource_reference(&program
->global_buffers
[i
], resources
[i
]);
174 va
= r600_resource(resources
[i
])->gpu_address
;
175 offset
= util_le32_to_cpu(*handles
[i
]);
177 va
= util_cpu_to_le64(va
);
178 memcpy(handles
[i
], &va
, sizeof(va
));
183 * This function computes the value for R_00B860_COMPUTE_TMPRING_SIZE.WAVES
184 * /p block_layout is the number of threads in each work group.
185 * /p grid layout is the number of work groups.
187 static unsigned compute_num_waves_for_scratch(
188 const struct radeon_info
*info
,
189 const uint
*block_layout
,
190 const uint
*grid_layout
)
192 unsigned num_sh
= MAX2(info
->max_sh_per_se
, 1);
193 unsigned num_se
= MAX2(info
->max_se
, 1);
194 unsigned num_blocks
= 1;
195 unsigned threads_per_block
= 1;
196 unsigned waves_per_block
;
197 unsigned waves_per_sh
;
199 unsigned scratch_waves
;
202 for (i
= 0; i
< 3; i
++) {
203 threads_per_block
*= block_layout
[i
];
204 num_blocks
*= grid_layout
[i
];
207 waves_per_block
= align(threads_per_block
, 64) / 64;
208 waves
= waves_per_block
* num_blocks
;
209 waves_per_sh
= align(waves
, num_sh
* num_se
) / (num_sh
* num_se
);
210 scratch_waves
= waves_per_sh
* num_sh
* num_se
;
212 if (waves_per_block
> waves_per_sh
) {
213 scratch_waves
= waves_per_block
* num_sh
* num_se
;
216 return scratch_waves
;
219 static void si_launch_grid(
220 struct pipe_context
*ctx
,
221 const uint
*block_layout
, const uint
*grid_layout
,
222 uint32_t pc
, const void *input
)
224 struct si_context
*sctx
= (struct si_context
*)ctx
;
225 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
226 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
227 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
228 struct r600_resource
*input_buffer
= program
->input_buffer
;
229 unsigned kernel_args_size
;
230 unsigned num_work_size_bytes
= 36;
231 uint32_t kernel_args_offset
= 0;
232 uint32_t *kernel_args
;
233 uint64_t kernel_args_va
;
234 uint64_t scratch_buffer_va
= 0;
237 struct si_shader
*shader
= &program
->shader
;
239 unsigned num_waves_for_scratch
;
241 #if HAVE_LLVM < 0x0306
242 shader
= &program
->kernels
[pc
];
246 radeon_emit(cs
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0) | PKT3_SHADER_TYPE_S(1));
247 radeon_emit(cs
, 0x80000000);
248 radeon_emit(cs
, 0x80000000);
250 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
251 SI_CONTEXT_INV_GLOBAL_L2
|
252 SI_CONTEXT_INV_ICACHE
|
253 SI_CONTEXT_INV_SMEM_L1
|
254 SI_CONTEXT_FLUSH_WITH_INV_L2
|
255 SI_CONTEXT_FLAG_COMPUTE
;
256 si_emit_cache_flush(sctx
, NULL
);
258 pm4
->compute_pkt
= true;
260 #if HAVE_LLVM >= 0x0306
261 /* Read the config information */
262 si_shader_binary_read_config(sctx
->screen
, shader
, pc
);
265 /* Upload the kernel arguments */
267 /* The extra num_work_size_bytes are for work group / work item size information */
268 kernel_args_size
= program
->input_size
+ num_work_size_bytes
+ 8 /* For scratch va */;
270 kernel_args
= sctx
->b
.ws
->buffer_map(input_buffer
->buf
,
271 sctx
->b
.gfx
.cs
, PIPE_TRANSFER_WRITE
);
272 for (i
= 0; i
< 3; i
++) {
273 kernel_args
[i
] = grid_layout
[i
];
274 kernel_args
[i
+ 3] = grid_layout
[i
] * block_layout
[i
];
275 kernel_args
[i
+ 6] = block_layout
[i
];
278 num_waves_for_scratch
= compute_num_waves_for_scratch(
279 &sctx
->screen
->b
.info
, block_layout
, grid_layout
);
281 memcpy(kernel_args
+ (num_work_size_bytes
/ 4), input
, program
->input_size
);
283 if (shader
->scratch_bytes_per_wave
> 0) {
285 COMPUTE_DBG(sctx
->screen
, "Waves: %u; Scratch per wave: %u bytes; "
286 "Total Scratch: %u bytes\n", num_waves_for_scratch
,
287 shader
->scratch_bytes_per_wave
,
288 shader
->scratch_bytes_per_wave
*
289 num_waves_for_scratch
);
291 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
293 RADEON_USAGE_READWRITE
,
294 RADEON_PRIO_SCRATCH_BUFFER
);
296 scratch_buffer_va
= shader
->scratch_bo
->gpu_address
;
299 for (i
= 0; i
< (kernel_args_size
/ 4); i
++) {
300 COMPUTE_DBG(sctx
->screen
, "input %u : %u\n", i
,
304 kernel_args_va
= input_buffer
->gpu_address
;
305 kernel_args_va
+= kernel_args_offset
;
307 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, input_buffer
,
308 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
310 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
, kernel_args_va
);
311 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
+ 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) | S_008F04_STRIDE(0));
312 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
+ 8, scratch_buffer_va
);
313 si_pm4_set_reg(pm4
, R_00B900_COMPUTE_USER_DATA_0
+ 12,
314 S_008F04_BASE_ADDRESS_HI(scratch_buffer_va
>> 32)
315 | S_008F04_STRIDE(shader
->scratch_bytes_per_wave
/ 64));
317 si_pm4_set_reg(pm4
, R_00B810_COMPUTE_START_X
, 0);
318 si_pm4_set_reg(pm4
, R_00B814_COMPUTE_START_Y
, 0);
319 si_pm4_set_reg(pm4
, R_00B818_COMPUTE_START_Z
, 0);
321 si_pm4_set_reg(pm4
, R_00B81C_COMPUTE_NUM_THREAD_X
,
322 S_00B81C_NUM_THREAD_FULL(block_layout
[0]));
323 si_pm4_set_reg(pm4
, R_00B820_COMPUTE_NUM_THREAD_Y
,
324 S_00B820_NUM_THREAD_FULL(block_layout
[1]));
325 si_pm4_set_reg(pm4
, R_00B824_COMPUTE_NUM_THREAD_Z
,
326 S_00B824_NUM_THREAD_FULL(block_layout
[2]));
329 for (i
= 0; i
< MAX_GLOBAL_BUFFERS
; i
++) {
330 struct r600_resource
*buffer
=
331 (struct r600_resource
*)program
->global_buffers
[i
];
335 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, buffer
,
336 RADEON_USAGE_READWRITE
,
337 RADEON_PRIO_COMPUTE_GLOBAL
);
340 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
341 * and is now per pipe, so it should be handled in the
342 * kernel if we want to use something other than the default value,
343 * which is now 0x22f.
345 if (sctx
->b
.chip_class
<= SI
) {
346 /* XXX: This should be:
347 * (number of compute units) * 4 * (waves per simd) - 1 */
349 si_pm4_set_reg(pm4
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
350 0x190 /* Default value */);
353 shader_va
= shader
->bo
->gpu_address
;
355 #if HAVE_LLVM >= 0x0306
358 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, shader
->bo
,
359 RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
360 si_pm4_set_reg(pm4
, R_00B830_COMPUTE_PGM_LO
, shader_va
>> 8);
361 si_pm4_set_reg(pm4
, R_00B834_COMPUTE_PGM_HI
, shader_va
>> 40);
363 si_pm4_set_reg(pm4
, R_00B848_COMPUTE_PGM_RSRC1
, shader
->rsrc1
);
365 lds_blocks
= shader
->lds_size
;
366 /* XXX: We are over allocating LDS. For SI, the shader reports LDS in
367 * blocks of 256 bytes, so if there are 4 bytes lds allocated in
368 * the shader and 4 bytes allocated by the state tracker, then
369 * we will set LDS_SIZE to 512 bytes rather than 256.
371 if (sctx
->b
.chip_class
<= SI
) {
372 lds_blocks
+= align(program
->local_size
, 256) >> 8;
374 lds_blocks
+= align(program
->local_size
, 512) >> 9;
377 assert(lds_blocks
<= 0xFF);
379 shader
->rsrc2
&= C_00B84C_LDS_SIZE
;
380 shader
->rsrc2
|= S_00B84C_LDS_SIZE(lds_blocks
);
382 si_pm4_set_reg(pm4
, R_00B84C_COMPUTE_PGM_RSRC2
, shader
->rsrc2
);
383 si_pm4_set_reg(pm4
, R_00B854_COMPUTE_RESOURCE_LIMITS
, 0);
385 si_pm4_set_reg(pm4
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
,
386 S_00B858_SH0_CU_EN(0xffff /* Default value */)
387 | S_00B858_SH1_CU_EN(0xffff /* Default value */))
390 si_pm4_set_reg(pm4
, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1
,
391 S_00B85C_SH0_CU_EN(0xffff /* Default value */)
392 | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
395 num_waves_for_scratch
=
396 MIN2(num_waves_for_scratch
,
397 32 * sctx
->screen
->b
.info
.max_compute_units
);
398 si_pm4_set_reg(pm4
, R_00B860_COMPUTE_TMPRING_SIZE
,
399 /* The maximum value for WAVES is 32 * num CU.
400 * If you program this value incorrectly, the GPU will hang if
401 * COMPUTE_PGM_RSRC2.SCRATCH_EN is enabled.
403 S_00B860_WAVES(num_waves_for_scratch
)
404 | S_00B860_WAVESIZE(shader
->scratch_bytes_per_wave
>> 10))
407 si_pm4_cmd_begin(pm4
, PKT3_DISPATCH_DIRECT
);
408 si_pm4_cmd_add(pm4
, grid_layout
[0]); /* Thread groups DIM_X */
409 si_pm4_cmd_add(pm4
, grid_layout
[1]); /* Thread groups DIM_Y */
410 si_pm4_cmd_add(pm4
, grid_layout
[2]); /* Thread gropus DIM_Z */
411 si_pm4_cmd_add(pm4
, 1); /* DISPATCH_INITIATOR */
412 si_pm4_cmd_end(pm4
, false);
414 si_pm4_emit(sctx
, pm4
);
417 fprintf(stderr
, "cdw: %i\n", sctx
->cs
->cdw
);
418 for (i
= 0; i
< sctx
->cs
->cdw
; i
++) {
419 fprintf(stderr
, "%4i : 0x%08X\n", i
, sctx
->cs
->buf
[i
]);
423 si_pm4_free_state(sctx
, pm4
, ~0);
425 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
|
426 SI_CONTEXT_INV_VMEM_L1
|
427 SI_CONTEXT_INV_GLOBAL_L2
|
428 SI_CONTEXT_INV_ICACHE
|
429 SI_CONTEXT_INV_SMEM_L1
|
430 SI_CONTEXT_FLAG_COMPUTE
;
431 si_emit_cache_flush(sctx
, NULL
);
435 static void si_delete_compute_state(struct pipe_context
*ctx
, void* state
){
436 struct si_compute
*program
= (struct si_compute
*)state
;
442 #if HAVE_LLVM < 0x0306
443 if (program
->kernels
) {
444 for (int i
= 0; i
< program
->num_kernels
; i
++){
445 if (program
->kernels
[i
].bo
){
446 si_shader_destroy(&program
->kernels
[i
]);
449 FREE(program
->kernels
);
452 if (program
->llvm_ctx
){
453 LLVMContextDispose(program
->llvm_ctx
);
456 FREE(program
->shader
.binary
.config
);
457 FREE(program
->shader
.binary
.rodata
);
458 FREE(program
->shader
.binary
.global_symbol_offsets
);
459 si_shader_destroy(&program
->shader
);
462 pipe_resource_reference(
463 (struct pipe_resource
**)&program
->input_buffer
, NULL
);
468 static void si_set_compute_resources(struct pipe_context
* ctx_
,
469 unsigned start
, unsigned count
,
470 struct pipe_surface
** surfaces
) { }
472 void si_init_compute_functions(struct si_context
*sctx
)
474 sctx
->b
.b
.create_compute_state
= si_create_compute_state
;
475 sctx
->b
.b
.delete_compute_state
= si_delete_compute_state
;
476 sctx
->b
.b
.bind_compute_state
= si_bind_compute_state
;
477 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
478 sctx
->b
.b
.set_compute_resources
= si_set_compute_resources
;
479 sctx
->b
.b
.set_global_binding
= si_set_global_binding
;
480 sctx
->b
.b
.launch_grid
= si_launch_grid
;