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radeonsi: let internal compute dispatches tune WAVES_PER_SH
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "tgsi/tgsi_parse.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30
31 #include "amd_kernel_code_t.h"
32 #include "si_build_pm4.h"
33 #include "si_compute.h"
34
35 #define COMPUTE_DBG(rscreen, fmt, args...) \
36 do { \
37 if ((rscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
38 } while (0);
39
40 struct dispatch_packet {
41 uint16_t header;
42 uint16_t setup;
43 uint16_t workgroup_size_x;
44 uint16_t workgroup_size_y;
45 uint16_t workgroup_size_z;
46 uint16_t reserved0;
47 uint32_t grid_size_x;
48 uint32_t grid_size_y;
49 uint32_t grid_size_z;
50 uint32_t private_segment_size;
51 uint32_t group_segment_size;
52 uint64_t kernel_object;
53 uint64_t kernarg_address;
54 uint64_t reserved2;
55 };
56
57 static const amd_kernel_code_t *si_compute_get_code_object(
58 const struct si_compute *program,
59 uint64_t symbol_offset)
60 {
61 if (!program->use_code_object_v2) {
62 return NULL;
63 }
64 return (const amd_kernel_code_t*)
65 (program->shader.binary.code + symbol_offset);
66 }
67
68 static void code_object_to_config(const amd_kernel_code_t *code_object,
69 struct si_shader_config *out_config) {
70
71 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
72 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
73 out_config->num_sgprs = code_object->wavefront_sgpr_count;
74 out_config->num_vgprs = code_object->workitem_vgpr_count;
75 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
76 out_config->rsrc1 = rsrc1;
77 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
78 out_config->rsrc2 = rsrc2;
79 out_config->scratch_bytes_per_wave =
80 align(code_object->workitem_private_segment_byte_size * 64, 1024);
81 }
82
83 /* Asynchronous compute shader compilation. */
84 static void si_create_compute_state_async(void *job, int thread_index)
85 {
86 struct si_compute *program = (struct si_compute *)job;
87 struct si_shader *shader = &program->shader;
88 struct si_shader_selector sel;
89 struct ac_llvm_compiler *compiler;
90 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
91 struct si_screen *sscreen = program->screen;
92
93 assert(!debug->debug_message || debug->async);
94 assert(thread_index >= 0);
95 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
96 compiler = &sscreen->compiler[thread_index];
97
98 memset(&sel, 0, sizeof(sel));
99
100 sel.screen = sscreen;
101
102 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
103 tgsi_scan_shader(program->ir.tgsi, &sel.info);
104 sel.tokens = program->ir.tgsi;
105 } else {
106 assert(program->ir_type == PIPE_SHADER_IR_NIR);
107 sel.nir = program->ir.nir;
108
109 si_nir_scan_shader(sel.nir, &sel.info);
110 si_lower_nir(&sel);
111 }
112
113 /* Store the declared LDS size into tgsi_shader_info for the shader
114 * cache to include it.
115 */
116 sel.info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
117
118 sel.type = PIPE_SHADER_COMPUTE;
119 si_get_active_slot_masks(&sel.info,
120 &program->active_const_and_shader_buffers,
121 &program->active_samplers_and_images);
122
123 program->shader.selector = &sel;
124 program->shader.is_monolithic = true;
125 program->uses_grid_size = sel.info.uses_grid_size;
126 program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
127 program->uses_bindless_images = sel.info.uses_bindless_images;
128 program->reads_variable_block_size =
129 sel.info.uses_block_size &&
130 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
131 program->num_cs_user_data_dwords =
132 sel.info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
133
134 void *ir_binary = si_get_ir_binary(&sel);
135
136 /* Try to load the shader from the shader cache. */
137 mtx_lock(&sscreen->shader_cache_mutex);
138
139 if (ir_binary &&
140 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
141 mtx_unlock(&sscreen->shader_cache_mutex);
142
143 si_shader_dump_stats_for_shader_db(shader, debug);
144 si_shader_dump(sscreen, shader, debug, PIPE_SHADER_COMPUTE,
145 stderr, true);
146
147 if (si_shader_binary_upload(sscreen, shader))
148 program->shader.compilation_failed = true;
149 } else {
150 mtx_unlock(&sscreen->shader_cache_mutex);
151
152 if (si_shader_create(sscreen, compiler, &program->shader, debug)) {
153 program->shader.compilation_failed = true;
154
155 if (program->ir_type == PIPE_SHADER_IR_TGSI)
156 FREE(program->ir.tgsi);
157 program->shader.selector = NULL;
158 return;
159 }
160
161 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
162 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
163 (sel.info.uses_grid_size ? 3 : 0) +
164 (program->reads_variable_block_size ? 3 : 0) +
165 program->num_cs_user_data_dwords;
166
167 shader->config.rsrc1 =
168 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
169 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
170 S_00B848_DX10_CLAMP(1) |
171 S_00B848_FLOAT_MODE(shader->config.float_mode);
172
173 shader->config.rsrc2 =
174 S_00B84C_USER_SGPR(user_sgprs) |
175 S_00B84C_SCRATCH_EN(scratch_enabled) |
176 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
177 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
178 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
179 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
180 sel.info.uses_thread_id[1] ? 1 : 0) |
181 S_00B84C_LDS_SIZE(shader->config.lds_size);
182
183 if (ir_binary) {
184 mtx_lock(&sscreen->shader_cache_mutex);
185 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
186 FREE(ir_binary);
187 mtx_unlock(&sscreen->shader_cache_mutex);
188 }
189 }
190
191 if (program->ir_type == PIPE_SHADER_IR_TGSI)
192 FREE(program->ir.tgsi);
193
194 program->shader.selector = NULL;
195 }
196
197 static void *si_create_compute_state(
198 struct pipe_context *ctx,
199 const struct pipe_compute_state *cso)
200 {
201 struct si_context *sctx = (struct si_context *)ctx;
202 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
203 struct si_compute *program = CALLOC_STRUCT(si_compute);
204
205 pipe_reference_init(&program->reference, 1);
206 program->screen = (struct si_screen *)ctx->screen;
207 program->ir_type = cso->ir_type;
208 program->local_size = cso->req_local_mem;
209 program->private_size = cso->req_private_mem;
210 program->input_size = cso->req_input_mem;
211 program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
212
213 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
214 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
215 program->ir.tgsi = tgsi_dup_tokens(cso->prog);
216 if (!program->ir.tgsi) {
217 FREE(program);
218 return NULL;
219 }
220 } else {
221 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
222 program->ir.nir = (struct nir_shader *) cso->prog;
223 }
224
225 program->compiler_ctx_state.debug = sctx->debug;
226 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
227 p_atomic_inc(&sscreen->num_shaders_created);
228
229 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
230 &program->ready,
231 &program->compiler_ctx_state,
232 program, si_create_compute_state_async);
233 } else {
234 const struct pipe_llvm_program_header *header;
235 const char *code;
236 header = cso->prog;
237 code = cso->prog + sizeof(struct pipe_llvm_program_header);
238
239 ac_elf_read(code, header->num_bytes, &program->shader.binary);
240 if (program->use_code_object_v2) {
241 const amd_kernel_code_t *code_object =
242 si_compute_get_code_object(program, 0);
243 code_object_to_config(code_object, &program->shader.config);
244 if (program->shader.binary.reloc_count != 0) {
245 fprintf(stderr, "Error: %d unsupported relocations\n",
246 program->shader.binary.reloc_count);
247 FREE(program);
248 return NULL;
249 }
250 } else {
251 si_shader_binary_read_config(&program->shader.binary,
252 &program->shader.config, 0);
253 }
254 si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
255 PIPE_SHADER_COMPUTE, stderr, true);
256 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
257 fprintf(stderr, "LLVM failed to upload shader\n");
258 FREE(program);
259 return NULL;
260 }
261 }
262
263 return program;
264 }
265
266 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
267 {
268 struct si_context *sctx = (struct si_context*)ctx;
269 struct si_compute *program = (struct si_compute*)state;
270
271 sctx->cs_shader_state.program = program;
272 if (!program)
273 return;
274
275 /* Wait because we need active slot usage masks. */
276 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
277 util_queue_fence_wait(&program->ready);
278
279 si_set_active_descriptors(sctx,
280 SI_DESCS_FIRST_COMPUTE +
281 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
282 program->active_const_and_shader_buffers);
283 si_set_active_descriptors(sctx,
284 SI_DESCS_FIRST_COMPUTE +
285 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
286 program->active_samplers_and_images);
287 }
288
289 static void si_set_global_binding(
290 struct pipe_context *ctx, unsigned first, unsigned n,
291 struct pipe_resource **resources,
292 uint32_t **handles)
293 {
294 unsigned i;
295 struct si_context *sctx = (struct si_context*)ctx;
296 struct si_compute *program = sctx->cs_shader_state.program;
297
298 assert(first + n <= MAX_GLOBAL_BUFFERS);
299
300 if (!resources) {
301 for (i = 0; i < n; i++) {
302 pipe_resource_reference(&program->global_buffers[first + i], NULL);
303 }
304 return;
305 }
306
307 for (i = 0; i < n; i++) {
308 uint64_t va;
309 uint32_t offset;
310 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
311 va = r600_resource(resources[i])->gpu_address;
312 offset = util_le32_to_cpu(*handles[i]);
313 va += offset;
314 va = util_cpu_to_le64(va);
315 memcpy(handles[i], &va, sizeof(va));
316 }
317 }
318
319 static void si_initialize_compute(struct si_context *sctx)
320 {
321 struct radeon_cmdbuf *cs = sctx->gfx_cs;
322 uint64_t bc_va;
323
324 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
325 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
326 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
327 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
328
329 if (sctx->chip_class >= CIK) {
330 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
331 radeon_set_sh_reg_seq(cs,
332 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
333 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
334 S_00B864_SH1_CU_EN(0xffff));
335 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
336 S_00B868_SH1_CU_EN(0xffff));
337 }
338
339 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
340 * and is now per pipe, so it should be handled in the
341 * kernel if we want to use something other than the default value,
342 * which is now 0x22f.
343 */
344 if (sctx->chip_class <= SI) {
345 /* XXX: This should be:
346 * (number of compute units) * 4 * (waves per simd) - 1 */
347
348 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
349 0x190 /* Default value */);
350 }
351
352 /* Set the pointer to border colors. */
353 bc_va = sctx->border_color_buffer->gpu_address;
354
355 if (sctx->chip_class >= CIK) {
356 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
357 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
358 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
359 } else {
360 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
361 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
362 bc_va >> 8);
363 }
364 }
365
366 sctx->cs_shader_state.emitted_program = NULL;
367 sctx->cs_shader_state.initialized = true;
368 }
369
370 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
371 struct si_shader *shader,
372 struct si_shader_config *config)
373 {
374 uint64_t scratch_bo_size, scratch_needed;
375 scratch_bo_size = 0;
376 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
377 if (sctx->compute_scratch_buffer)
378 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
379
380 if (scratch_bo_size < scratch_needed) {
381 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
382
383 sctx->compute_scratch_buffer =
384 si_aligned_buffer_create(&sctx->screen->b,
385 SI_RESOURCE_FLAG_UNMAPPABLE,
386 PIPE_USAGE_DEFAULT,
387 scratch_needed, 256);
388
389 if (!sctx->compute_scratch_buffer)
390 return false;
391 }
392
393 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
394 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
395
396 si_shader_apply_scratch_relocs(shader, scratch_va);
397
398 if (si_shader_binary_upload(sctx->screen, shader))
399 return false;
400
401 r600_resource_reference(&shader->scratch_bo,
402 sctx->compute_scratch_buffer);
403 }
404
405 return true;
406 }
407
408 static bool si_switch_compute_shader(struct si_context *sctx,
409 struct si_compute *program,
410 struct si_shader *shader,
411 const amd_kernel_code_t *code_object,
412 unsigned offset)
413 {
414 struct radeon_cmdbuf *cs = sctx->gfx_cs;
415 struct si_shader_config inline_config = {0};
416 struct si_shader_config *config;
417 uint64_t shader_va;
418
419 if (sctx->cs_shader_state.emitted_program == program &&
420 sctx->cs_shader_state.offset == offset)
421 return true;
422
423 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
424 config = &shader->config;
425 } else {
426 unsigned lds_blocks;
427
428 config = &inline_config;
429 if (code_object) {
430 code_object_to_config(code_object, config);
431 } else {
432 si_shader_binary_read_config(&shader->binary, config, offset);
433 }
434
435 lds_blocks = config->lds_size;
436 /* XXX: We are over allocating LDS. For SI, the shader reports
437 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
438 * allocated in the shader and 4 bytes allocated by the state
439 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
440 */
441 if (sctx->chip_class <= SI) {
442 lds_blocks += align(program->local_size, 256) >> 8;
443 } else {
444 lds_blocks += align(program->local_size, 512) >> 9;
445 }
446
447 /* TODO: use si_multiwave_lds_size_workaround */
448 assert(lds_blocks <= 0xFF);
449
450 config->rsrc2 &= C_00B84C_LDS_SIZE;
451 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
452 }
453
454 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
455 return false;
456
457 if (shader->scratch_bo) {
458 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
459 "Total Scratch: %u bytes\n", sctx->scratch_waves,
460 config->scratch_bytes_per_wave,
461 config->scratch_bytes_per_wave *
462 sctx->scratch_waves);
463
464 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
465 shader->scratch_bo, RADEON_USAGE_READWRITE,
466 RADEON_PRIO_SCRATCH_BUFFER);
467 }
468
469 /* Prefetch the compute shader to TC L2.
470 *
471 * We should also prefetch graphics shaders if a compute dispatch was
472 * the last command, and the compute shader if a draw call was the last
473 * command. However, that would add more complexity and we're likely
474 * to get a shader state change in that case anyway.
475 */
476 if (sctx->chip_class >= CIK) {
477 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
478 0, program->shader.bo->b.b.width0);
479 }
480
481 shader_va = shader->bo->gpu_address + offset;
482 if (program->use_code_object_v2) {
483 /* Shader code is placed after the amd_kernel_code_t
484 * struct. */
485 shader_va += sizeof(amd_kernel_code_t);
486 }
487
488 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
489 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
490
491 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
492 radeon_emit(cs, shader_va >> 8);
493 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
494
495 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
496 radeon_emit(cs, config->rsrc1);
497 radeon_emit(cs, config->rsrc2);
498
499 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
500 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
501
502 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
503 S_00B860_WAVES(sctx->scratch_waves)
504 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
505
506 sctx->cs_shader_state.emitted_program = program;
507 sctx->cs_shader_state.offset = offset;
508 sctx->cs_shader_state.uses_scratch =
509 config->scratch_bytes_per_wave != 0;
510
511 return true;
512 }
513
514 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
515 const amd_kernel_code_t *code_object,
516 unsigned user_sgpr)
517 {
518 struct radeon_cmdbuf *cs = sctx->gfx_cs;
519 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
520
521 unsigned max_private_element_size = AMD_HSA_BITS_GET(
522 code_object->code_properties,
523 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
524
525 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
526 uint32_t scratch_dword1 =
527 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
528 S_008F04_SWIZZLE_ENABLE(1);
529
530 /* Disable address clamping */
531 uint32_t scratch_dword2 = 0xffffffff;
532 uint32_t scratch_dword3 =
533 S_008F0C_INDEX_STRIDE(3) |
534 S_008F0C_ADD_TID_ENABLE(1);
535
536 if (sctx->chip_class >= GFX9) {
537 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
538 } else {
539 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
540
541 if (sctx->chip_class < VI) {
542 /* BUF_DATA_FORMAT is ignored, but it cannot be
543 * BUF_DATA_FORMAT_INVALID. */
544 scratch_dword3 |=
545 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
546 }
547 }
548
549 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
550 (user_sgpr * 4), 4);
551 radeon_emit(cs, scratch_dword0);
552 radeon_emit(cs, scratch_dword1);
553 radeon_emit(cs, scratch_dword2);
554 radeon_emit(cs, scratch_dword3);
555 }
556
557 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
558 const amd_kernel_code_t *code_object,
559 const struct pipe_grid_info *info,
560 uint64_t kernel_args_va)
561 {
562 struct si_compute *program = sctx->cs_shader_state.program;
563 struct radeon_cmdbuf *cs = sctx->gfx_cs;
564
565 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
566 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
567 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
568 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
569 };
570
571 unsigned i, user_sgpr = 0;
572 if (AMD_HSA_BITS_GET(code_object->code_properties,
573 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
574 if (code_object->workitem_private_segment_byte_size > 0) {
575 setup_scratch_rsrc_user_sgprs(sctx, code_object,
576 user_sgpr);
577 }
578 user_sgpr += 4;
579 }
580
581 if (AMD_HSA_BITS_GET(code_object->code_properties,
582 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
583 struct dispatch_packet dispatch;
584 unsigned dispatch_offset;
585 struct r600_resource *dispatch_buf = NULL;
586 uint64_t dispatch_va;
587
588 /* Upload dispatch ptr */
589 memset(&dispatch, 0, sizeof(dispatch));
590
591 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
592 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
593 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
594
595 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
596 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
597 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
598
599 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
600 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
601
602 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
603
604 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
605 256, &dispatch, &dispatch_offset,
606 (struct pipe_resource**)&dispatch_buf);
607
608 if (!dispatch_buf) {
609 fprintf(stderr, "Error: Failed to allocate dispatch "
610 "packet.");
611 }
612 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
613 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
614
615 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
616
617 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
618 (user_sgpr * 4), 2);
619 radeon_emit(cs, dispatch_va);
620 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
621 S_008F04_STRIDE(0));
622
623 r600_resource_reference(&dispatch_buf, NULL);
624 user_sgpr += 2;
625 }
626
627 if (AMD_HSA_BITS_GET(code_object->code_properties,
628 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
629 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
630 (user_sgpr * 4), 2);
631 radeon_emit(cs, kernel_args_va);
632 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
633 S_008F04_STRIDE(0));
634 user_sgpr += 2;
635 }
636
637 for (i = 0; i < 3 && user_sgpr < 16; i++) {
638 if (code_object->code_properties & workgroup_count_masks[i]) {
639 radeon_set_sh_reg_seq(cs,
640 R_00B900_COMPUTE_USER_DATA_0 +
641 (user_sgpr * 4), 1);
642 radeon_emit(cs, info->grid[i]);
643 user_sgpr += 1;
644 }
645 }
646 }
647
648 static bool si_upload_compute_input(struct si_context *sctx,
649 const amd_kernel_code_t *code_object,
650 const struct pipe_grid_info *info)
651 {
652 struct radeon_cmdbuf *cs = sctx->gfx_cs;
653 struct si_compute *program = sctx->cs_shader_state.program;
654 struct r600_resource *input_buffer = NULL;
655 unsigned kernel_args_size;
656 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
657 uint32_t kernel_args_offset = 0;
658 uint32_t *kernel_args;
659 void *kernel_args_ptr;
660 uint64_t kernel_args_va;
661 unsigned i;
662
663 /* The extra num_work_size_bytes are for work group / work item size information */
664 kernel_args_size = program->input_size + num_work_size_bytes;
665
666 u_upload_alloc(sctx->b.const_uploader, 0, kernel_args_size,
667 sctx->screen->info.tcc_cache_line_size,
668 &kernel_args_offset,
669 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
670
671 if (unlikely(!kernel_args_ptr))
672 return false;
673
674 kernel_args = (uint32_t*)kernel_args_ptr;
675 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
676
677 if (!code_object) {
678 for (i = 0; i < 3; i++) {
679 kernel_args[i] = util_cpu_to_le32(info->grid[i]);
680 kernel_args[i + 3] = util_cpu_to_le32(info->grid[i] * info->block[i]);
681 kernel_args[i + 6] = util_cpu_to_le32(info->block[i]);
682 }
683 }
684
685 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
686 program->input_size);
687
688
689 for (i = 0; i < (kernel_args_size / 4); i++) {
690 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
691 kernel_args[i]);
692 }
693
694
695 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
696 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
697
698 if (code_object) {
699 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
700 } else {
701 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
702 radeon_emit(cs, kernel_args_va);
703 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
704 S_008F04_STRIDE(0));
705 }
706
707 r600_resource_reference(&input_buffer, NULL);
708
709 return true;
710 }
711
712 static void si_setup_tgsi_user_data(struct si_context *sctx,
713 const struct pipe_grid_info *info)
714 {
715 struct si_compute *program = sctx->cs_shader_state.program;
716 struct radeon_cmdbuf *cs = sctx->gfx_cs;
717 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
718 4 * SI_NUM_RESOURCE_SGPRS;
719 unsigned block_size_reg = grid_size_reg +
720 /* 12 bytes = 3 dwords. */
721 12 * program->uses_grid_size;
722 unsigned cs_user_data_reg = block_size_reg +
723 12 * program->reads_variable_block_size;
724
725 if (info->indirect) {
726 if (program->uses_grid_size) {
727 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
728 uint64_t va = base_va + info->indirect_offset;
729 int i;
730
731 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
732 r600_resource(info->indirect),
733 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
734
735 for (i = 0; i < 3; ++i) {
736 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
737 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
738 COPY_DATA_DST_SEL(COPY_DATA_REG));
739 radeon_emit(cs, (va + 4 * i));
740 radeon_emit(cs, (va + 4 * i) >> 32);
741 radeon_emit(cs, (grid_size_reg >> 2) + i);
742 radeon_emit(cs, 0);
743 }
744 }
745 } else {
746 if (program->uses_grid_size) {
747 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
748 radeon_emit(cs, info->grid[0]);
749 radeon_emit(cs, info->grid[1]);
750 radeon_emit(cs, info->grid[2]);
751 }
752 if (program->reads_variable_block_size) {
753 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
754 radeon_emit(cs, info->block[0]);
755 radeon_emit(cs, info->block[1]);
756 radeon_emit(cs, info->block[2]);
757 }
758 }
759
760 if (program->num_cs_user_data_dwords) {
761 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
762 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
763 }
764 }
765
766 static void si_emit_dispatch_packets(struct si_context *sctx,
767 const struct pipe_grid_info *info)
768 {
769 struct si_screen *sscreen = sctx->screen;
770 struct radeon_cmdbuf *cs = sctx->gfx_cs;
771 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
772 unsigned waves_per_threadgroup =
773 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
774 unsigned compute_resource_limits =
775 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
776
777 if (sctx->chip_class >= CIK) {
778 unsigned num_cu_per_se = sscreen->info.num_good_compute_units /
779 sscreen->info.max_se;
780
781 /* Force even distribution on all SIMDs in CU if the workgroup
782 * size is 64. This has shown some good improvements if # of CUs
783 * per SE is not a multiple of 4.
784 */
785 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
786 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
787
788 compute_resource_limits |= S_00B854_WAVES_PER_SH(sctx->cs_max_waves_per_sh);
789 } else {
790 /* SI */
791 if (sctx->cs_max_waves_per_sh) {
792 unsigned limit_div16 = DIV_ROUND_UP(sctx->cs_max_waves_per_sh, 16);
793 compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
794 }
795 }
796
797 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
798 compute_resource_limits);
799
800 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
801 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
802 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
803 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
804
805 unsigned dispatch_initiator =
806 S_00B800_COMPUTE_SHADER_EN(1) |
807 S_00B800_FORCE_START_AT_000(1) |
808 /* If the KMD allows it (there is a KMD hw register for it),
809 * allow launching waves out-of-order. (same as Vulkan) */
810 S_00B800_ORDER_MODE(sctx->chip_class >= CIK);
811
812 if (info->indirect) {
813 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
814
815 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
816 r600_resource(info->indirect),
817 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
818
819 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
820 PKT3_SHADER_TYPE_S(1));
821 radeon_emit(cs, 1);
822 radeon_emit(cs, base_va);
823 radeon_emit(cs, base_va >> 32);
824
825 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
826 PKT3_SHADER_TYPE_S(1));
827 radeon_emit(cs, info->indirect_offset);
828 radeon_emit(cs, dispatch_initiator);
829 } else {
830 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
831 PKT3_SHADER_TYPE_S(1));
832 radeon_emit(cs, info->grid[0]);
833 radeon_emit(cs, info->grid[1]);
834 radeon_emit(cs, info->grid[2]);
835 radeon_emit(cs, dispatch_initiator);
836 }
837 }
838
839
840 static void si_launch_grid(
841 struct pipe_context *ctx, const struct pipe_grid_info *info)
842 {
843 struct si_context *sctx = (struct si_context*)ctx;
844 struct si_compute *program = sctx->cs_shader_state.program;
845 const amd_kernel_code_t *code_object =
846 si_compute_get_code_object(program, info->pc);
847 int i;
848 /* HW bug workaround when CS threadgroups > 256 threads and async
849 * compute isn't used, i.e. only one compute job can run at a time.
850 * If async compute is possible, the threadgroup size must be limited
851 * to 256 threads on all queues to avoid the bug.
852 * Only SI and certain CIK chips are affected.
853 */
854 bool cs_regalloc_hang =
855 (sctx->chip_class == SI ||
856 sctx->family == CHIP_BONAIRE ||
857 sctx->family == CHIP_KABINI) &&
858 info->block[0] * info->block[1] * info->block[2] > 256;
859
860 if (cs_regalloc_hang)
861 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
862 SI_CONTEXT_CS_PARTIAL_FLUSH;
863
864 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
865 program->shader.compilation_failed)
866 return;
867
868 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
869 si_update_fb_dirtiness_after_rendering(sctx);
870 sctx->last_num_draw_calls = sctx->num_draw_calls;
871 }
872
873 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
874
875 /* Add buffer sizes for memory checking in need_cs_space. */
876 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
877 /* TODO: add the scratch buffer */
878
879 if (info->indirect) {
880 si_context_add_resource_size(sctx, info->indirect);
881
882 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
883 if (sctx->chip_class <= VI &&
884 r600_resource(info->indirect)->TC_L2_dirty) {
885 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
886 r600_resource(info->indirect)->TC_L2_dirty = false;
887 }
888 }
889
890 si_need_gfx_cs_space(sctx);
891
892 if (!sctx->cs_shader_state.initialized)
893 si_initialize_compute(sctx);
894
895 if (sctx->flags)
896 si_emit_cache_flush(sctx);
897
898 if (!si_switch_compute_shader(sctx, program, &program->shader,
899 code_object, info->pc))
900 return;
901
902 si_upload_compute_shader_descriptors(sctx);
903 si_emit_compute_shader_pointers(sctx);
904
905 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
906 sctx->atoms.s.render_cond.emit(sctx);
907 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
908 }
909
910 if ((program->input_size ||
911 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
912 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
913 return;
914 }
915
916 /* Global buffers */
917 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
918 struct r600_resource *buffer =
919 r600_resource(program->global_buffers[i]);
920 if (!buffer) {
921 continue;
922 }
923 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
924 RADEON_USAGE_READWRITE,
925 RADEON_PRIO_COMPUTE_GLOBAL);
926 }
927
928 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
929 si_setup_tgsi_user_data(sctx, info);
930
931 si_emit_dispatch_packets(sctx, info);
932
933 if (unlikely(sctx->current_saved_cs)) {
934 si_trace_emit(sctx);
935 si_log_compute_state(sctx, sctx->log);
936 }
937
938 sctx->compute_is_busy = true;
939 sctx->num_compute_calls++;
940 if (sctx->cs_shader_state.uses_scratch)
941 sctx->num_spill_compute_calls++;
942
943 if (cs_regalloc_hang)
944 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
945 }
946
947 void si_destroy_compute(struct si_compute *program)
948 {
949 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
950 util_queue_drop_job(&program->screen->shader_compiler_queue,
951 &program->ready);
952 util_queue_fence_destroy(&program->ready);
953 }
954
955 si_shader_destroy(&program->shader);
956 FREE(program);
957 }
958
959 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
960 struct si_compute *program = (struct si_compute *)state;
961 struct si_context *sctx = (struct si_context*)ctx;
962
963 if (!state)
964 return;
965
966 if (program == sctx->cs_shader_state.program)
967 sctx->cs_shader_state.program = NULL;
968
969 if (program == sctx->cs_shader_state.emitted_program)
970 sctx->cs_shader_state.emitted_program = NULL;
971
972 si_compute_reference(&program, NULL);
973 }
974
975 static void si_set_compute_resources(struct pipe_context * ctx_,
976 unsigned start, unsigned count,
977 struct pipe_surface ** surfaces) { }
978
979 void si_init_compute_functions(struct si_context *sctx)
980 {
981 sctx->b.create_compute_state = si_create_compute_state;
982 sctx->b.delete_compute_state = si_delete_compute_state;
983 sctx->b.bind_compute_state = si_bind_compute_state;
984 sctx->b.set_compute_resources = si_set_compute_resources;
985 sctx->b.set_global_binding = si_set_global_binding;
986 sctx->b.launch_grid = si_launch_grid;
987 }