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radeonsi/nir: implement subgroup system values for SPIR-V
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "nir/tgsi_to_nir.h"
27 #include "tgsi/tgsi_parse.h"
28 #include "util/u_async_debug.h"
29 #include "util/u_memory.h"
30 #include "util/u_upload_mgr.h"
31
32 #include "ac_rtld.h"
33 #include "amd_kernel_code_t.h"
34 #include "si_build_pm4.h"
35 #include "si_compute.h"
36
37 #define COMPUTE_DBG(sscreen, fmt, args...) \
38 do { \
39 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
40 } while (0);
41
42 struct dispatch_packet {
43 uint16_t header;
44 uint16_t setup;
45 uint16_t workgroup_size_x;
46 uint16_t workgroup_size_y;
47 uint16_t workgroup_size_z;
48 uint16_t reserved0;
49 uint32_t grid_size_x;
50 uint32_t grid_size_y;
51 uint32_t grid_size_z;
52 uint32_t private_segment_size;
53 uint32_t group_segment_size;
54 uint64_t kernel_object;
55 uint64_t kernarg_address;
56 uint64_t reserved2;
57 };
58
59 static const amd_kernel_code_t *si_compute_get_code_object(
60 const struct si_compute *program,
61 uint64_t symbol_offset)
62 {
63 const struct si_shader_selector *sel = &program->sel;
64
65 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
66 return NULL;
67
68 struct ac_rtld_binary rtld;
69 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
70 .info = &sel->screen->info,
71 .shader_type = MESA_SHADER_COMPUTE,
72 .wave_size = sel->screen->compute_wave_size,
73 .num_parts = 1,
74 .elf_ptrs = &program->shader.binary.elf_buffer,
75 .elf_sizes = &program->shader.binary.elf_size }))
76 return NULL;
77
78 const amd_kernel_code_t *result = NULL;
79 const char *text;
80 size_t size;
81 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
82 goto out;
83
84 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
85 goto out;
86
87 result = (const amd_kernel_code_t*)(text + symbol_offset);
88
89 out:
90 ac_rtld_close(&rtld);
91 return result;
92 }
93
94 static void code_object_to_config(const amd_kernel_code_t *code_object,
95 struct ac_shader_config *out_config) {
96
97 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
98 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
99 out_config->num_sgprs = code_object->wavefront_sgpr_count;
100 out_config->num_vgprs = code_object->workitem_vgpr_count;
101 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
102 out_config->rsrc1 = rsrc1;
103 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
104 out_config->rsrc2 = rsrc2;
105 out_config->scratch_bytes_per_wave =
106 align(code_object->workitem_private_segment_byte_size * 64, 1024);
107 }
108
109 /* Asynchronous compute shader compilation. */
110 static void si_create_compute_state_async(void *job, int thread_index)
111 {
112 struct si_compute *program = (struct si_compute *)job;
113 struct si_shader_selector *sel = &program->sel;
114 struct si_shader *shader = &program->shader;
115 struct ac_llvm_compiler *compiler;
116 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
117 struct si_screen *sscreen = sel->screen;
118
119 assert(!debug->debug_message || debug->async);
120 assert(thread_index >= 0);
121 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
122 compiler = &sscreen->compiler[thread_index];
123
124 if (!compiler->passes)
125 si_init_compiler(sscreen, compiler);
126
127 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
128 tgsi_scan_shader(sel->tokens, &sel->info);
129 } else {
130 assert(program->ir_type == PIPE_SHADER_IR_NIR);
131
132 si_nir_scan_shader(sel->nir, &sel->info);
133 }
134
135 /* Store the declared LDS size into tgsi_shader_info for the shader
136 * cache to include it.
137 */
138 sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
139
140 si_get_active_slot_masks(&sel->info,
141 &sel->active_const_and_shader_buffers,
142 &sel->active_samplers_and_images);
143
144 program->shader.is_monolithic = true;
145 program->reads_variable_block_size =
146 sel->info.uses_block_size &&
147 sel->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
148 program->num_cs_user_data_dwords =
149 sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
150
151 unsigned char ir_sha1_cache_key[20];
152 si_get_ir_cache_key(sel, false, false, ir_sha1_cache_key);
153
154 /* Try to load the shader from the shader cache. */
155 simple_mtx_lock(&sscreen->shader_cache_mutex);
156
157 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
158 simple_mtx_unlock(&sscreen->shader_cache_mutex);
159
160 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
161 si_shader_dump(sscreen, shader, debug, stderr, true);
162
163 if (!si_shader_binary_upload(sscreen, shader, 0))
164 program->shader.compilation_failed = true;
165 } else {
166 simple_mtx_unlock(&sscreen->shader_cache_mutex);
167
168 if (!si_shader_create(sscreen, compiler, &program->shader, debug)) {
169 program->shader.compilation_failed = true;
170
171 if (program->ir_type == PIPE_SHADER_IR_TGSI)
172 FREE(sel->tokens);
173 return;
174 }
175
176 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
177 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
178 (sel->info.uses_grid_size ? 3 : 0) +
179 (program->reads_variable_block_size ? 3 : 0) +
180 program->num_cs_user_data_dwords;
181
182 shader->config.rsrc1 =
183 S_00B848_VGPRS((shader->config.num_vgprs - 1) /
184 (sscreen->compute_wave_size == 32 ? 8 : 4)) |
185 S_00B848_DX10_CLAMP(1) |
186 S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
187 S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
188 S_00B848_FLOAT_MODE(shader->config.float_mode);
189
190 if (sscreen->info.chip_class < GFX10) {
191 shader->config.rsrc1 |=
192 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
193 }
194
195 shader->config.rsrc2 =
196 S_00B84C_USER_SGPR(user_sgprs) |
197 S_00B84C_SCRATCH_EN(scratch_enabled) |
198 S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
199 S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
200 S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
201 S_00B84C_TG_SIZE_EN(sel->info.uses_subgroup_info) |
202 S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2] ? 2 :
203 sel->info.uses_thread_id[1] ? 1 : 0) |
204 S_00B84C_LDS_SIZE(shader->config.lds_size);
205
206 simple_mtx_lock(&sscreen->shader_cache_mutex);
207 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
208 shader, true);
209 simple_mtx_unlock(&sscreen->shader_cache_mutex);
210 }
211
212 FREE(sel->tokens);
213 sel->tokens = NULL;
214 ralloc_free(sel->nir);
215 sel->nir = NULL;
216 }
217
218 static void *si_create_compute_state(
219 struct pipe_context *ctx,
220 const struct pipe_compute_state *cso)
221 {
222 struct si_context *sctx = (struct si_context *)ctx;
223 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
224 struct si_compute *program = CALLOC_STRUCT(si_compute);
225 struct si_shader_selector *sel = &program->sel;
226
227 pipe_reference_init(&sel->reference, 1);
228 sel->type = PIPE_SHADER_COMPUTE;
229 sel->screen = sscreen;
230 program->shader.selector = &program->sel;
231 program->ir_type = cso->ir_type;
232 program->local_size = cso->req_local_mem;
233 program->private_size = cso->req_private_mem;
234 program->input_size = cso->req_input_mem;
235
236 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
237 if (sscreen->options.enable_nir &&
238 cso->ir_type == PIPE_SHADER_IR_TGSI) {
239 program->ir_type = PIPE_SHADER_IR_NIR;
240 sel->nir = tgsi_to_nir(cso->prog, ctx->screen);
241 } else if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
242 sel->tokens = tgsi_dup_tokens(cso->prog);
243 if (!sel->tokens) {
244 FREE(program);
245 return NULL;
246 }
247 } else {
248 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
249 sel->nir = (struct nir_shader *) cso->prog;
250 }
251
252 sel->compiler_ctx_state.debug = sctx->debug;
253 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
254 p_atomic_inc(&sscreen->num_shaders_created);
255
256 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
257 &sel->ready,
258 &sel->compiler_ctx_state,
259 program, si_create_compute_state_async);
260 } else {
261 const struct pipe_binary_program_header *header;
262 header = cso->prog;
263
264 program->shader.binary.elf_size = header->num_bytes;
265 program->shader.binary.elf_buffer = malloc(header->num_bytes);
266 if (!program->shader.binary.elf_buffer) {
267 FREE(program);
268 return NULL;
269 }
270 memcpy((void *)program->shader.binary.elf_buffer, header->blob, header->num_bytes);
271
272 const amd_kernel_code_t *code_object =
273 si_compute_get_code_object(program, 0);
274 code_object_to_config(code_object, &program->shader.config);
275
276 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
277 if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
278 fprintf(stderr, "LLVM failed to upload shader\n");
279 free((void *)program->shader.binary.elf_buffer);
280 FREE(program);
281 return NULL;
282 }
283 }
284
285 return program;
286 }
287
288 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
289 {
290 struct si_context *sctx = (struct si_context*)ctx;
291 struct si_compute *program = (struct si_compute*)state;
292 struct si_shader_selector *sel = &program->sel;
293
294 sctx->cs_shader_state.program = program;
295 if (!program)
296 return;
297
298 /* Wait because we need active slot usage masks. */
299 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
300 util_queue_fence_wait(&sel->ready);
301
302 si_set_active_descriptors(sctx,
303 SI_DESCS_FIRST_COMPUTE +
304 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
305 sel->active_const_and_shader_buffers);
306 si_set_active_descriptors(sctx,
307 SI_DESCS_FIRST_COMPUTE +
308 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
309 sel->active_samplers_and_images);
310 }
311
312 static void si_set_global_binding(
313 struct pipe_context *ctx, unsigned first, unsigned n,
314 struct pipe_resource **resources,
315 uint32_t **handles)
316 {
317 unsigned i;
318 struct si_context *sctx = (struct si_context*)ctx;
319 struct si_compute *program = sctx->cs_shader_state.program;
320
321 if (first + n > program->max_global_buffers) {
322 unsigned old_max = program->max_global_buffers;
323 program->max_global_buffers = first + n;
324 program->global_buffers =
325 realloc(program->global_buffers,
326 program->max_global_buffers *
327 sizeof(program->global_buffers[0]));
328 if (!program->global_buffers) {
329 fprintf(stderr, "radeonsi: failed to allocate compute global_buffers\n");
330 return;
331 }
332
333 memset(&program->global_buffers[old_max], 0,
334 (program->max_global_buffers - old_max) *
335 sizeof(program->global_buffers[0]));
336 }
337
338 if (!resources) {
339 for (i = 0; i < n; i++) {
340 pipe_resource_reference(&program->global_buffers[first + i], NULL);
341 }
342 return;
343 }
344
345 for (i = 0; i < n; i++) {
346 uint64_t va;
347 uint32_t offset;
348 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
349 va = si_resource(resources[i])->gpu_address;
350 offset = util_le32_to_cpu(*handles[i]);
351 va += offset;
352 va = util_cpu_to_le64(va);
353 memcpy(handles[i], &va, sizeof(va));
354 }
355 }
356
357 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
358 {
359 uint64_t bc_va;
360
361 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
362 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
363 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
364 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
365 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
366
367 if (sctx->chip_class >= GFX7) {
368 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
369 radeon_set_sh_reg_seq(cs,
370 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
371 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
372 S_00B858_SH1_CU_EN(0xffff));
373 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
374 S_00B858_SH1_CU_EN(0xffff));
375 }
376
377 if (sctx->chip_class >= GFX10)
378 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
379
380 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
381 * and is now per pipe, so it should be handled in the
382 * kernel if we want to use something other than the default value,
383 * which is now 0x22f.
384 */
385 if (sctx->chip_class <= GFX6) {
386 /* XXX: This should be:
387 * (number of compute units) * 4 * (waves per simd) - 1 */
388
389 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
390 0x190 /* Default value */);
391 }
392
393 /* Set the pointer to border colors. */
394 bc_va = sctx->border_color_buffer->gpu_address;
395
396 if (sctx->chip_class >= GFX7) {
397 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
398 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
399 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
400 } else {
401 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
402 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
403 bc_va >> 8);
404 }
405 }
406 }
407
408 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
409 struct si_shader *shader,
410 struct ac_shader_config *config)
411 {
412 uint64_t scratch_bo_size, scratch_needed;
413 scratch_bo_size = 0;
414 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
415 if (sctx->compute_scratch_buffer)
416 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
417
418 if (scratch_bo_size < scratch_needed) {
419 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
420
421 sctx->compute_scratch_buffer =
422 si_aligned_buffer_create(&sctx->screen->b,
423 SI_RESOURCE_FLAG_UNMAPPABLE,
424 PIPE_USAGE_DEFAULT,
425 scratch_needed,
426 sctx->screen->info.pte_fragment_size);
427
428 if (!sctx->compute_scratch_buffer)
429 return false;
430 }
431
432 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
433 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
434
435 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
436 return false;
437
438 si_resource_reference(&shader->scratch_bo,
439 sctx->compute_scratch_buffer);
440 }
441
442 return true;
443 }
444
445 static bool si_switch_compute_shader(struct si_context *sctx,
446 struct si_compute *program,
447 struct si_shader *shader,
448 const amd_kernel_code_t *code_object,
449 unsigned offset)
450 {
451 struct radeon_cmdbuf *cs = sctx->gfx_cs;
452 struct ac_shader_config inline_config = {0};
453 struct ac_shader_config *config;
454 uint64_t shader_va;
455
456 if (sctx->cs_shader_state.emitted_program == program &&
457 sctx->cs_shader_state.offset == offset)
458 return true;
459
460 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
461 config = &shader->config;
462 } else {
463 unsigned lds_blocks;
464
465 config = &inline_config;
466 code_object_to_config(code_object, config);
467
468 lds_blocks = config->lds_size;
469 /* XXX: We are over allocating LDS. For GFX6, the shader reports
470 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
471 * allocated in the shader and 4 bytes allocated by the state
472 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
473 */
474 if (sctx->chip_class <= GFX6) {
475 lds_blocks += align(program->local_size, 256) >> 8;
476 } else {
477 lds_blocks += align(program->local_size, 512) >> 9;
478 }
479
480 /* TODO: use si_multiwave_lds_size_workaround */
481 assert(lds_blocks <= 0xFF);
482
483 config->rsrc2 &= C_00B84C_LDS_SIZE;
484 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
485 }
486
487 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
488 return false;
489
490 if (shader->scratch_bo) {
491 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
492 "Total Scratch: %u bytes\n", sctx->scratch_waves,
493 config->scratch_bytes_per_wave,
494 config->scratch_bytes_per_wave *
495 sctx->scratch_waves);
496
497 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
498 shader->scratch_bo, RADEON_USAGE_READWRITE,
499 RADEON_PRIO_SCRATCH_BUFFER);
500 }
501
502 /* Prefetch the compute shader to TC L2.
503 *
504 * We should also prefetch graphics shaders if a compute dispatch was
505 * the last command, and the compute shader if a draw call was the last
506 * command. However, that would add more complexity and we're likely
507 * to get a shader state change in that case anyway.
508 */
509 if (sctx->chip_class >= GFX7) {
510 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
511 0, program->shader.bo->b.b.width0);
512 }
513
514 shader_va = shader->bo->gpu_address + offset;
515 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
516 /* Shader code is placed after the amd_kernel_code_t
517 * struct. */
518 shader_va += sizeof(amd_kernel_code_t);
519 }
520
521 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
522 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
523
524 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
525 radeon_emit(cs, shader_va >> 8);
526 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
527
528 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
529 radeon_emit(cs, config->rsrc1);
530 radeon_emit(cs, config->rsrc2);
531
532 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
533 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
534
535 sctx->max_seen_compute_scratch_bytes_per_wave =
536 MAX2(sctx->max_seen_compute_scratch_bytes_per_wave,
537 config->scratch_bytes_per_wave);
538
539 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
540 S_00B860_WAVES(sctx->scratch_waves)
541 | S_00B860_WAVESIZE(sctx->max_seen_compute_scratch_bytes_per_wave >> 10));
542
543 sctx->cs_shader_state.emitted_program = program;
544 sctx->cs_shader_state.offset = offset;
545 sctx->cs_shader_state.uses_scratch =
546 config->scratch_bytes_per_wave != 0;
547
548 return true;
549 }
550
551 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
552 const amd_kernel_code_t *code_object,
553 unsigned user_sgpr)
554 {
555 struct radeon_cmdbuf *cs = sctx->gfx_cs;
556 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
557
558 unsigned max_private_element_size = AMD_HSA_BITS_GET(
559 code_object->code_properties,
560 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
561
562 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
563 uint32_t scratch_dword1 =
564 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
565 S_008F04_SWIZZLE_ENABLE(1);
566
567 /* Disable address clamping */
568 uint32_t scratch_dword2 = 0xffffffff;
569 uint32_t scratch_dword3 =
570 S_008F0C_INDEX_STRIDE(3) |
571 S_008F0C_ADD_TID_ENABLE(1);
572
573 if (sctx->chip_class >= GFX9) {
574 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
575 } else {
576 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
577
578 if (sctx->chip_class < GFX8) {
579 /* BUF_DATA_FORMAT is ignored, but it cannot be
580 * BUF_DATA_FORMAT_INVALID. */
581 scratch_dword3 |=
582 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
583 }
584 }
585
586 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
587 (user_sgpr * 4), 4);
588 radeon_emit(cs, scratch_dword0);
589 radeon_emit(cs, scratch_dword1);
590 radeon_emit(cs, scratch_dword2);
591 radeon_emit(cs, scratch_dword3);
592 }
593
594 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
595 const amd_kernel_code_t *code_object,
596 const struct pipe_grid_info *info,
597 uint64_t kernel_args_va)
598 {
599 struct si_compute *program = sctx->cs_shader_state.program;
600 struct radeon_cmdbuf *cs = sctx->gfx_cs;
601
602 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
603 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
604 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
605 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
606 };
607
608 unsigned i, user_sgpr = 0;
609 if (AMD_HSA_BITS_GET(code_object->code_properties,
610 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
611 if (code_object->workitem_private_segment_byte_size > 0) {
612 setup_scratch_rsrc_user_sgprs(sctx, code_object,
613 user_sgpr);
614 }
615 user_sgpr += 4;
616 }
617
618 if (AMD_HSA_BITS_GET(code_object->code_properties,
619 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
620 struct dispatch_packet dispatch;
621 unsigned dispatch_offset;
622 struct si_resource *dispatch_buf = NULL;
623 uint64_t dispatch_va;
624
625 /* Upload dispatch ptr */
626 memset(&dispatch, 0, sizeof(dispatch));
627
628 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
629 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
630 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
631
632 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
633 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
634 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
635
636 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
637 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
638
639 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
640
641 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
642 256, &dispatch, &dispatch_offset,
643 (struct pipe_resource**)&dispatch_buf);
644
645 if (!dispatch_buf) {
646 fprintf(stderr, "Error: Failed to allocate dispatch "
647 "packet.");
648 }
649 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
650 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
651
652 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
653
654 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
655 (user_sgpr * 4), 2);
656 radeon_emit(cs, dispatch_va);
657 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
658 S_008F04_STRIDE(0));
659
660 si_resource_reference(&dispatch_buf, NULL);
661 user_sgpr += 2;
662 }
663
664 if (AMD_HSA_BITS_GET(code_object->code_properties,
665 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
666 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
667 (user_sgpr * 4), 2);
668 radeon_emit(cs, kernel_args_va);
669 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
670 S_008F04_STRIDE(0));
671 user_sgpr += 2;
672 }
673
674 for (i = 0; i < 3 && user_sgpr < 16; i++) {
675 if (code_object->code_properties & workgroup_count_masks[i]) {
676 radeon_set_sh_reg_seq(cs,
677 R_00B900_COMPUTE_USER_DATA_0 +
678 (user_sgpr * 4), 1);
679 radeon_emit(cs, info->grid[i]);
680 user_sgpr += 1;
681 }
682 }
683 }
684
685 static bool si_upload_compute_input(struct si_context *sctx,
686 const amd_kernel_code_t *code_object,
687 const struct pipe_grid_info *info)
688 {
689 struct si_compute *program = sctx->cs_shader_state.program;
690 struct si_resource *input_buffer = NULL;
691 uint32_t kernel_args_offset = 0;
692 uint32_t *kernel_args;
693 void *kernel_args_ptr;
694 uint64_t kernel_args_va;
695
696 u_upload_alloc(sctx->b.const_uploader, 0, program->input_size,
697 sctx->screen->info.tcc_cache_line_size,
698 &kernel_args_offset,
699 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
700
701 if (unlikely(!kernel_args_ptr))
702 return false;
703
704 kernel_args = (uint32_t*)kernel_args_ptr;
705 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
706
707 memcpy(kernel_args, info->input, program->input_size);
708
709 for (unsigned i = 0; i < program->input_size / 4; i++) {
710 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
711 kernel_args[i]);
712 }
713
714 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
715 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
716
717 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
718 si_resource_reference(&input_buffer, NULL);
719 return true;
720 }
721
722 static void si_setup_tgsi_user_data(struct si_context *sctx,
723 const struct pipe_grid_info *info)
724 {
725 struct si_compute *program = sctx->cs_shader_state.program;
726 struct si_shader_selector *sel = &program->sel;
727 struct radeon_cmdbuf *cs = sctx->gfx_cs;
728 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
729 4 * SI_NUM_RESOURCE_SGPRS;
730 unsigned block_size_reg = grid_size_reg +
731 /* 12 bytes = 3 dwords. */
732 12 * sel->info.uses_grid_size;
733 unsigned cs_user_data_reg = block_size_reg +
734 12 * program->reads_variable_block_size;
735
736 if (info->indirect) {
737 if (sel->info.uses_grid_size) {
738 for (unsigned i = 0; i < 3; ++i) {
739 si_cp_copy_data(sctx, sctx->gfx_cs,
740 COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
741 COPY_DATA_SRC_MEM, si_resource(info->indirect),
742 info->indirect_offset + 4 * i);
743 }
744 }
745 } else {
746 if (sel->info.uses_grid_size) {
747 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
748 radeon_emit(cs, info->grid[0]);
749 radeon_emit(cs, info->grid[1]);
750 radeon_emit(cs, info->grid[2]);
751 }
752 if (program->reads_variable_block_size) {
753 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
754 radeon_emit(cs, info->block[0]);
755 radeon_emit(cs, info->block[1]);
756 radeon_emit(cs, info->block[2]);
757 }
758 }
759
760 if (program->num_cs_user_data_dwords) {
761 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
762 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
763 }
764 }
765
766 static void si_emit_dispatch_packets(struct si_context *sctx,
767 const struct pipe_grid_info *info)
768 {
769 struct si_screen *sscreen = sctx->screen;
770 struct radeon_cmdbuf *cs = sctx->gfx_cs;
771 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
772 unsigned threads_per_threadgroup =
773 info->block[0] * info->block[1] * info->block[2];
774 unsigned waves_per_threadgroup =
775 DIV_ROUND_UP(threads_per_threadgroup, sscreen->compute_wave_size);
776 unsigned threadgroups_per_cu = 1;
777
778 if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1)
779 threadgroups_per_cu = 2;
780
781 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
782 ac_get_compute_resource_limits(&sscreen->info,
783 waves_per_threadgroup,
784 sctx->cs_max_waves_per_sh,
785 threadgroups_per_cu));
786
787 unsigned dispatch_initiator =
788 S_00B800_COMPUTE_SHADER_EN(1) |
789 S_00B800_FORCE_START_AT_000(1) |
790 /* If the KMD allows it (there is a KMD hw register for it),
791 * allow launching waves out-of-order. (same as Vulkan) */
792 S_00B800_ORDER_MODE(sctx->chip_class >= GFX7) |
793 S_00B800_CS_W32_EN(sscreen->compute_wave_size == 32);
794
795 const uint *last_block = info->last_block;
796 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
797
798 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
799
800 if (partial_block_en) {
801 unsigned partial[3];
802
803 /* If no partial_block, these should be an entire block size, not 0. */
804 partial[0] = last_block[0] ? last_block[0] : info->block[0];
805 partial[1] = last_block[1] ? last_block[1] : info->block[1];
806 partial[2] = last_block[2] ? last_block[2] : info->block[2];
807
808 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
809 S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
810 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
811 S_00B820_NUM_THREAD_PARTIAL(partial[1]));
812 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
813 S_00B824_NUM_THREAD_PARTIAL(partial[2]));
814
815 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
816 } else {
817 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
818 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
819 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
820 }
821
822 if (info->indirect) {
823 uint64_t base_va = si_resource(info->indirect)->gpu_address;
824
825 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
826 si_resource(info->indirect),
827 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
828
829 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
830 PKT3_SHADER_TYPE_S(1));
831 radeon_emit(cs, 1);
832 radeon_emit(cs, base_va);
833 radeon_emit(cs, base_va >> 32);
834
835 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
836 PKT3_SHADER_TYPE_S(1));
837 radeon_emit(cs, info->indirect_offset);
838 radeon_emit(cs, dispatch_initiator);
839 } else {
840 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
841 PKT3_SHADER_TYPE_S(1));
842 radeon_emit(cs, info->grid[0]);
843 radeon_emit(cs, info->grid[1]);
844 radeon_emit(cs, info->grid[2]);
845 radeon_emit(cs, dispatch_initiator);
846 }
847 }
848
849
850 static void si_launch_grid(
851 struct pipe_context *ctx, const struct pipe_grid_info *info)
852 {
853 struct si_context *sctx = (struct si_context*)ctx;
854 struct si_compute *program = sctx->cs_shader_state.program;
855 const amd_kernel_code_t *code_object =
856 si_compute_get_code_object(program, info->pc);
857 int i;
858 /* HW bug workaround when CS threadgroups > 256 threads and async
859 * compute isn't used, i.e. only one compute job can run at a time.
860 * If async compute is possible, the threadgroup size must be limited
861 * to 256 threads on all queues to avoid the bug.
862 * Only GFX6 and certain GFX7 chips are affected.
863 */
864 bool cs_regalloc_hang =
865 (sctx->chip_class == GFX6 ||
866 sctx->family == CHIP_BONAIRE ||
867 sctx->family == CHIP_KABINI) &&
868 info->block[0] * info->block[1] * info->block[2] > 256;
869
870 if (cs_regalloc_hang)
871 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
872 SI_CONTEXT_CS_PARTIAL_FLUSH;
873
874 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
875 program->shader.compilation_failed)
876 return;
877
878 if (sctx->has_graphics) {
879 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
880 si_update_fb_dirtiness_after_rendering(sctx);
881 sctx->last_num_draw_calls = sctx->num_draw_calls;
882 }
883
884 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
885 }
886
887 /* Add buffer sizes for memory checking in need_cs_space. */
888 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
889 /* TODO: add the scratch buffer */
890
891 if (info->indirect) {
892 si_context_add_resource_size(sctx, info->indirect);
893
894 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
895 if (sctx->chip_class <= GFX8 &&
896 si_resource(info->indirect)->TC_L2_dirty) {
897 sctx->flags |= SI_CONTEXT_WB_L2;
898 si_resource(info->indirect)->TC_L2_dirty = false;
899 }
900 }
901
902 si_need_gfx_cs_space(sctx);
903
904 if (sctx->bo_list_add_all_compute_resources)
905 si_compute_resources_add_all_to_bo_list(sctx);
906
907 if (!sctx->cs_shader_state.initialized) {
908 si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
909
910 sctx->cs_shader_state.emitted_program = NULL;
911 sctx->cs_shader_state.initialized = true;
912 }
913
914 if (sctx->flags)
915 sctx->emit_cache_flush(sctx);
916
917 if (!si_switch_compute_shader(sctx, program, &program->shader,
918 code_object, info->pc))
919 return;
920
921 si_upload_compute_shader_descriptors(sctx);
922 si_emit_compute_shader_pointers(sctx);
923
924 if (sctx->has_graphics &&
925 si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
926 sctx->atoms.s.render_cond.emit(sctx);
927 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
928 }
929
930 if (program->ir_type == PIPE_SHADER_IR_NATIVE &&
931 unlikely(!si_upload_compute_input(sctx, code_object, info)))
932 return;
933
934 /* Global buffers */
935 for (i = 0; i < program->max_global_buffers; i++) {
936 struct si_resource *buffer =
937 si_resource(program->global_buffers[i]);
938 if (!buffer) {
939 continue;
940 }
941 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
942 RADEON_USAGE_READWRITE,
943 RADEON_PRIO_COMPUTE_GLOBAL);
944 }
945
946 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
947 si_setup_tgsi_user_data(sctx, info);
948
949 si_emit_dispatch_packets(sctx, info);
950
951 if (unlikely(sctx->current_saved_cs)) {
952 si_trace_emit(sctx);
953 si_log_compute_state(sctx, sctx->log);
954 }
955
956 sctx->compute_is_busy = true;
957 sctx->num_compute_calls++;
958 if (sctx->cs_shader_state.uses_scratch)
959 sctx->num_spill_compute_calls++;
960
961 if (cs_regalloc_hang)
962 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
963 }
964
965 void si_destroy_compute(struct si_compute *program)
966 {
967 struct si_shader_selector *sel = &program->sel;
968
969 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
970 util_queue_drop_job(&sel->screen->shader_compiler_queue,
971 &sel->ready);
972 util_queue_fence_destroy(&sel->ready);
973 }
974
975 for (unsigned i = 0; i < program->max_global_buffers; i++)
976 pipe_resource_reference(&program->global_buffers[i], NULL);
977 FREE(program->global_buffers);
978
979 si_shader_destroy(&program->shader);
980 FREE(program->sel.tokens);
981 ralloc_free(program->sel.nir);
982 FREE(program);
983 }
984
985 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
986 struct si_compute *program = (struct si_compute *)state;
987 struct si_context *sctx = (struct si_context*)ctx;
988
989 if (!state)
990 return;
991
992 if (program == sctx->cs_shader_state.program)
993 sctx->cs_shader_state.program = NULL;
994
995 if (program == sctx->cs_shader_state.emitted_program)
996 sctx->cs_shader_state.emitted_program = NULL;
997
998 si_compute_reference(&program, NULL);
999 }
1000
1001 static void si_set_compute_resources(struct pipe_context * ctx_,
1002 unsigned start, unsigned count,
1003 struct pipe_surface ** surfaces) { }
1004
1005 void si_init_compute_functions(struct si_context *sctx)
1006 {
1007 sctx->b.create_compute_state = si_create_compute_state;
1008 sctx->b.delete_compute_state = si_delete_compute_state;
1009 sctx->b.bind_compute_state = si_bind_compute_state;
1010 sctx->b.set_compute_resources = si_set_compute_resources;
1011 sctx->b.set_global_binding = si_set_global_binding;
1012 sctx->b.launch_grid = si_launch_grid;
1013 }