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radeonsi: support ARB_compute_variable_group_size
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
28 #include "radeon/radeon_elf_util.h"
29
30 #include "amd_kernel_code_t.h"
31 #include "radeon/r600_cs.h"
32 #include "si_pipe.h"
33 #include "sid.h"
34
35 #define MAX_GLOBAL_BUFFERS 20
36
37 struct si_compute {
38 unsigned ir_type;
39 unsigned local_size;
40 unsigned private_size;
41 unsigned input_size;
42 struct si_shader shader;
43
44 struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
45 bool use_code_object_v2;
46 };
47
48 struct dispatch_packet {
49 uint16_t header;
50 uint16_t setup;
51 uint16_t workgroup_size_x;
52 uint16_t workgroup_size_y;
53 uint16_t workgroup_size_z;
54 uint16_t reserved0;
55 uint32_t grid_size_x;
56 uint32_t grid_size_y;
57 uint32_t grid_size_z;
58 uint32_t private_segment_size;
59 uint32_t group_segment_size;
60 uint64_t kernel_object;
61 uint64_t kernarg_address;
62 uint64_t reserved2;
63 };
64
65 static const amd_kernel_code_t *si_compute_get_code_object(
66 const struct si_compute *program,
67 uint64_t symbol_offset)
68 {
69 if (!program->use_code_object_v2) {
70 return NULL;
71 }
72 return (const amd_kernel_code_t*)
73 (program->shader.binary.code + symbol_offset);
74 }
75
76 static void code_object_to_config(const amd_kernel_code_t *code_object,
77 struct si_shader_config *out_config) {
78
79 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
80 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
81 out_config->num_sgprs = code_object->wavefront_sgpr_count;
82 out_config->num_vgprs = code_object->workitem_vgpr_count;
83 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
84 out_config->rsrc1 = rsrc1;
85 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
86 out_config->rsrc2 = rsrc2;
87 out_config->scratch_bytes_per_wave =
88 align(code_object->workitem_private_segment_byte_size * 64, 1024);
89 }
90
91 static void *si_create_compute_state(
92 struct pipe_context *ctx,
93 const struct pipe_compute_state *cso)
94 {
95 struct si_context *sctx = (struct si_context *)ctx;
96 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
97 struct si_compute *program = CALLOC_STRUCT(si_compute);
98 struct si_shader *shader = &program->shader;
99
100
101 program->ir_type = cso->ir_type;
102 program->local_size = cso->req_local_mem;
103 program->private_size = cso->req_private_mem;
104 program->input_size = cso->req_input_mem;
105 program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
106 cso->ir_type == PIPE_SHADER_IR_NATIVE;
107
108
109 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
110 struct si_shader_selector sel;
111 bool scratch_enabled;
112
113 memset(&sel, 0, sizeof(sel));
114
115 sel.tokens = tgsi_dup_tokens(cso->prog);
116 if (!sel.tokens) {
117 FREE(program);
118 return NULL;
119 }
120
121 tgsi_scan_shader(cso->prog, &sel.info);
122 sel.type = PIPE_SHADER_COMPUTE;
123 sel.local_size = cso->req_local_mem;
124
125 p_atomic_inc(&sscreen->b.num_shaders_created);
126
127 program->shader.selector = &sel;
128
129 if (si_shader_create(sscreen, sctx->tm, &program->shader,
130 &sctx->b.debug)) {
131 FREE(sel.tokens);
132 FREE(program);
133 return NULL;
134 }
135
136 scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
137
138 shader->config.rsrc1 =
139 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
140 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
141 S_00B848_DX10_CLAMP(1) |
142 S_00B848_FLOAT_MODE(shader->config.float_mode);
143
144 shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
145 S_00B84C_SCRATCH_EN(scratch_enabled) |
146 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
147 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
148 S_00B84C_LDS_SIZE(shader->config.lds_size);
149
150 FREE(sel.tokens);
151 } else {
152 const struct pipe_llvm_program_header *header;
153 const char *code;
154 header = cso->prog;
155 code = cso->prog + sizeof(struct pipe_llvm_program_header);
156
157 radeon_elf_read(code, header->num_bytes, &program->shader.binary);
158 if (program->use_code_object_v2) {
159 const amd_kernel_code_t *code_object =
160 si_compute_get_code_object(program, 0);
161 code_object_to_config(code_object, &program->shader.config);
162 } else {
163 si_shader_binary_read_config(&program->shader.binary,
164 &program->shader.config, 0);
165 }
166 si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
167 PIPE_SHADER_COMPUTE, stderr);
168 si_shader_binary_upload(sctx->screen, &program->shader);
169 }
170
171 return program;
172 }
173
174 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
175 {
176 struct si_context *sctx = (struct si_context*)ctx;
177 sctx->cs_shader_state.program = (struct si_compute*)state;
178 }
179
180 static void si_set_global_binding(
181 struct pipe_context *ctx, unsigned first, unsigned n,
182 struct pipe_resource **resources,
183 uint32_t **handles)
184 {
185 unsigned i;
186 struct si_context *sctx = (struct si_context*)ctx;
187 struct si_compute *program = sctx->cs_shader_state.program;
188
189 if (!resources) {
190 for (i = first; i < first + n; i++) {
191 pipe_resource_reference(&program->global_buffers[i], NULL);
192 }
193 return;
194 }
195
196 for (i = first; i < first + n; i++) {
197 uint64_t va;
198 uint32_t offset;
199 pipe_resource_reference(&program->global_buffers[i], resources[i]);
200 va = r600_resource(resources[i])->gpu_address;
201 offset = util_le32_to_cpu(*handles[i]);
202 va += offset;
203 va = util_cpu_to_le64(va);
204 memcpy(handles[i], &va, sizeof(va));
205 }
206 }
207
208 static void si_initialize_compute(struct si_context *sctx)
209 {
210 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
211 uint64_t bc_va;
212
213 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
214 radeon_emit(cs, 0);
215 radeon_emit(cs, 0);
216 radeon_emit(cs, 0);
217
218 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
219 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
220 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
221 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
222
223 if (sctx->b.chip_class >= CIK) {
224 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
225 radeon_set_sh_reg_seq(cs,
226 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
227 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
228 S_00B864_SH1_CU_EN(0xffff));
229 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
230 S_00B868_SH1_CU_EN(0xffff));
231 }
232
233 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
234 * and is now per pipe, so it should be handled in the
235 * kernel if we want to use something other than the default value,
236 * which is now 0x22f.
237 */
238 if (sctx->b.chip_class <= SI) {
239 /* XXX: This should be:
240 * (number of compute units) * 4 * (waves per simd) - 1 */
241
242 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
243 0x190 /* Default value */);
244 }
245
246 /* Set the pointer to border colors. */
247 bc_va = sctx->border_color_buffer->gpu_address;
248
249 if (sctx->b.chip_class >= CIK) {
250 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
251 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
252 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
253 } else {
254 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
255 }
256
257 sctx->cs_shader_state.emitted_program = NULL;
258 sctx->cs_shader_state.initialized = true;
259 }
260
261 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
262 struct si_shader *shader,
263 struct si_shader_config *config)
264 {
265 uint64_t scratch_bo_size, scratch_needed;
266 scratch_bo_size = 0;
267 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
268 if (sctx->compute_scratch_buffer)
269 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
270
271 if (scratch_bo_size < scratch_needed) {
272 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
273
274 sctx->compute_scratch_buffer =
275 si_resource_create_custom(&sctx->screen->b.b,
276 PIPE_USAGE_DEFAULT, scratch_needed);
277
278 if (!sctx->compute_scratch_buffer)
279 return false;
280 }
281
282 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
283 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
284
285 si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
286
287 if (si_shader_binary_upload(sctx->screen, shader))
288 return false;
289
290 r600_resource_reference(&shader->scratch_bo,
291 sctx->compute_scratch_buffer);
292 }
293
294 return true;
295 }
296
297 static bool si_switch_compute_shader(struct si_context *sctx,
298 struct si_compute *program,
299 struct si_shader *shader,
300 const amd_kernel_code_t *code_object,
301 unsigned offset)
302 {
303 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
304 struct si_shader_config inline_config = {0};
305 struct si_shader_config *config;
306 uint64_t shader_va;
307
308 if (sctx->cs_shader_state.emitted_program == program &&
309 sctx->cs_shader_state.offset == offset)
310 return true;
311
312 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
313 config = &shader->config;
314 } else {
315 unsigned lds_blocks;
316
317 config = &inline_config;
318 if (code_object) {
319 code_object_to_config(code_object, config);
320 } else {
321 si_shader_binary_read_config(&shader->binary, config, offset);
322 }
323
324 lds_blocks = config->lds_size;
325 /* XXX: We are over allocating LDS. For SI, the shader reports
326 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
327 * allocated in the shader and 4 bytes allocated by the state
328 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
329 */
330 if (sctx->b.chip_class <= SI) {
331 lds_blocks += align(program->local_size, 256) >> 8;
332 } else {
333 lds_blocks += align(program->local_size, 512) >> 9;
334 }
335
336 assert(lds_blocks <= 0xFF);
337
338 config->rsrc2 &= C_00B84C_LDS_SIZE;
339 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
340 }
341
342 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
343 return false;
344
345 if (shader->scratch_bo) {
346 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
347 "Total Scratch: %u bytes\n", sctx->scratch_waves,
348 config->scratch_bytes_per_wave,
349 config->scratch_bytes_per_wave *
350 sctx->scratch_waves);
351
352 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
353 shader->scratch_bo, RADEON_USAGE_READWRITE,
354 RADEON_PRIO_SCRATCH_BUFFER);
355 }
356
357 shader_va = shader->bo->gpu_address + offset;
358 if (program->use_code_object_v2) {
359 /* Shader code is placed after the amd_kernel_code_t
360 * struct. */
361 shader_va += sizeof(amd_kernel_code_t);
362 }
363
364 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
365 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
366
367 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
368 radeon_emit(cs, shader_va >> 8);
369 radeon_emit(cs, shader_va >> 40);
370
371 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
372 radeon_emit(cs, config->rsrc1);
373 radeon_emit(cs, config->rsrc2);
374
375 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
376 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
377
378 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
379 S_00B860_WAVES(sctx->scratch_waves)
380 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
381
382 sctx->cs_shader_state.emitted_program = program;
383 sctx->cs_shader_state.offset = offset;
384 sctx->cs_shader_state.uses_scratch =
385 config->scratch_bytes_per_wave != 0;
386
387 return true;
388 }
389
390 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
391 const amd_kernel_code_t *code_object,
392 unsigned user_sgpr)
393 {
394 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
395 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
396
397 unsigned max_private_element_size = AMD_HSA_BITS_GET(
398 code_object->code_properties,
399 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
400
401 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
402 uint32_t scratch_dword1 =
403 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
404 S_008F04_SWIZZLE_ENABLE(1);
405
406 /* Disable address clamping */
407 uint32_t scratch_dword2 = 0xffffffff;
408 uint32_t scratch_dword3 =
409 S_008F0C_ELEMENT_SIZE(max_private_element_size) |
410 S_008F0C_INDEX_STRIDE(3) |
411 S_008F0C_ADD_TID_ENABLE(1);
412
413
414 if (sctx->screen->b.chip_class < VI) {
415 /* BUF_DATA_FORMAT is ignored, but it cannot be
416 BUF_DATA_FORMAT_INVALID. */
417 scratch_dword3 |=
418 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
419 }
420
421 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
422 (user_sgpr * 4), 4);
423 radeon_emit(cs, scratch_dword0);
424 radeon_emit(cs, scratch_dword1);
425 radeon_emit(cs, scratch_dword2);
426 radeon_emit(cs, scratch_dword3);
427 }
428
429 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
430 const amd_kernel_code_t *code_object,
431 const struct pipe_grid_info *info,
432 uint64_t kernel_args_va)
433 {
434 struct si_compute *program = sctx->cs_shader_state.program;
435 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
436
437 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
438 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
439 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
440 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
441 };
442
443 unsigned i, user_sgpr = 0;
444 if (AMD_HSA_BITS_GET(code_object->code_properties,
445 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
446 if (code_object->workitem_private_segment_byte_size > 0) {
447 setup_scratch_rsrc_user_sgprs(sctx, code_object,
448 user_sgpr);
449 }
450 user_sgpr += 4;
451 }
452
453 if (AMD_HSA_BITS_GET(code_object->code_properties,
454 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
455 struct dispatch_packet dispatch;
456 unsigned dispatch_offset;
457 struct r600_resource *dispatch_buf = NULL;
458 uint64_t dispatch_va;
459
460 /* Upload dispatch ptr */
461 memset(&dispatch, 0, sizeof(dispatch));
462
463 dispatch.workgroup_size_x = info->block[0];
464 dispatch.workgroup_size_y = info->block[1];
465 dispatch.workgroup_size_z = info->block[2];
466
467 dispatch.grid_size_x = info->grid[0] * info->block[0];
468 dispatch.grid_size_y = info->grid[1] * info->block[1];
469 dispatch.grid_size_z = info->grid[2] * info->block[2];
470
471 dispatch.private_segment_size = program->private_size;
472 dispatch.group_segment_size = program->local_size;
473
474 dispatch.kernarg_address = kernel_args_va;
475
476 u_upload_data(sctx->b.uploader, 0, sizeof(dispatch), 256,
477 &dispatch, &dispatch_offset,
478 (struct pipe_resource**)&dispatch_buf);
479
480 if (!dispatch_buf) {
481 fprintf(stderr, "Error: Failed to allocate dispatch "
482 "packet.");
483 }
484 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
485 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
486
487 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
488
489 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
490 (user_sgpr * 4), 2);
491 radeon_emit(cs, dispatch_va);
492 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
493 S_008F04_STRIDE(0));
494
495 r600_resource_reference(&dispatch_buf, NULL);
496 user_sgpr += 2;
497 }
498
499 if (AMD_HSA_BITS_GET(code_object->code_properties,
500 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
501 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
502 (user_sgpr * 4), 2);
503 radeon_emit(cs, kernel_args_va);
504 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
505 S_008F04_STRIDE(0));
506 user_sgpr += 2;
507 }
508
509 for (i = 0; i < 3 && user_sgpr < 16; i++) {
510 if (code_object->code_properties & workgroup_count_masks[i]) {
511 radeon_set_sh_reg_seq(cs,
512 R_00B900_COMPUTE_USER_DATA_0 +
513 (user_sgpr * 4), 1);
514 radeon_emit(cs, info->grid[i]);
515 user_sgpr += 1;
516 }
517 }
518 }
519
520 static void si_upload_compute_input(struct si_context *sctx,
521 const amd_kernel_code_t *code_object,
522 const struct pipe_grid_info *info)
523 {
524 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
525 struct si_compute *program = sctx->cs_shader_state.program;
526 struct r600_resource *input_buffer = NULL;
527 unsigned kernel_args_size;
528 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
529 uint32_t kernel_args_offset = 0;
530 uint32_t *kernel_args;
531 void *kernel_args_ptr;
532 uint64_t kernel_args_va;
533 unsigned i;
534
535 /* The extra num_work_size_bytes are for work group / work item size information */
536 kernel_args_size = program->input_size + num_work_size_bytes;
537
538 u_upload_alloc(sctx->b.uploader, 0, kernel_args_size, 256,
539 &kernel_args_offset,
540 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
541
542 kernel_args = (uint32_t*)kernel_args_ptr;
543 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
544
545 if (!code_object) {
546 for (i = 0; i < 3; i++) {
547 kernel_args[i] = info->grid[i];
548 kernel_args[i + 3] = info->grid[i] * info->block[i];
549 kernel_args[i + 6] = info->block[i];
550 }
551 }
552
553 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
554 program->input_size);
555
556
557 for (i = 0; i < (kernel_args_size / 4); i++) {
558 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
559 kernel_args[i]);
560 }
561
562
563 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
564 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
565
566 if (code_object) {
567 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
568 } else {
569 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
570 radeon_emit(cs, kernel_args_va);
571 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
572 S_008F04_STRIDE(0));
573 }
574
575 r600_resource_reference(&input_buffer, NULL);
576 }
577
578 static void si_setup_tgsi_grid(struct si_context *sctx,
579 const struct pipe_grid_info *info)
580 {
581 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
582 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
583 4 * SI_SGPR_GRID_SIZE;
584
585 if (info->indirect) {
586 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
587 uint64_t va = base_va + info->indirect_offset;
588 int i;
589
590 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
591 (struct r600_resource *)info->indirect,
592 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
593
594 for (i = 0; i < 3; ++i) {
595 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
596 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
597 COPY_DATA_DST_SEL(COPY_DATA_REG));
598 radeon_emit(cs, (va + 4 * i));
599 radeon_emit(cs, (va + 4 * i) >> 32);
600 radeon_emit(cs, (grid_size_reg >> 2) + i);
601 radeon_emit(cs, 0);
602 }
603 } else {
604 struct si_compute *program = sctx->cs_shader_state.program;
605 bool variable_group_size =
606 program->shader.selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
607
608 radeon_set_sh_reg_seq(cs, grid_size_reg, variable_group_size ? 6 : 3);
609 radeon_emit(cs, info->grid[0]);
610 radeon_emit(cs, info->grid[1]);
611 radeon_emit(cs, info->grid[2]);
612 if (variable_group_size) {
613 radeon_emit(cs, info->block[0]);
614 radeon_emit(cs, info->block[1]);
615 radeon_emit(cs, info->block[2]);
616 }
617 }
618 }
619
620 static void si_emit_dispatch_packets(struct si_context *sctx,
621 const struct pipe_grid_info *info)
622 {
623 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
624 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
625 unsigned waves_per_threadgroup =
626 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
627
628 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
629 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
630
631 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
632 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
633 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
634 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
635
636 if (info->indirect) {
637 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
638
639 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
640 (struct r600_resource *)info->indirect,
641 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
642
643 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
644 PKT3_SHADER_TYPE_S(1));
645 radeon_emit(cs, 1);
646 radeon_emit(cs, base_va);
647 radeon_emit(cs, base_va >> 32);
648
649 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
650 PKT3_SHADER_TYPE_S(1));
651 radeon_emit(cs, info->indirect_offset);
652 radeon_emit(cs, 1);
653 } else {
654 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
655 PKT3_SHADER_TYPE_S(1));
656 radeon_emit(cs, info->grid[0]);
657 radeon_emit(cs, info->grid[1]);
658 radeon_emit(cs, info->grid[2]);
659 radeon_emit(cs, 1);
660 }
661 }
662
663
664 static void si_launch_grid(
665 struct pipe_context *ctx, const struct pipe_grid_info *info)
666 {
667 struct si_context *sctx = (struct si_context*)ctx;
668 struct si_compute *program = sctx->cs_shader_state.program;
669 const amd_kernel_code_t *code_object =
670 si_compute_get_code_object(program, info->pc);
671 int i;
672 /* HW bug workaround when CS threadgroups > 256 threads and async
673 * compute isn't used, i.e. only one compute job can run at a time.
674 * If async compute is possible, the threadgroup size must be limited
675 * to 256 threads on all queues to avoid the bug.
676 * Only SI and certain CIK chips are affected.
677 */
678 bool cs_regalloc_hang =
679 (sctx->b.chip_class == SI ||
680 sctx->b.family == CHIP_BONAIRE ||
681 sctx->b.family == CHIP_KABINI) &&
682 info->block[0] * info->block[1] * info->block[2] > 256;
683
684 if (cs_regalloc_hang)
685 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
686 SI_CONTEXT_CS_PARTIAL_FLUSH;
687
688 si_decompress_compute_textures(sctx);
689
690 /* Add buffer sizes for memory checking in need_cs_space. */
691 r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
692 /* TODO: add the scratch buffer */
693
694 if (info->indirect) {
695 r600_context_add_resource_size(ctx, info->indirect);
696
697 /* The hw doesn't read the indirect buffer via TC L2. */
698 if (r600_resource(info->indirect)->TC_L2_dirty) {
699 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
700 r600_resource(info->indirect)->TC_L2_dirty = false;
701 }
702 }
703
704 si_need_cs_space(sctx);
705
706 if (!sctx->cs_shader_state.initialized)
707 si_initialize_compute(sctx);
708
709 if (sctx->b.flags)
710 si_emit_cache_flush(sctx);
711
712 if (!si_switch_compute_shader(sctx, program, &program->shader,
713 code_object, info->pc))
714 return;
715
716 si_upload_compute_shader_descriptors(sctx);
717 si_emit_compute_shader_userdata(sctx);
718
719 if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
720 sctx->atoms.s.render_cond->emit(&sctx->b,
721 sctx->atoms.s.render_cond);
722 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
723 }
724
725 if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
726 si_upload_compute_input(sctx, code_object, info);
727
728 /* Global buffers */
729 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
730 struct r600_resource *buffer =
731 (struct r600_resource*)program->global_buffers[i];
732 if (!buffer) {
733 continue;
734 }
735 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
736 RADEON_USAGE_READWRITE,
737 RADEON_PRIO_COMPUTE_GLOBAL);
738 }
739
740 if (program->ir_type == PIPE_SHADER_IR_TGSI)
741 si_setup_tgsi_grid(sctx, info);
742
743 si_ce_pre_draw_synchronization(sctx);
744
745 si_emit_dispatch_packets(sctx, info);
746
747 si_ce_post_draw_synchronization(sctx);
748
749 sctx->compute_is_busy = true;
750 sctx->b.num_compute_calls++;
751 if (sctx->cs_shader_state.uses_scratch)
752 sctx->b.num_spill_compute_calls++;
753
754 if (cs_regalloc_hang)
755 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
756 }
757
758
759 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
760 struct si_compute *program = (struct si_compute *)state;
761 struct si_context *sctx = (struct si_context*)ctx;
762
763 if (!state) {
764 return;
765 }
766
767 if (program == sctx->cs_shader_state.program)
768 sctx->cs_shader_state.program = NULL;
769
770 if (program == sctx->cs_shader_state.emitted_program)
771 sctx->cs_shader_state.emitted_program = NULL;
772
773 si_shader_destroy(&program->shader);
774 FREE(program);
775 }
776
777 static void si_set_compute_resources(struct pipe_context * ctx_,
778 unsigned start, unsigned count,
779 struct pipe_surface ** surfaces) { }
780
781 void si_init_compute_functions(struct si_context *sctx)
782 {
783 sctx->b.b.create_compute_state = si_create_compute_state;
784 sctx->b.b.delete_compute_state = si_delete_compute_state;
785 sctx->b.b.bind_compute_state = si_bind_compute_state;
786 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
787 sctx->b.b.set_compute_resources = si_set_compute_resources;
788 sctx->b.b.set_global_binding = si_set_global_binding;
789 sctx->b.b.launch_grid = si_launch_grid;
790 }