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radeonsi: don't load unused compute shader input SGPRs and VGPRs
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
28
29 #include "amd_kernel_code_t.h"
30 #include "radeon/r600_cs.h"
31 #include "si_pipe.h"
32 #include "sid.h"
33
34 #define MAX_GLOBAL_BUFFERS 22
35
36 struct si_compute {
37 struct si_screen *screen;
38 struct tgsi_token *tokens;
39 struct util_queue_fence ready;
40 struct si_compiler_ctx_state compiler_ctx_state;
41
42 unsigned ir_type;
43 unsigned local_size;
44 unsigned private_size;
45 unsigned input_size;
46 struct si_shader shader;
47
48 struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
49 unsigned use_code_object_v2 : 1;
50 unsigned variable_group_size : 1;
51 unsigned uses_grid_size:1;
52 unsigned uses_block_size:1;
53 };
54
55 struct dispatch_packet {
56 uint16_t header;
57 uint16_t setup;
58 uint16_t workgroup_size_x;
59 uint16_t workgroup_size_y;
60 uint16_t workgroup_size_z;
61 uint16_t reserved0;
62 uint32_t grid_size_x;
63 uint32_t grid_size_y;
64 uint32_t grid_size_z;
65 uint32_t private_segment_size;
66 uint32_t group_segment_size;
67 uint64_t kernel_object;
68 uint64_t kernarg_address;
69 uint64_t reserved2;
70 };
71
72 static const amd_kernel_code_t *si_compute_get_code_object(
73 const struct si_compute *program,
74 uint64_t symbol_offset)
75 {
76 if (!program->use_code_object_v2) {
77 return NULL;
78 }
79 return (const amd_kernel_code_t*)
80 (program->shader.binary.code + symbol_offset);
81 }
82
83 static void code_object_to_config(const amd_kernel_code_t *code_object,
84 struct si_shader_config *out_config) {
85
86 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
87 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
88 out_config->num_sgprs = code_object->wavefront_sgpr_count;
89 out_config->num_vgprs = code_object->workitem_vgpr_count;
90 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
91 out_config->rsrc1 = rsrc1;
92 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
93 out_config->rsrc2 = rsrc2;
94 out_config->scratch_bytes_per_wave =
95 align(code_object->workitem_private_segment_byte_size * 64, 1024);
96 }
97
98 /* Asynchronous compute shader compilation. */
99 static void si_create_compute_state_async(void *job, int thread_index)
100 {
101 struct si_compute *program = (struct si_compute *)job;
102 struct si_shader *shader = &program->shader;
103 struct si_shader_selector sel;
104 LLVMTargetMachineRef tm;
105 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
106
107 if (thread_index >= 0) {
108 assert(thread_index < ARRAY_SIZE(program->screen->tm));
109 tm = program->screen->tm[thread_index];
110 if (!debug->async)
111 debug = NULL;
112 } else {
113 tm = program->compiler_ctx_state.tm;
114 }
115
116 memset(&sel, 0, sizeof(sel));
117
118 sel.screen = program->screen;
119 tgsi_scan_shader(program->tokens, &sel.info);
120 sel.tokens = program->tokens;
121 sel.type = PIPE_SHADER_COMPUTE;
122 sel.local_size = program->local_size;
123
124 program->shader.selector = &sel;
125 program->shader.is_monolithic = true;
126 program->uses_grid_size = sel.info.uses_grid_size;
127 program->uses_block_size = sel.info.uses_block_size;
128
129 if (si_shader_create(program->screen, tm, &program->shader, debug)) {
130 program->shader.compilation_failed = true;
131 } else {
132 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
133 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
134 (sel.info.uses_grid_size ? 3 : 0) +
135 (sel.info.uses_block_size ? 3 : 0);
136
137 shader->config.rsrc1 =
138 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
139 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
140 S_00B848_DX10_CLAMP(1) |
141 S_00B848_FLOAT_MODE(shader->config.float_mode);
142
143 shader->config.rsrc2 =
144 S_00B84C_USER_SGPR(user_sgprs) |
145 S_00B84C_SCRATCH_EN(scratch_enabled) |
146 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
147 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
148 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
149 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
150 sel.info.uses_thread_id[1] ? 1 : 0) |
151 S_00B84C_LDS_SIZE(shader->config.lds_size);
152
153 program->variable_group_size =
154 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
155 }
156
157 FREE(program->tokens);
158 program->shader.selector = NULL;
159 }
160
161 static void *si_create_compute_state(
162 struct pipe_context *ctx,
163 const struct pipe_compute_state *cso)
164 {
165 struct si_context *sctx = (struct si_context *)ctx;
166 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
167 struct si_compute *program = CALLOC_STRUCT(si_compute);
168
169 program->screen = (struct si_screen *)ctx->screen;
170 program->ir_type = cso->ir_type;
171 program->local_size = cso->req_local_mem;
172 program->private_size = cso->req_private_mem;
173 program->input_size = cso->req_input_mem;
174 program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
175 cso->ir_type == PIPE_SHADER_IR_NATIVE;
176
177 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
178 program->tokens = tgsi_dup_tokens(cso->prog);
179 if (!program->tokens) {
180 FREE(program);
181 return NULL;
182 }
183
184 program->compiler_ctx_state.tm = sctx->tm;
185 program->compiler_ctx_state.debug = sctx->b.debug;
186 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
187 p_atomic_inc(&sscreen->b.num_shaders_created);
188 util_queue_fence_init(&program->ready);
189
190 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
191 sctx->is_debug ||
192 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_COMPUTE))
193 si_create_compute_state_async(program, -1);
194 else
195 util_queue_add_job(&sscreen->shader_compiler_queue,
196 program, &program->ready,
197 si_create_compute_state_async, NULL);
198 } else {
199 const struct pipe_llvm_program_header *header;
200 const char *code;
201 header = cso->prog;
202 code = cso->prog + sizeof(struct pipe_llvm_program_header);
203
204 ac_elf_read(code, header->num_bytes, &program->shader.binary);
205 if (program->use_code_object_v2) {
206 const amd_kernel_code_t *code_object =
207 si_compute_get_code_object(program, 0);
208 code_object_to_config(code_object, &program->shader.config);
209 } else {
210 si_shader_binary_read_config(&program->shader.binary,
211 &program->shader.config, 0);
212 }
213 si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
214 PIPE_SHADER_COMPUTE, stderr, true);
215 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
216 fprintf(stderr, "LLVM failed to upload shader\n");
217 FREE(program);
218 return NULL;
219 }
220 }
221
222 return program;
223 }
224
225 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
226 {
227 struct si_context *sctx = (struct si_context*)ctx;
228 sctx->cs_shader_state.program = (struct si_compute*)state;
229 }
230
231 static void si_set_global_binding(
232 struct pipe_context *ctx, unsigned first, unsigned n,
233 struct pipe_resource **resources,
234 uint32_t **handles)
235 {
236 unsigned i;
237 struct si_context *sctx = (struct si_context*)ctx;
238 struct si_compute *program = sctx->cs_shader_state.program;
239
240 assert(first + n <= MAX_GLOBAL_BUFFERS);
241
242 if (!resources) {
243 for (i = 0; i < n; i++) {
244 pipe_resource_reference(&program->global_buffers[first + i], NULL);
245 }
246 return;
247 }
248
249 for (i = 0; i < n; i++) {
250 uint64_t va;
251 uint32_t offset;
252 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
253 va = r600_resource(resources[i])->gpu_address;
254 offset = util_le32_to_cpu(*handles[i]);
255 va += offset;
256 va = util_cpu_to_le64(va);
257 memcpy(handles[i], &va, sizeof(va));
258 }
259 }
260
261 static void si_initialize_compute(struct si_context *sctx)
262 {
263 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
264 uint64_t bc_va;
265
266 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
267 radeon_emit(cs, 0);
268 radeon_emit(cs, 0);
269 radeon_emit(cs, 0);
270
271 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
272 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
273 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
274 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
275
276 if (sctx->b.chip_class >= CIK) {
277 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
278 radeon_set_sh_reg_seq(cs,
279 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
280 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
281 S_00B864_SH1_CU_EN(0xffff));
282 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
283 S_00B868_SH1_CU_EN(0xffff));
284 }
285
286 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
287 * and is now per pipe, so it should be handled in the
288 * kernel if we want to use something other than the default value,
289 * which is now 0x22f.
290 */
291 if (sctx->b.chip_class <= SI) {
292 /* XXX: This should be:
293 * (number of compute units) * 4 * (waves per simd) - 1 */
294
295 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
296 0x190 /* Default value */);
297 }
298
299 /* Set the pointer to border colors. */
300 bc_va = sctx->border_color_buffer->gpu_address;
301
302 if (sctx->b.chip_class >= CIK) {
303 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
304 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
305 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
306 } else {
307 if (sctx->screen->b.info.drm_major == 3 ||
308 (sctx->screen->b.info.drm_major == 2 &&
309 sctx->screen->b.info.drm_minor >= 48)) {
310 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
311 bc_va >> 8);
312 }
313 }
314
315 sctx->cs_shader_state.emitted_program = NULL;
316 sctx->cs_shader_state.initialized = true;
317 }
318
319 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
320 struct si_shader *shader,
321 struct si_shader_config *config)
322 {
323 uint64_t scratch_bo_size, scratch_needed;
324 scratch_bo_size = 0;
325 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
326 if (sctx->compute_scratch_buffer)
327 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
328
329 if (scratch_bo_size < scratch_needed) {
330 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
331
332 sctx->compute_scratch_buffer = (struct r600_resource*)
333 r600_aligned_buffer_create(&sctx->screen->b.b,
334 R600_RESOURCE_FLAG_UNMAPPABLE,
335 PIPE_USAGE_DEFAULT,
336 scratch_needed, 256);
337
338 if (!sctx->compute_scratch_buffer)
339 return false;
340 }
341
342 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
343 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
344
345 si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
346
347 if (si_shader_binary_upload(sctx->screen, shader))
348 return false;
349
350 r600_resource_reference(&shader->scratch_bo,
351 sctx->compute_scratch_buffer);
352 }
353
354 return true;
355 }
356
357 static bool si_switch_compute_shader(struct si_context *sctx,
358 struct si_compute *program,
359 struct si_shader *shader,
360 const amd_kernel_code_t *code_object,
361 unsigned offset)
362 {
363 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
364 struct si_shader_config inline_config = {0};
365 struct si_shader_config *config;
366 uint64_t shader_va;
367
368 if (sctx->cs_shader_state.emitted_program == program &&
369 sctx->cs_shader_state.offset == offset)
370 return true;
371
372 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
373 config = &shader->config;
374 } else {
375 unsigned lds_blocks;
376
377 config = &inline_config;
378 if (code_object) {
379 code_object_to_config(code_object, config);
380 } else {
381 si_shader_binary_read_config(&shader->binary, config, offset);
382 }
383
384 lds_blocks = config->lds_size;
385 /* XXX: We are over allocating LDS. For SI, the shader reports
386 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
387 * allocated in the shader and 4 bytes allocated by the state
388 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
389 */
390 if (sctx->b.chip_class <= SI) {
391 lds_blocks += align(program->local_size, 256) >> 8;
392 } else {
393 lds_blocks += align(program->local_size, 512) >> 9;
394 }
395
396 /* TODO: use si_multiwave_lds_size_workaround */
397 assert(lds_blocks <= 0xFF);
398
399 config->rsrc2 &= C_00B84C_LDS_SIZE;
400 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
401 }
402
403 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
404 return false;
405
406 if (shader->scratch_bo) {
407 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
408 "Total Scratch: %u bytes\n", sctx->scratch_waves,
409 config->scratch_bytes_per_wave,
410 config->scratch_bytes_per_wave *
411 sctx->scratch_waves);
412
413 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
414 shader->scratch_bo, RADEON_USAGE_READWRITE,
415 RADEON_PRIO_SCRATCH_BUFFER);
416 }
417
418 /* Prefetch the compute shader to TC L2.
419 *
420 * We should also prefetch graphics shaders if a compute dispatch was
421 * the last command, and the compute shader if a draw call was the last
422 * command. However, that would add more complexity and we're likely
423 * to get a shader state change in that case anyway.
424 */
425 if (sctx->b.chip_class >= CIK) {
426 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
427 0, program->shader.bo->b.b.width0);
428 }
429
430 shader_va = shader->bo->gpu_address + offset;
431 if (program->use_code_object_v2) {
432 /* Shader code is placed after the amd_kernel_code_t
433 * struct. */
434 shader_va += sizeof(amd_kernel_code_t);
435 }
436
437 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
438 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
439
440 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
441 radeon_emit(cs, shader_va >> 8);
442 radeon_emit(cs, shader_va >> 40);
443
444 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
445 radeon_emit(cs, config->rsrc1);
446 radeon_emit(cs, config->rsrc2);
447
448 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
449 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
450
451 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
452 S_00B860_WAVES(sctx->scratch_waves)
453 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
454
455 sctx->cs_shader_state.emitted_program = program;
456 sctx->cs_shader_state.offset = offset;
457 sctx->cs_shader_state.uses_scratch =
458 config->scratch_bytes_per_wave != 0;
459
460 return true;
461 }
462
463 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
464 const amd_kernel_code_t *code_object,
465 unsigned user_sgpr)
466 {
467 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
468 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
469
470 unsigned max_private_element_size = AMD_HSA_BITS_GET(
471 code_object->code_properties,
472 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
473
474 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
475 uint32_t scratch_dword1 =
476 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
477 S_008F04_SWIZZLE_ENABLE(1);
478
479 /* Disable address clamping */
480 uint32_t scratch_dword2 = 0xffffffff;
481 uint32_t scratch_dword3 =
482 S_008F0C_INDEX_STRIDE(3) |
483 S_008F0C_ADD_TID_ENABLE(1);
484
485 if (sctx->b.chip_class >= GFX9) {
486 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
487 } else {
488 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
489
490 if (sctx->b.chip_class < VI) {
491 /* BUF_DATA_FORMAT is ignored, but it cannot be
492 * BUF_DATA_FORMAT_INVALID. */
493 scratch_dword3 |=
494 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
495 }
496 }
497
498 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
499 (user_sgpr * 4), 4);
500 radeon_emit(cs, scratch_dword0);
501 radeon_emit(cs, scratch_dword1);
502 radeon_emit(cs, scratch_dword2);
503 radeon_emit(cs, scratch_dword3);
504 }
505
506 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
507 const amd_kernel_code_t *code_object,
508 const struct pipe_grid_info *info,
509 uint64_t kernel_args_va)
510 {
511 struct si_compute *program = sctx->cs_shader_state.program;
512 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
513
514 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
515 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
516 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
517 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
518 };
519
520 unsigned i, user_sgpr = 0;
521 if (AMD_HSA_BITS_GET(code_object->code_properties,
522 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
523 if (code_object->workitem_private_segment_byte_size > 0) {
524 setup_scratch_rsrc_user_sgprs(sctx, code_object,
525 user_sgpr);
526 }
527 user_sgpr += 4;
528 }
529
530 if (AMD_HSA_BITS_GET(code_object->code_properties,
531 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
532 struct dispatch_packet dispatch;
533 unsigned dispatch_offset;
534 struct r600_resource *dispatch_buf = NULL;
535 uint64_t dispatch_va;
536
537 /* Upload dispatch ptr */
538 memset(&dispatch, 0, sizeof(dispatch));
539
540 dispatch.workgroup_size_x = info->block[0];
541 dispatch.workgroup_size_y = info->block[1];
542 dispatch.workgroup_size_z = info->block[2];
543
544 dispatch.grid_size_x = info->grid[0] * info->block[0];
545 dispatch.grid_size_y = info->grid[1] * info->block[1];
546 dispatch.grid_size_z = info->grid[2] * info->block[2];
547
548 dispatch.private_segment_size = program->private_size;
549 dispatch.group_segment_size = program->local_size;
550
551 dispatch.kernarg_address = kernel_args_va;
552
553 u_upload_data(sctx->b.b.const_uploader, 0, sizeof(dispatch),
554 256, &dispatch, &dispatch_offset,
555 (struct pipe_resource**)&dispatch_buf);
556
557 if (!dispatch_buf) {
558 fprintf(stderr, "Error: Failed to allocate dispatch "
559 "packet.");
560 }
561 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
562 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
563
564 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
565
566 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
567 (user_sgpr * 4), 2);
568 radeon_emit(cs, dispatch_va);
569 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
570 S_008F04_STRIDE(0));
571
572 r600_resource_reference(&dispatch_buf, NULL);
573 user_sgpr += 2;
574 }
575
576 if (AMD_HSA_BITS_GET(code_object->code_properties,
577 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
578 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
579 (user_sgpr * 4), 2);
580 radeon_emit(cs, kernel_args_va);
581 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
582 S_008F04_STRIDE(0));
583 user_sgpr += 2;
584 }
585
586 for (i = 0; i < 3 && user_sgpr < 16; i++) {
587 if (code_object->code_properties & workgroup_count_masks[i]) {
588 radeon_set_sh_reg_seq(cs,
589 R_00B900_COMPUTE_USER_DATA_0 +
590 (user_sgpr * 4), 1);
591 radeon_emit(cs, info->grid[i]);
592 user_sgpr += 1;
593 }
594 }
595 }
596
597 static bool si_upload_compute_input(struct si_context *sctx,
598 const amd_kernel_code_t *code_object,
599 const struct pipe_grid_info *info)
600 {
601 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
602 struct si_compute *program = sctx->cs_shader_state.program;
603 struct r600_resource *input_buffer = NULL;
604 unsigned kernel_args_size;
605 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
606 uint32_t kernel_args_offset = 0;
607 uint32_t *kernel_args;
608 void *kernel_args_ptr;
609 uint64_t kernel_args_va;
610 unsigned i;
611
612 /* The extra num_work_size_bytes are for work group / work item size information */
613 kernel_args_size = program->input_size + num_work_size_bytes;
614
615 u_upload_alloc(sctx->b.b.const_uploader, 0, kernel_args_size,
616 sctx->screen->b.info.tcc_cache_line_size,
617 &kernel_args_offset,
618 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
619
620 if (unlikely(!kernel_args_ptr))
621 return false;
622
623 kernel_args = (uint32_t*)kernel_args_ptr;
624 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
625
626 if (!code_object) {
627 for (i = 0; i < 3; i++) {
628 kernel_args[i] = info->grid[i];
629 kernel_args[i + 3] = info->grid[i] * info->block[i];
630 kernel_args[i + 6] = info->block[i];
631 }
632 }
633
634 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
635 program->input_size);
636
637
638 for (i = 0; i < (kernel_args_size / 4); i++) {
639 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
640 kernel_args[i]);
641 }
642
643
644 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
645 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
646
647 if (code_object) {
648 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
649 } else {
650 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
651 radeon_emit(cs, kernel_args_va);
652 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
653 S_008F04_STRIDE(0));
654 }
655
656 r600_resource_reference(&input_buffer, NULL);
657
658 return true;
659 }
660
661 static void si_setup_tgsi_grid(struct si_context *sctx,
662 const struct pipe_grid_info *info)
663 {
664 struct si_compute *program = sctx->cs_shader_state.program;
665 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
666 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
667 4 * SI_NUM_RESOURCE_SGPRS;
668 unsigned block_size_reg = grid_size_reg +
669 /* 12 bytes = 3 dwords. */
670 12 * program->uses_grid_size;
671
672 if (info->indirect) {
673 if (program->uses_grid_size) {
674 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
675 uint64_t va = base_va + info->indirect_offset;
676 int i;
677
678 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
679 (struct r600_resource *)info->indirect,
680 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
681
682 for (i = 0; i < 3; ++i) {
683 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
684 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
685 COPY_DATA_DST_SEL(COPY_DATA_REG));
686 radeon_emit(cs, (va + 4 * i));
687 radeon_emit(cs, (va + 4 * i) >> 32);
688 radeon_emit(cs, (grid_size_reg >> 2) + i);
689 radeon_emit(cs, 0);
690 }
691 }
692 } else {
693 if (program->uses_grid_size) {
694 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
695 radeon_emit(cs, info->grid[0]);
696 radeon_emit(cs, info->grid[1]);
697 radeon_emit(cs, info->grid[2]);
698 }
699 if (program->variable_group_size && program->uses_block_size) {
700 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
701 radeon_emit(cs, info->block[0]);
702 radeon_emit(cs, info->block[1]);
703 radeon_emit(cs, info->block[2]);
704 }
705 }
706 }
707
708 static void si_emit_dispatch_packets(struct si_context *sctx,
709 const struct pipe_grid_info *info)
710 {
711 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
712 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
713 unsigned waves_per_threadgroup =
714 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
715
716 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
717 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
718
719 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
720 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
721 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
722 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
723
724 if (info->indirect) {
725 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
726
727 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
728 (struct r600_resource *)info->indirect,
729 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
730
731 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
732 PKT3_SHADER_TYPE_S(1));
733 radeon_emit(cs, 1);
734 radeon_emit(cs, base_va);
735 radeon_emit(cs, base_va >> 32);
736
737 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
738 PKT3_SHADER_TYPE_S(1));
739 radeon_emit(cs, info->indirect_offset);
740 radeon_emit(cs, 1);
741 } else {
742 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
743 PKT3_SHADER_TYPE_S(1));
744 radeon_emit(cs, info->grid[0]);
745 radeon_emit(cs, info->grid[1]);
746 radeon_emit(cs, info->grid[2]);
747 radeon_emit(cs, 1);
748 }
749 }
750
751
752 static void si_launch_grid(
753 struct pipe_context *ctx, const struct pipe_grid_info *info)
754 {
755 struct si_context *sctx = (struct si_context*)ctx;
756 struct si_compute *program = sctx->cs_shader_state.program;
757 const amd_kernel_code_t *code_object =
758 si_compute_get_code_object(program, info->pc);
759 int i;
760 /* HW bug workaround when CS threadgroups > 256 threads and async
761 * compute isn't used, i.e. only one compute job can run at a time.
762 * If async compute is possible, the threadgroup size must be limited
763 * to 256 threads on all queues to avoid the bug.
764 * Only SI and certain CIK chips are affected.
765 */
766 bool cs_regalloc_hang =
767 (sctx->b.chip_class == SI ||
768 sctx->b.family == CHIP_BONAIRE ||
769 sctx->b.family == CHIP_KABINI) &&
770 info->block[0] * info->block[1] * info->block[2] > 256;
771
772 if (cs_regalloc_hang)
773 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
774 SI_CONTEXT_CS_PARTIAL_FLUSH;
775
776 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
777 util_queue_fence_wait(&program->ready);
778
779 if (program->shader.compilation_failed)
780 return;
781 }
782
783 si_decompress_compute_textures(sctx);
784
785 /* Add buffer sizes for memory checking in need_cs_space. */
786 r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
787 /* TODO: add the scratch buffer */
788
789 if (info->indirect) {
790 r600_context_add_resource_size(ctx, info->indirect);
791
792 /* The hw doesn't read the indirect buffer via TC L2. */
793 if (r600_resource(info->indirect)->TC_L2_dirty) {
794 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
795 r600_resource(info->indirect)->TC_L2_dirty = false;
796 }
797 }
798
799 si_need_cs_space(sctx);
800
801 if (!sctx->cs_shader_state.initialized)
802 si_initialize_compute(sctx);
803
804 if (sctx->b.flags)
805 si_emit_cache_flush(sctx);
806
807 if (!si_switch_compute_shader(sctx, program, &program->shader,
808 code_object, info->pc))
809 return;
810
811 si_upload_compute_shader_descriptors(sctx);
812 si_emit_compute_shader_userdata(sctx);
813
814 if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
815 sctx->atoms.s.render_cond->emit(&sctx->b,
816 sctx->atoms.s.render_cond);
817 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
818 }
819
820 if ((program->input_size ||
821 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
822 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
823 return;
824 }
825
826 /* Global buffers */
827 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
828 struct r600_resource *buffer =
829 (struct r600_resource*)program->global_buffers[i];
830 if (!buffer) {
831 continue;
832 }
833 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
834 RADEON_USAGE_READWRITE,
835 RADEON_PRIO_COMPUTE_GLOBAL);
836 }
837
838 if (program->ir_type == PIPE_SHADER_IR_TGSI)
839 si_setup_tgsi_grid(sctx, info);
840
841 si_ce_pre_draw_synchronization(sctx);
842
843 si_emit_dispatch_packets(sctx, info);
844
845 si_ce_post_draw_synchronization(sctx);
846
847 sctx->compute_is_busy = true;
848 sctx->b.num_compute_calls++;
849 if (sctx->cs_shader_state.uses_scratch)
850 sctx->b.num_spill_compute_calls++;
851
852 if (cs_regalloc_hang)
853 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
854 }
855
856
857 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
858 struct si_compute *program = (struct si_compute *)state;
859 struct si_context *sctx = (struct si_context*)ctx;
860
861 if (!state) {
862 return;
863 }
864
865 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
866 util_queue_fence_wait(&program->ready);
867 util_queue_fence_destroy(&program->ready);
868 }
869
870 if (program == sctx->cs_shader_state.program)
871 sctx->cs_shader_state.program = NULL;
872
873 if (program == sctx->cs_shader_state.emitted_program)
874 sctx->cs_shader_state.emitted_program = NULL;
875
876 si_shader_destroy(&program->shader);
877 FREE(program);
878 }
879
880 static void si_set_compute_resources(struct pipe_context * ctx_,
881 unsigned start, unsigned count,
882 struct pipe_surface ** surfaces) { }
883
884 void si_init_compute_functions(struct si_context *sctx)
885 {
886 sctx->b.b.create_compute_state = si_create_compute_state;
887 sctx->b.b.delete_compute_state = si_delete_compute_state;
888 sctx->b.b.bind_compute_state = si_bind_compute_state;
889 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
890 sctx->b.b.set_compute_resources = si_set_compute_resources;
891 sctx->b.b.set_global_binding = si_set_global_binding;
892 sctx->b.b.launch_grid = si_launch_grid;
893 }