src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "tgsi/tgsi_parse.h"
  26 #include "util/u_memory.h"
  27 #include "util/u_upload_mgr.h"
  28 #include "radeon/r600_pipe_common.h"
  29 #include "radeon/radeon_elf_util.h"
  30 #include "radeon/radeon_llvm_util.h"
  31
  32 #include "radeon/r600_cs.h"
  33 #include "si_pipe.h"
  34 #include "si_shader.h"
  35 #include "sid.h"
  36
  37 #define MAX_GLOBAL_BUFFERS 20
  38
  39 struct si_compute {
  40         unsigned ir_type;
  41         unsigned local_size;
  42         unsigned private_size;
  43         unsigned input_size;
  44         struct si_shader shader;
  45
  46         struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
  47 };
  48
  49 static void *si_create_compute_state(
  50         struct pipe_context *ctx,
  51         const struct pipe_compute_state *cso)
  52 {
  53         struct si_context *sctx = (struct si_context *)ctx;
  54         struct si_screen *sscreen = (struct si_screen *)ctx->screen;
  55         struct si_compute *program = CALLOC_STRUCT(si_compute);
  56         struct si_shader *shader = &program->shader;
  57
  58
  59         program->ir_type = cso->ir_type;
  60         program->local_size = cso->req_local_mem;
  61         program->private_size = cso->req_private_mem;
  62         program->input_size = cso->req_input_mem;
  63
  64
  65         if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
  66                 struct si_shader_selector sel;
  67                 bool scratch_enabled;
  68
  69                 memset(&sel, 0, sizeof(sel));
  70
  71                 sel.tokens = tgsi_dup_tokens(cso->prog);
  72                 if (!sel.tokens) {
  73                         return NULL;
  74                 }
  75
  76                 tgsi_scan_shader(cso->prog, &sel.info);
  77                 sel.type = PIPE_SHADER_COMPUTE;
  78                 sel.local_size = cso->req_local_mem;
  79
  80                 p_atomic_inc(&sscreen->b.num_shaders_created);
  81
  82                 program->shader.selector = &sel;
  83
  84                 if (si_compile_tgsi_shader(sscreen, sctx->tm, &program->shader,
  85                                            true, &sctx->b.debug)) {
  86                         FREE(sel.tokens);
  87                         return NULL;
  88                 }
  89
  90                 scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
  91
  92                 shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
  93                            S_00B84C_SCRATCH_EN(scratch_enabled) |
  94                            S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
  95                            S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
  96                            S_00B84C_LDS_SIZE(shader->config.lds_size);
  97
  98                 FREE(sel.tokens);
  99         } else {
 100                 const struct pipe_llvm_program_header *header;
 101                 const char *code;
 102                 header = cso->prog;
 103                 code = cso->prog + sizeof(struct pipe_llvm_program_header);
 104
 105                 radeon_elf_read(code, header->num_bytes, &program->shader.binary);
 106                 si_shader_binary_read_config(&program->shader.binary,
 107                              &program->shader.config, 0);
 108         }
 109         si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
 110                        TGSI_PROCESSOR_COMPUTE, stderr);
 111         si_shader_binary_upload(sctx->screen, &program->shader);
 112
 113         return program;
 114 }
 115
 116 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 117 {
 118         struct si_context *sctx = (struct si_context*)ctx;
 119         sctx->cs_shader_state.program = (struct si_compute*)state;
 120 }
 121
 122 static void si_set_global_binding(
 123         struct pipe_context *ctx, unsigned first, unsigned n,
 124         struct pipe_resource **resources,
 125         uint32_t **handles)
 126 {
 127         unsigned i;
 128         struct si_context *sctx = (struct si_context*)ctx;
 129         struct si_compute *program = sctx->cs_shader_state.program;
 130
 131         if (!resources) {
 132                 for (i = first; i < first + n; i++) {
 133                         pipe_resource_reference(&program->global_buffers[i], NULL);
 134                 }
 135                 return;
 136         }
 137
 138         for (i = first; i < first + n; i++) {
 139                 uint64_t va;
 140                 uint32_t offset;
 141                 pipe_resource_reference(&program->global_buffers[i], resources[i]);
 142                 va = r600_resource(resources[i])->gpu_address;
 143                 offset = util_le32_to_cpu(*handles[i]);
 144                 va += offset;
 145                 va = util_cpu_to_le64(va);
 146                 memcpy(handles[i], &va, sizeof(va));
 147         }
 148 }
 149
 150 static void si_initialize_compute(struct si_context *sctx)
 151 {
 152         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 153
 154         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
 155         radeon_emit(cs, 0);
 156         radeon_emit(cs, 0);
 157         radeon_emit(cs, 0);
 158
 159         radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, 3);
 160         radeon_emit(cs, 0);
 161         /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
 162         radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 163         radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
 164
 165         if (sctx->b.chip_class >= CIK) {
 166                 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
 167                 radeon_set_sh_reg_seq(cs,
 168                                      R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
 169                 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
 170                                 S_00B864_SH1_CU_EN(0xffff));
 171                 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
 172                                 S_00B868_SH1_CU_EN(0xffff));
 173         }
 174
 175         /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 176          * and is now per pipe, so it should be handled in the
 177          * kernel if we want to use something other than the default value,
 178          * which is now 0x22f.
 179          */
 180         if (sctx->b.chip_class <= SI) {
 181                 /* XXX: This should be:
 182                  * (number of compute units) * 4 * (waves per simd) - 1 */
 183
 184                 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
 185                                   0x190 /* Default value */);
 186         }
 187
 188         sctx->cs_shader_state.emitted_program = NULL;
 189         sctx->cs_shader_state.initialized = true;
 190 }
 191
 192 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
 193                                             struct si_shader *shader,
 194                                             struct si_shader_config *config)
 195 {
 196         uint64_t scratch_bo_size, scratch_needed;
 197         scratch_bo_size = 0;
 198         scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
 199         if (sctx->compute_scratch_buffer)
 200                 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
 201
 202         if (scratch_bo_size < scratch_needed) {
 203                 pipe_resource_reference(
 204                         (struct pipe_resource**)&sctx->compute_scratch_buffer,
 205                         NULL);
 206
 207                 sctx->compute_scratch_buffer =
 208                                 si_resource_create_custom(&sctx->screen->b.b,
 209                                 PIPE_USAGE_DEFAULT, scratch_needed);
 210
 211                 if (!sctx->compute_scratch_buffer)
 212                         return false;
 213         }
 214
 215         if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
 216                 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 217
 218                 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
 219
 220                 if (si_shader_binary_upload(sctx->screen, shader))
 221                         return false;
 222
 223                 r600_resource_reference(&shader->scratch_bo,
 224                                         sctx->compute_scratch_buffer);
 225         }
 226
 227         return true;
 228 }
 229
 230 static bool si_switch_compute_shader(struct si_context *sctx,
 231                                      struct si_compute *program,
 232                                      struct si_shader *shader, unsigned offset)
 233 {
 234         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 235         struct si_shader_config inline_config = {0};
 236         struct si_shader_config *config;
 237         uint64_t shader_va;
 238
 239         if (sctx->cs_shader_state.emitted_program == program &&
 240             sctx->cs_shader_state.offset == offset)
 241                 return true;
 242
 243         if (program->ir_type == PIPE_SHADER_IR_TGSI) {
 244                 config = &shader->config;
 245         } else {
 246                 unsigned lds_blocks;
 247
 248                 config = &inline_config;
 249                 si_shader_binary_read_config(&shader->binary, config, offset);
 250
 251                 lds_blocks = config->lds_size;
 252                 /* XXX: We are over allocating LDS.  For SI, the shader reports
 253                 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
 254                 * allocated in the shader and 4 bytes allocated by the state
 255                 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
 256                 */
 257                 if (sctx->b.chip_class <= SI) {
 258                         lds_blocks += align(program->local_size, 256) >> 8;
 259                 } else {
 260                         lds_blocks += align(program->local_size, 512) >> 9;
 261                 }
 262
 263                 assert(lds_blocks <= 0xFF);
 264
 265                 config->rsrc2 &= C_00B84C_LDS_SIZE;
 266                 config->rsrc2 |=  S_00B84C_LDS_SIZE(lds_blocks);
 267         }
 268
 269         if (!si_setup_compute_scratch_buffer(sctx, shader, config))
 270                 return false;
 271
 272         if (shader->scratch_bo) {
 273                 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
 274                             "Total Scratch: %u bytes\n", sctx->scratch_waves,
 275                             config->scratch_bytes_per_wave,
 276                             config->scratch_bytes_per_wave *
 277                             sctx->scratch_waves);
 278
 279                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 280                               shader->scratch_bo, RADEON_USAGE_READWRITE,
 281                               RADEON_PRIO_SCRATCH_BUFFER);
 282         }
 283
 284         shader_va = shader->bo->gpu_address + offset;
 285
 286         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 287                                   RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
 288
 289         radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
 290         radeon_emit(cs, shader_va >> 8);
 291         radeon_emit(cs, shader_va >> 40);
 292
 293         radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
 294         radeon_emit(cs, config->rsrc1);
 295         radeon_emit(cs, config->rsrc2);
 296
 297         radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
 298                   S_00B860_WAVES(sctx->scratch_waves)
 299                      | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
 300
 301         sctx->cs_shader_state.emitted_program = program;
 302         sctx->cs_shader_state.offset = offset;
 303
 304         return true;
 305 }
 306
 307 static void si_upload_compute_input(struct si_context *sctx,
 308                                   const struct pipe_grid_info *info)
 309 {
 310         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 311         struct si_compute *program = sctx->cs_shader_state.program;
 312         struct r600_resource *input_buffer = NULL;
 313         unsigned kernel_args_size;
 314         unsigned num_work_size_bytes = 36;
 315         uint32_t kernel_args_offset = 0;
 316         uint32_t *kernel_args;
 317         void *kernel_args_ptr;
 318         uint64_t kernel_args_va;
 319         unsigned i;
 320
 321         /* The extra num_work_size_bytes are for work group / work item size information */
 322         kernel_args_size = program->input_size + num_work_size_bytes;
 323
 324         u_upload_alloc(sctx->b.uploader, 0, kernel_args_size, 256,
 325                        &kernel_args_offset,
 326                        (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
 327
 328         kernel_args = (uint32_t*)kernel_args_ptr;
 329         for (i = 0; i < 3; i++) {
 330                 kernel_args[i] = info->grid[i];
 331                 kernel_args[i + 3] = info->grid[i] * info->block[i];
 332                 kernel_args[i + 6] = info->block[i];
 333         }
 334
 335         memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
 336                program->input_size);
 337
 338
 339         for (i = 0; i < (kernel_args_size / 4); i++) {
 340                 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
 341                         kernel_args[i]);
 342         }
 343
 344         kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
 345
 346         radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
 347                                   RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
 348
 349         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
 350         radeon_emit(cs, kernel_args_va);
 351         radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
 352                         S_008F04_STRIDE(0));
 353
 354         pipe_resource_reference((struct pipe_resource**)&input_buffer, NULL);
 355 }
 356
 357 static void si_setup_tgsi_grid(struct si_context *sctx,
 358                                 const struct pipe_grid_info *info)
 359 {
 360         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 361         unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
 362                                   4 * SI_SGPR_GRID_SIZE;
 363
 364         if (info->indirect) {
 365                 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
 366                 uint64_t va = base_va + info->indirect_offset;
 367                 int i;
 368
 369                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 370                                  (struct r600_resource *)info->indirect,
 371                                  RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
 372
 373                 for (i = 0; i < 3; ++i) {
 374                         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 375                         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
 376                                         COPY_DATA_DST_SEL(COPY_DATA_REG));
 377                         radeon_emit(cs, (va +  4 * i));
 378                         radeon_emit(cs, (va + 4 * i) >> 32);
 379                         radeon_emit(cs, (grid_size_reg >> 2) + i);
 380                         radeon_emit(cs, 0);
 381                 }
 382         } else {
 383
 384                 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
 385                 radeon_emit(cs, info->grid[0]);
 386                 radeon_emit(cs, info->grid[1]);
 387                 radeon_emit(cs, info->grid[2]);
 388         }
 389 }
 390
 391 static void si_emit_dispatch_packets(struct si_context *sctx,
 392                                      const struct pipe_grid_info *info)
 393 {
 394         struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 395         bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
 396
 397         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
 398         radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
 399         radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
 400         radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
 401
 402         if (info->indirect) {
 403                 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
 404
 405                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 406                                  (struct r600_resource *)info->indirect,
 407                                  RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
 408
 409                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
 410                                 PKT3_SHADER_TYPE_S(1));
 411                 radeon_emit(cs, 1);
 412                 radeon_emit(cs, base_va);
 413                 radeon_emit(cs, base_va >> 32);
 414
 415                 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
 416                                 PKT3_SHADER_TYPE_S(1));
 417                 radeon_emit(cs, info->indirect_offset);
 418                 radeon_emit(cs, 1);
 419         } else {
 420                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
 421                                 PKT3_SHADER_TYPE_S(1));
 422                 radeon_emit(cs, info->grid[0]);
 423                 radeon_emit(cs, info->grid[1]);
 424                 radeon_emit(cs, info->grid[2]);
 425                 radeon_emit(cs, 1);
 426         }
 427 }
 428
 429
 430 static void si_launch_grid(
 431                 struct pipe_context *ctx, const struct pipe_grid_info *info)
 432 {
 433         struct si_context *sctx = (struct si_context*)ctx;
 434         struct si_compute *program = sctx->cs_shader_state.program;
 435         int i;
 436
 437         si_decompress_compute_textures(sctx);
 438
 439         si_need_cs_space(sctx);
 440
 441         if (!sctx->cs_shader_state.initialized)
 442                 si_initialize_compute(sctx);
 443
 444         if (sctx->b.flags)
 445                 si_emit_cache_flush(sctx, NULL);
 446
 447         if (!si_switch_compute_shader(sctx, program, &program->shader, info->pc))
 448                 return;
 449
 450         si_upload_compute_shader_descriptors(sctx);
 451         si_emit_compute_shader_userdata(sctx);
 452
 453         if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
 454                 sctx->atoms.s.render_cond->emit(&sctx->b,
 455                                                 sctx->atoms.s.render_cond);
 456                 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
 457         }
 458
 459         if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
 460                 si_upload_compute_input(sctx, info);
 461
 462         /* Global buffers */
 463         for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
 464                 struct r600_resource *buffer =
 465                                 (struct r600_resource*)program->global_buffers[i];
 466                 if (!buffer) {
 467                         continue;
 468                 }
 469                 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
 470                                           RADEON_USAGE_READWRITE,
 471                                           RADEON_PRIO_COMPUTE_GLOBAL);
 472         }
 473
 474         if (program->ir_type == PIPE_SHADER_IR_TGSI)
 475                 si_setup_tgsi_grid(sctx, info);
 476
 477         si_emit_dispatch_packets(sctx, info);
 478 }
 479
 480
 481 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
 482         struct si_compute *program = (struct si_compute *)state;
 483         struct si_context *sctx = (struct si_context*)ctx;
 484
 485         if (!state) {
 486                 return;
 487         }
 488
 489         if (program == sctx->cs_shader_state.program)
 490                 sctx->cs_shader_state.program = NULL;
 491
 492         if (program == sctx->cs_shader_state.emitted_program)
 493                 sctx->cs_shader_state.emitted_program = NULL;
 494
 495         si_shader_destroy(&program->shader);
 496         FREE(program);
 497 }
 498
 499 static void si_set_compute_resources(struct pipe_context * ctx_,
 500                 unsigned start, unsigned count,
 501                 struct pipe_surface ** surfaces) { }
 502
 503 void si_init_compute_functions(struct si_context *sctx)
 504 {
 505         sctx->b.b.create_compute_state = si_create_compute_state;
 506         sctx->b.b.delete_compute_state = si_delete_compute_state;
 507         sctx->b.b.bind_compute_state = si_bind_compute_state;
 508 /*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
 509         sctx->b.b.set_compute_resources = si_set_compute_resources;
 510         sctx->b.b.set_global_binding = si_set_global_binding;
 511         sctx->b.b.launch_grid = si_launch_grid;
 512 }