src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include "si_compute.h"
  27
  28 #include "ac_rtld.h"
  29 #include "amd_kernel_code_t.h"
  30 #include "nir/tgsi_to_nir.h"
  31 #include "si_build_pm4.h"
  32 #include "util/u_async_debug.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_upload_mgr.h"
  35
  36 #define COMPUTE_DBG(sscreen, fmt, args...)                                                         \
  37    do {                                                                                            \
  38       if ((sscreen->debug_flags & DBG(COMPUTE)))                                                   \
  39          fprintf(stderr, fmt, ##args);                                                             \
  40    } while (0);
  41
  42 struct dispatch_packet {
  43    uint16_t header;
  44    uint16_t setup;
  45    uint16_t workgroup_size_x;
  46    uint16_t workgroup_size_y;
  47    uint16_t workgroup_size_z;
  48    uint16_t reserved0;
  49    uint32_t grid_size_x;
  50    uint32_t grid_size_y;
  51    uint32_t grid_size_z;
  52    uint32_t private_segment_size;
  53    uint32_t group_segment_size;
  54    uint64_t kernel_object;
  55    uint64_t kernarg_address;
  56    uint64_t reserved2;
  57 };
  58
  59 static const amd_kernel_code_t *si_compute_get_code_object(const struct si_compute *program,
  60                                                            uint64_t symbol_offset)
  61 {
  62    const struct si_shader_selector *sel = &program->sel;
  63
  64    if (program->ir_type != PIPE_SHADER_IR_NATIVE)
  65       return NULL;
  66
  67    struct ac_rtld_binary rtld;
  68    if (!ac_rtld_open(&rtld,
  69                      (struct ac_rtld_open_info){.info = &sel->screen->info,
  70                                                 .shader_type = MESA_SHADER_COMPUTE,
  71                                                 .wave_size = sel->screen->compute_wave_size,
  72                                                 .num_parts = 1,
  73                                                 .elf_ptrs = &program->shader.binary.elf_buffer,
  74                                                 .elf_sizes = &program->shader.binary.elf_size}))
  75       return NULL;
  76
  77    const amd_kernel_code_t *result = NULL;
  78    const char *text;
  79    size_t size;
  80    if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
  81       goto out;
  82
  83    if (symbol_offset + sizeof(amd_kernel_code_t) > size)
  84       goto out;
  85
  86    result = (const amd_kernel_code_t *)(text + symbol_offset);
  87
  88 out:
  89    ac_rtld_close(&rtld);
  90    return result;
  91 }
  92
  93 static void code_object_to_config(const amd_kernel_code_t *code_object,
  94                                   struct ac_shader_config *out_config)
  95 {
  96
  97    uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
  98    uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
  99    out_config->num_sgprs = code_object->wavefront_sgpr_count;
 100    out_config->num_vgprs = code_object->workitem_vgpr_count;
 101    out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
 102    out_config->rsrc1 = rsrc1;
 103    out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
 104    out_config->rsrc2 = rsrc2;
 105    out_config->scratch_bytes_per_wave =
 106       align(code_object->workitem_private_segment_byte_size * 64, 1024);
 107 }
 108
 109 /* Asynchronous compute shader compilation. */
 110 static void si_create_compute_state_async(void *job, int thread_index)
 111 {
 112    struct si_compute *program = (struct si_compute *)job;
 113    struct si_shader_selector *sel = &program->sel;
 114    struct si_shader *shader = &program->shader;
 115    struct ac_llvm_compiler *compiler;
 116    struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
 117    struct si_screen *sscreen = sel->screen;
 118
 119    assert(!debug->debug_message || debug->async);
 120    assert(thread_index >= 0);
 121    assert(thread_index < ARRAY_SIZE(sscreen->compiler));
 122    compiler = &sscreen->compiler[thread_index];
 123
 124    if (!compiler->passes)
 125       si_init_compiler(sscreen, compiler);
 126
 127    assert(program->ir_type == PIPE_SHADER_IR_NIR);
 128    si_nir_scan_shader(sel->nir, &sel->info);
 129
 130    /* Store the declared LDS size into si_shader_info for the shader
 131     * cache to include it.
 132     */
 133    sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
 134
 135    si_get_active_slot_masks(&sel->info, &sel->active_const_and_shader_buffers,
 136                             &sel->active_samplers_and_images);
 137
 138    program->shader.is_monolithic = true;
 139    program->reads_variable_block_size =
 140       sel->info.uses_block_size && sel->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
 141    program->num_cs_user_data_dwords =
 142       sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
 143
 144    unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS + (sel->info.uses_grid_size ? 3 : 0) +
 145                          (program->reads_variable_block_size ? 3 : 0) +
 146                          program->num_cs_user_data_dwords;
 147
 148    /* Fast path for compute shaders - some descriptors passed via user SGPRs. */
 149    /* Shader buffers in user SGPRs. */
 150    for (unsigned i = 0; i < 3 && user_sgprs <= 12 && sel->info.shader_buffers_declared & (1 << i); i++) {
 151       user_sgprs = align(user_sgprs, 4);
 152       if (i == 0)
 153          sel->cs_shaderbufs_sgpr_index = user_sgprs;
 154       user_sgprs += 4;
 155       sel->cs_num_shaderbufs_in_user_sgprs++;
 156    }
 157
 158    /* Images in user SGPRs. */
 159    unsigned non_msaa_images = sel->info.images_declared & ~sel->info.msaa_images_declared;
 160
 161    for (unsigned i = 0; i < 3 && non_msaa_images & (1 << i); i++) {
 162       unsigned num_sgprs = sel->info.image_buffers & (1 << i) ? 4 : 8;
 163
 164       if (align(user_sgprs, num_sgprs) + num_sgprs > 16)
 165          break;
 166
 167       user_sgprs = align(user_sgprs, num_sgprs);
 168       if (i == 0)
 169          sel->cs_images_sgpr_index = user_sgprs;
 170       user_sgprs += num_sgprs;
 171       sel->cs_num_images_in_user_sgprs++;
 172    }
 173    sel->cs_images_num_sgprs = user_sgprs - sel->cs_images_sgpr_index;
 174    assert(user_sgprs <= 16);
 175
 176    unsigned char ir_sha1_cache_key[20];
 177    si_get_ir_cache_key(sel, false, false, ir_sha1_cache_key);
 178
 179    /* Try to load the shader from the shader cache. */
 180    simple_mtx_lock(&sscreen->shader_cache_mutex);
 181
 182    if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
 183       simple_mtx_unlock(&sscreen->shader_cache_mutex);
 184
 185       si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
 186       si_shader_dump(sscreen, shader, debug, stderr, true);
 187
 188       if (!si_shader_binary_upload(sscreen, shader, 0))
 189          program->shader.compilation_failed = true;
 190    } else {
 191       simple_mtx_unlock(&sscreen->shader_cache_mutex);
 192
 193       if (!si_create_shader_variant(sscreen, compiler, &program->shader, debug)) {
 194          program->shader.compilation_failed = true;
 195          return;
 196       }
 197
 198       bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
 199
 200       shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) /
 201                                             (sscreen->compute_wave_size == 32 ? 8 : 4)) |
 202                              S_00B848_DX10_CLAMP(1) |
 203                              S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
 204                              S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
 205                              S_00B848_FLOAT_MODE(shader->config.float_mode);
 206
 207       if (sscreen->info.chip_class < GFX10) {
 208          shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
 209       }
 210
 211       shader->config.rsrc2 = S_00B84C_USER_SGPR(user_sgprs) | S_00B84C_SCRATCH_EN(scratch_enabled) |
 212                              S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
 213                              S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
 214                              S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
 215                              S_00B84C_TG_SIZE_EN(sel->info.uses_subgroup_info) |
 216                              S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2]
 217                                                         ? 2
 218                                                         : sel->info.uses_thread_id[1] ? 1 : 0) |
 219                              S_00B84C_LDS_SIZE(shader->config.lds_size);
 220
 221       simple_mtx_lock(&sscreen->shader_cache_mutex);
 222       si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
 223       simple_mtx_unlock(&sscreen->shader_cache_mutex);
 224    }
 225
 226    ralloc_free(sel->nir);
 227    sel->nir = NULL;
 228 }
 229
 230 static void *si_create_compute_state(struct pipe_context *ctx, const struct pipe_compute_state *cso)
 231 {
 232    struct si_context *sctx = (struct si_context *)ctx;
 233    struct si_screen *sscreen = (struct si_screen *)ctx->screen;
 234    struct si_compute *program = CALLOC_STRUCT(si_compute);
 235    struct si_shader_selector *sel = &program->sel;
 236
 237    pipe_reference_init(&sel->base.reference, 1);
 238    sel->type = PIPE_SHADER_COMPUTE;
 239    sel->screen = sscreen;
 240    program->shader.selector = &program->sel;
 241    program->ir_type = cso->ir_type;
 242    program->local_size = cso->req_local_mem;
 243    program->private_size = cso->req_private_mem;
 244    program->input_size = cso->req_input_mem;
 245
 246    if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
 247       if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
 248          program->ir_type = PIPE_SHADER_IR_NIR;
 249          sel->nir = tgsi_to_nir(cso->prog, ctx->screen, true);
 250       } else {
 251          assert(cso->ir_type == PIPE_SHADER_IR_NIR);
 252          sel->nir = (struct nir_shader *)cso->prog;
 253       }
 254
 255       sel->compiler_ctx_state.debug = sctx->debug;
 256       sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
 257       p_atomic_inc(&sscreen->num_shaders_created);
 258
 259       si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE, &sel->ready, &sel->compiler_ctx_state,
 260                                   program, si_create_compute_state_async);
 261    } else {
 262       const struct pipe_binary_program_header *header;
 263       header = cso->prog;
 264
 265       program->shader.binary.elf_size = header->num_bytes;
 266       program->shader.binary.elf_buffer = malloc(header->num_bytes);
 267       if (!program->shader.binary.elf_buffer) {
 268          FREE(program);
 269          return NULL;
 270       }
 271       memcpy((void *)program->shader.binary.elf_buffer, header->blob, header->num_bytes);
 272
 273       const amd_kernel_code_t *code_object = si_compute_get_code_object(program, 0);
 274       code_object_to_config(code_object, &program->shader.config);
 275
 276       si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
 277       if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
 278          fprintf(stderr, "LLVM failed to upload shader\n");
 279          free((void *)program->shader.binary.elf_buffer);
 280          FREE(program);
 281          return NULL;
 282       }
 283    }
 284
 285    return program;
 286 }
 287
 288 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 289 {
 290    struct si_context *sctx = (struct si_context *)ctx;
 291    struct si_compute *program = (struct si_compute *)state;
 292    struct si_shader_selector *sel = &program->sel;
 293
 294    sctx->cs_shader_state.program = program;
 295    if (!program)
 296       return;
 297
 298    /* Wait because we need active slot usage masks. */
 299    if (program->ir_type != PIPE_SHADER_IR_NATIVE)
 300       util_queue_fence_wait(&sel->ready);
 301
 302    si_set_active_descriptors(sctx,
 303                              SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
 304                              sel->active_const_and_shader_buffers);
 305    si_set_active_descriptors(sctx, SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
 306                              sel->active_samplers_and_images);
 307
 308    sctx->compute_shaderbuf_sgprs_dirty = true;
 309    sctx->compute_image_sgprs_dirty = true;
 310 }
 311
 312 static void si_set_global_binding(struct pipe_context *ctx, unsigned first, unsigned n,
 313                                   struct pipe_resource **resources, uint32_t **handles)
 314 {
 315    unsigned i;
 316    struct si_context *sctx = (struct si_context *)ctx;
 317    struct si_compute *program = sctx->cs_shader_state.program;
 318
 319    if (first + n > program->max_global_buffers) {
 320       unsigned old_max = program->max_global_buffers;
 321       program->max_global_buffers = first + n;
 322       program->global_buffers = realloc(
 323          program->global_buffers, program->max_global_buffers * sizeof(program->global_buffers[0]));
 324       if (!program->global_buffers) {
 325          fprintf(stderr, "radeonsi: failed to allocate compute global_buffers\n");
 326          return;
 327       }
 328
 329       memset(&program->global_buffers[old_max], 0,
 330              (program->max_global_buffers - old_max) * sizeof(program->global_buffers[0]));
 331    }
 332
 333    if (!resources) {
 334       for (i = 0; i < n; i++) {
 335          pipe_resource_reference(&program->global_buffers[first + i], NULL);
 336       }
 337       return;
 338    }
 339
 340    for (i = 0; i < n; i++) {
 341       uint64_t va;
 342       uint32_t offset;
 343       pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
 344       va = si_resource(resources[i])->gpu_address;
 345       offset = util_le32_to_cpu(*handles[i]);
 346       va += offset;
 347       va = util_cpu_to_le64(va);
 348       memcpy(handles[i], &va, sizeof(va));
 349    }
 350 }
 351
 352 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
 353 {
 354    uint64_t bc_va;
 355
 356    radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
 357    /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
 358     * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
 359    radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 360    radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 361
 362    if (sctx->chip_class >= GFX7) {
 363       /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
 364       radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
 365       radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 366       radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 367    }
 368
 369    if (sctx->chip_class >= GFX10)
 370       radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
 371
 372    /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 373     * and is now per pipe, so it should be handled in the
 374     * kernel if we want to use something other than the default value,
 375     * which is now 0x22f.
 376     */
 377    if (sctx->chip_class <= GFX6) {
 378       /* XXX: This should be:
 379        * (number of compute units) * 4 * (waves per simd) - 1 */
 380
 381       radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
 382    }
 383
 384    /* Set the pointer to border colors. */
 385    bc_va = sctx->border_color_buffer->gpu_address;
 386
 387    if (sctx->chip_class >= GFX7) {
 388       radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
 389       radeon_emit(cs, bc_va >> 8);                    /* R_030E00_TA_CS_BC_BASE_ADDR */
 390       radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
 391    } else {
 392       if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
 393          radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
 394       }
 395    }
 396 }
 397
 398 static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_shader *shader,
 399                                             struct ac_shader_config *config)
 400 {
 401    uint64_t scratch_bo_size, scratch_needed;
 402    scratch_bo_size = 0;
 403    scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
 404    if (sctx->compute_scratch_buffer)
 405       scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
 406
 407    if (scratch_bo_size < scratch_needed) {
 408       si_resource_reference(&sctx->compute_scratch_buffer, NULL);
 409
 410       sctx->compute_scratch_buffer =
 411          si_aligned_buffer_create(&sctx->screen->b, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
 412                                   scratch_needed, sctx->screen->info.pte_fragment_size);
 413
 414       if (!sctx->compute_scratch_buffer)
 415          return false;
 416    }
 417
 418    if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
 419       uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 420
 421       if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
 422          return false;
 423
 424       si_resource_reference(&shader->scratch_bo, sctx->compute_scratch_buffer);
 425    }
 426
 427    return true;
 428 }
 429
 430 static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute *program,
 431                                      struct si_shader *shader, const amd_kernel_code_t *code_object,
 432                                      unsigned offset)
 433 {
 434    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 435    struct ac_shader_config inline_config = {0};
 436    struct ac_shader_config *config;
 437    uint64_t shader_va;
 438
 439    if (sctx->cs_shader_state.emitted_program == program && sctx->cs_shader_state.offset == offset)
 440       return true;
 441
 442    if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
 443       config = &shader->config;
 444    } else {
 445       unsigned lds_blocks;
 446
 447       config = &inline_config;
 448       code_object_to_config(code_object, config);
 449
 450       lds_blocks = config->lds_size;
 451       /* XXX: We are over allocating LDS.  For GFX6, the shader reports
 452        * LDS in blocks of 256 bytes, so if there are 4 bytes lds
 453        * allocated in the shader and 4 bytes allocated by the state
 454        * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
 455        */
 456       if (sctx->chip_class <= GFX6) {
 457          lds_blocks += align(program->local_size, 256) >> 8;
 458       } else {
 459          lds_blocks += align(program->local_size, 512) >> 9;
 460       }
 461
 462       /* TODO: use si_multiwave_lds_size_workaround */
 463       assert(lds_blocks <= 0xFF);
 464
 465       config->rsrc2 &= C_00B84C_LDS_SIZE;
 466       config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
 467    }
 468
 469    if (!si_setup_compute_scratch_buffer(sctx, shader, config))
 470       return false;
 471
 472    if (shader->scratch_bo) {
 473       COMPUTE_DBG(sctx->screen,
 474                   "Waves: %u; Scratch per wave: %u bytes; "
 475                   "Total Scratch: %u bytes\n",
 476                   sctx->scratch_waves, config->scratch_bytes_per_wave,
 477                   config->scratch_bytes_per_wave * sctx->scratch_waves);
 478
 479       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->scratch_bo, RADEON_USAGE_READWRITE,
 480                                 RADEON_PRIO_SCRATCH_BUFFER);
 481    }
 482
 483    /* Prefetch the compute shader to TC L2.
 484     *
 485     * We should also prefetch graphics shaders if a compute dispatch was
 486     * the last command, and the compute shader if a draw call was the last
 487     * command. However, that would add more complexity and we're likely
 488     * to get a shader state change in that case anyway.
 489     */
 490    if (sctx->chip_class >= GFX7) {
 491       cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b, 0, program->shader.bo->b.b.width0);
 492    }
 493
 494    shader_va = shader->bo->gpu_address + offset;
 495    if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
 496       /* Shader code is placed after the amd_kernel_code_t
 497        * struct. */
 498       shader_va += sizeof(amd_kernel_code_t);
 499    }
 500
 501    radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo, RADEON_USAGE_READ,
 502                              RADEON_PRIO_SHADER_BINARY);
 503
 504    radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
 505    radeon_emit(cs, shader_va >> 8);
 506    radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
 507
 508    radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
 509    radeon_emit(cs, config->rsrc1);
 510    radeon_emit(cs, config->rsrc2);
 511
 512    COMPUTE_DBG(sctx->screen,
 513                "COMPUTE_PGM_RSRC1: 0x%08x "
 514                "COMPUTE_PGM_RSRC2: 0x%08x\n",
 515                config->rsrc1, config->rsrc2);
 516
 517    sctx->max_seen_compute_scratch_bytes_per_wave =
 518       MAX2(sctx->max_seen_compute_scratch_bytes_per_wave, config->scratch_bytes_per_wave);
 519
 520    radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
 521                      S_00B860_WAVES(sctx->scratch_waves) |
 522                         S_00B860_WAVESIZE(sctx->max_seen_compute_scratch_bytes_per_wave >> 10));
 523
 524    sctx->cs_shader_state.emitted_program = program;
 525    sctx->cs_shader_state.offset = offset;
 526    sctx->cs_shader_state.uses_scratch = config->scratch_bytes_per_wave != 0;
 527
 528    return true;
 529 }
 530
 531 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
 532                                           const amd_kernel_code_t *code_object, unsigned user_sgpr)
 533 {
 534    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 535    uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 536
 537    unsigned max_private_element_size =
 538       AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
 539
 540    uint32_t scratch_dword0 = scratch_va & 0xffffffff;
 541    uint32_t scratch_dword1 =
 542       S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE(1);
 543
 544    /* Disable address clamping */
 545    uint32_t scratch_dword2 = 0xffffffff;
 546    uint32_t scratch_dword3 = S_008F0C_INDEX_STRIDE(3) | S_008F0C_ADD_TID_ENABLE(1);
 547
 548    if (sctx->chip_class >= GFX9) {
 549       assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
 550    } else {
 551       scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
 552
 553       if (sctx->chip_class < GFX8) {
 554          /* BUF_DATA_FORMAT is ignored, but it cannot be
 555           * BUF_DATA_FORMAT_INVALID. */
 556          scratch_dword3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
 557       }
 558    }
 559
 560    radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 4);
 561    radeon_emit(cs, scratch_dword0);
 562    radeon_emit(cs, scratch_dword1);
 563    radeon_emit(cs, scratch_dword2);
 564    radeon_emit(cs, scratch_dword3);
 565 }
 566
 567 static void si_setup_user_sgprs_co_v2(struct si_context *sctx, const amd_kernel_code_t *code_object,
 568                                       const struct pipe_grid_info *info, uint64_t kernel_args_va)
 569 {
 570    struct si_compute *program = sctx->cs_shader_state.program;
 571    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 572
 573    static const enum amd_code_property_mask_t workgroup_count_masks[] = {
 574       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
 575       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
 576       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z};
 577
 578    unsigned i, user_sgpr = 0;
 579    if (AMD_HSA_BITS_GET(code_object->code_properties,
 580                         AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
 581       if (code_object->workitem_private_segment_byte_size > 0) {
 582          setup_scratch_rsrc_user_sgprs(sctx, code_object, user_sgpr);
 583       }
 584       user_sgpr += 4;
 585    }
 586
 587    if (AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
 588       struct dispatch_packet dispatch;
 589       unsigned dispatch_offset;
 590       struct si_resource *dispatch_buf = NULL;
 591       uint64_t dispatch_va;
 592
 593       /* Upload dispatch ptr */
 594       memset(&dispatch, 0, sizeof(dispatch));
 595
 596       dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
 597       dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
 598       dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
 599
 600       dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
 601       dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
 602       dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
 603
 604       dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
 605       dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
 606
 607       dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
 608
 609       u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch), 256, &dispatch, &dispatch_offset,
 610                     (struct pipe_resource **)&dispatch_buf);
 611
 612       if (!dispatch_buf) {
 613          fprintf(stderr, "Error: Failed to allocate dispatch "
 614                          "packet.");
 615       }
 616       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf, RADEON_USAGE_READ,
 617                                 RADEON_PRIO_CONST_BUFFER);
 618
 619       dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
 620
 621       radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
 622       radeon_emit(cs, dispatch_va);
 623       radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) | S_008F04_STRIDE(0));
 624
 625       si_resource_reference(&dispatch_buf, NULL);
 626       user_sgpr += 2;
 627    }
 628
 629    if (AMD_HSA_BITS_GET(code_object->code_properties,
 630                         AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
 631       radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
 632       radeon_emit(cs, kernel_args_va);
 633       radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(kernel_args_va >> 32) | S_008F04_STRIDE(0));
 634       user_sgpr += 2;
 635    }
 636
 637    for (i = 0; i < 3 && user_sgpr < 16; i++) {
 638       if (code_object->code_properties & workgroup_count_masks[i]) {
 639          radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 1);
 640          radeon_emit(cs, info->grid[i]);
 641          user_sgpr += 1;
 642       }
 643    }
 644 }
 645
 646 static bool si_upload_compute_input(struct si_context *sctx, const amd_kernel_code_t *code_object,
 647                                     const struct pipe_grid_info *info)
 648 {
 649    struct si_compute *program = sctx->cs_shader_state.program;
 650    struct si_resource *input_buffer = NULL;
 651    uint32_t kernel_args_offset = 0;
 652    uint32_t *kernel_args;
 653    void *kernel_args_ptr;
 654    uint64_t kernel_args_va;
 655
 656    u_upload_alloc(sctx->b.const_uploader, 0, program->input_size,
 657                   sctx->screen->info.tcc_cache_line_size, &kernel_args_offset,
 658                   (struct pipe_resource **)&input_buffer, &kernel_args_ptr);
 659
 660    if (unlikely(!kernel_args_ptr))
 661       return false;
 662
 663    kernel_args = (uint32_t *)kernel_args_ptr;
 664    kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
 665
 666    memcpy(kernel_args, info->input, program->input_size);
 667
 668    for (unsigned i = 0; i < program->input_size / 4; i++) {
 669       COMPUTE_DBG(sctx->screen, "input %u : %u\n", i, kernel_args[i]);
 670    }
 671
 672    radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer, RADEON_USAGE_READ,
 673                              RADEON_PRIO_CONST_BUFFER);
 674
 675    si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
 676    si_resource_reference(&input_buffer, NULL);
 677    return true;
 678 }
 679
 680 static void si_setup_nir_user_data(struct si_context *sctx, const struct pipe_grid_info *info)
 681 {
 682    struct si_compute *program = sctx->cs_shader_state.program;
 683    struct si_shader_selector *sel = &program->sel;
 684    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 685    unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 + 4 * SI_NUM_RESOURCE_SGPRS;
 686    unsigned block_size_reg = grid_size_reg +
 687                              /* 12 bytes = 3 dwords. */
 688                              12 * sel->info.uses_grid_size;
 689    unsigned cs_user_data_reg = block_size_reg + 12 * program->reads_variable_block_size;
 690
 691    if (info->indirect) {
 692       if (sel->info.uses_grid_size) {
 693          for (unsigned i = 0; i < 3; ++i) {
 694             si_cp_copy_data(sctx, sctx->gfx_cs, COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
 695                             COPY_DATA_SRC_MEM, si_resource(info->indirect),
 696                             info->indirect_offset + 4 * i);
 697          }
 698       }
 699    } else {
 700       if (sel->info.uses_grid_size) {
 701          radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
 702          radeon_emit(cs, info->grid[0]);
 703          radeon_emit(cs, info->grid[1]);
 704          radeon_emit(cs, info->grid[2]);
 705       }
 706       if (program->reads_variable_block_size) {
 707          radeon_set_sh_reg_seq(cs, block_size_reg, 3);
 708          radeon_emit(cs, info->block[0]);
 709          radeon_emit(cs, info->block[1]);
 710          radeon_emit(cs, info->block[2]);
 711       }
 712    }
 713
 714    if (program->num_cs_user_data_dwords) {
 715       radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
 716       radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
 717    }
 718 }
 719
 720 static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_grid_info *info)
 721 {
 722    struct si_screen *sscreen = sctx->screen;
 723    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 724    bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
 725    unsigned threads_per_threadgroup = info->block[0] * info->block[1] * info->block[2];
 726    unsigned waves_per_threadgroup =
 727       DIV_ROUND_UP(threads_per_threadgroup, sscreen->compute_wave_size);
 728    unsigned threadgroups_per_cu = 1;
 729
 730    if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1)
 731       threadgroups_per_cu = 2;
 732
 733    radeon_set_sh_reg(
 734       cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
 735       ac_get_compute_resource_limits(&sscreen->info, waves_per_threadgroup,
 736                                      sctx->cs_max_waves_per_sh, threadgroups_per_cu));
 737
 738    unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) | S_00B800_FORCE_START_AT_000(1) |
 739                                  /* If the KMD allows it (there is a KMD hw register for it),
 740                                   * allow launching waves out-of-order. (same as Vulkan) */
 741                                  S_00B800_ORDER_MODE(sctx->chip_class >= GFX7) |
 742                                  S_00B800_CS_W32_EN(sscreen->compute_wave_size == 32);
 743
 744    const uint *last_block = info->last_block;
 745    bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
 746
 747    radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
 748
 749    if (partial_block_en) {
 750       unsigned partial[3];
 751
 752       /* If no partial_block, these should be an entire block size, not 0. */
 753       partial[0] = last_block[0] ? last_block[0] : info->block[0];
 754       partial[1] = last_block[1] ? last_block[1] : info->block[1];
 755       partial[2] = last_block[2] ? last_block[2] : info->block[2];
 756
 757       radeon_emit(
 758          cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) | S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
 759       radeon_emit(
 760          cs, S_00B820_NUM_THREAD_FULL(info->block[1]) | S_00B820_NUM_THREAD_PARTIAL(partial[1]));
 761       radeon_emit(
 762          cs, S_00B824_NUM_THREAD_FULL(info->block[2]) | S_00B824_NUM_THREAD_PARTIAL(partial[2]));
 763
 764       dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
 765    } else {
 766       radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
 767       radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
 768       radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
 769    }
 770
 771    if (info->indirect) {
 772       uint64_t base_va = si_resource(info->indirect)->gpu_address;
 773
 774       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(info->indirect), RADEON_USAGE_READ,
 775                                 RADEON_PRIO_DRAW_INDIRECT);
 776
 777       radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) | PKT3_SHADER_TYPE_S(1));
 778       radeon_emit(cs, 1);
 779       radeon_emit(cs, base_va);
 780       radeon_emit(cs, base_va >> 32);
 781
 782       radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
 783       radeon_emit(cs, info->indirect_offset);
 784       radeon_emit(cs, dispatch_initiator);
 785    } else {
 786       radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
 787       radeon_emit(cs, info->grid[0]);
 788       radeon_emit(cs, info->grid[1]);
 789       radeon_emit(cs, info->grid[2]);
 790       radeon_emit(cs, dispatch_initiator);
 791    }
 792 }
 793
 794 static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
 795 {
 796    struct si_context *sctx = (struct si_context *)ctx;
 797    struct si_compute *program = sctx->cs_shader_state.program;
 798    const amd_kernel_code_t *code_object = si_compute_get_code_object(program, info->pc);
 799    int i;
 800    /* HW bug workaround when CS threadgroups > 256 threads and async
 801     * compute isn't used, i.e. only one compute job can run at a time.
 802     * If async compute is possible, the threadgroup size must be limited
 803     * to 256 threads on all queues to avoid the bug.
 804     * Only GFX6 and certain GFX7 chips are affected.
 805     */
 806    bool cs_regalloc_hang =
 807       (sctx->chip_class == GFX6 || sctx->family == CHIP_BONAIRE || sctx->family == CHIP_KABINI) &&
 808       info->block[0] * info->block[1] * info->block[2] > 256;
 809
 810    if (cs_regalloc_hang)
 811       sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
 812
 813    if (program->ir_type != PIPE_SHADER_IR_NATIVE && program->shader.compilation_failed)
 814       return;
 815
 816    if (sctx->has_graphics) {
 817       if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
 818          si_update_fb_dirtiness_after_rendering(sctx);
 819          sctx->last_num_draw_calls = sctx->num_draw_calls;
 820       }
 821
 822       si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
 823    }
 824
 825    /* Add buffer sizes for memory checking in need_cs_space. */
 826    si_context_add_resource_size(sctx, &program->shader.bo->b.b);
 827    /* TODO: add the scratch buffer */
 828
 829    if (info->indirect) {
 830       si_context_add_resource_size(sctx, info->indirect);
 831
 832       /* Indirect buffers use TC L2 on GFX9, but not older hw. */
 833       if (sctx->chip_class <= GFX8 && si_resource(info->indirect)->TC_L2_dirty) {
 834          sctx->flags |= SI_CONTEXT_WB_L2;
 835          si_resource(info->indirect)->TC_L2_dirty = false;
 836       }
 837    }
 838
 839    si_need_gfx_cs_space(sctx);
 840
 841    /* If we're using a secure context, determine if cs must be secure or not */
 842    if (unlikely(sctx->ws->ws_is_secure(sctx->ws))) {
 843       bool secure = si_compute_resources_check_encrypted(sctx);
 844       if (secure != sctx->ws->cs_is_secure(sctx->gfx_cs)) {
 845          si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 846          sctx->ws->cs_set_secure(sctx->gfx_cs, secure);
 847       }
 848    }
 849
 850    if (sctx->bo_list_add_all_compute_resources)
 851       si_compute_resources_add_all_to_bo_list(sctx);
 852
 853    if (!sctx->cs_shader_state.initialized) {
 854       si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
 855
 856       sctx->cs_shader_state.emitted_program = NULL;
 857       sctx->cs_shader_state.initialized = true;
 858    }
 859
 860    if (sctx->flags)
 861       sctx->emit_cache_flush(sctx);
 862
 863    if (!si_switch_compute_shader(sctx, program, &program->shader, code_object, info->pc))
 864       return;
 865
 866    si_upload_compute_shader_descriptors(sctx);
 867    si_emit_compute_shader_pointers(sctx);
 868
 869    if (sctx->has_graphics && si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
 870       sctx->atoms.s.render_cond.emit(sctx);
 871       si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
 872    }
 873
 874    if (program->ir_type == PIPE_SHADER_IR_NATIVE &&
 875        unlikely(!si_upload_compute_input(sctx, code_object, info)))
 876       return;
 877
 878    /* Global buffers */
 879    for (i = 0; i < program->max_global_buffers; i++) {
 880       struct si_resource *buffer = si_resource(program->global_buffers[i]);
 881       if (!buffer) {
 882          continue;
 883       }
 884       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer, RADEON_USAGE_READWRITE,
 885                                 RADEON_PRIO_COMPUTE_GLOBAL);
 886    }
 887
 888    if (program->ir_type != PIPE_SHADER_IR_NATIVE)
 889       si_setup_nir_user_data(sctx, info);
 890
 891    si_emit_dispatch_packets(sctx, info);
 892
 893    if (unlikely(sctx->current_saved_cs)) {
 894       si_trace_emit(sctx);
 895       si_log_compute_state(sctx, sctx->log);
 896    }
 897
 898    sctx->compute_is_busy = true;
 899    sctx->num_compute_calls++;
 900    if (sctx->cs_shader_state.uses_scratch)
 901       sctx->num_spill_compute_calls++;
 902
 903    if (cs_regalloc_hang)
 904       sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
 905 }
 906
 907 void si_destroy_compute(struct si_compute *program)
 908 {
 909    struct si_shader_selector *sel = &program->sel;
 910
 911    if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
 912       util_queue_drop_job(&sel->screen->shader_compiler_queue, &sel->ready);
 913       util_queue_fence_destroy(&sel->ready);
 914    }
 915
 916    for (unsigned i = 0; i < program->max_global_buffers; i++)
 917       pipe_resource_reference(&program->global_buffers[i], NULL);
 918    FREE(program->global_buffers);
 919
 920    si_shader_destroy(&program->shader);
 921    ralloc_free(program->sel.nir);
 922    FREE(program);
 923 }
 924
 925 static void si_delete_compute_state(struct pipe_context *ctx, void *state)
 926 {
 927    struct si_compute *program = (struct si_compute *)state;
 928    struct si_context *sctx = (struct si_context *)ctx;
 929
 930    if (!state)
 931       return;
 932
 933    if (program == sctx->cs_shader_state.program)
 934       sctx->cs_shader_state.program = NULL;
 935
 936    if (program == sctx->cs_shader_state.emitted_program)
 937       sctx->cs_shader_state.emitted_program = NULL;
 938
 939    si_compute_reference(&program, NULL);
 940 }
 941
 942 static void si_set_compute_resources(struct pipe_context *ctx_, unsigned start, unsigned count,
 943                                      struct pipe_surface **surfaces)
 944 {
 945 }
 946
 947 void si_init_compute_functions(struct si_context *sctx)
 948 {
 949    sctx->b.create_compute_state = si_create_compute_state;
 950    sctx->b.delete_compute_state = si_delete_compute_state;
 951    sctx->b.bind_compute_state = si_bind_compute_state;
 952    sctx->b.set_compute_resources = si_set_compute_resources;
 953    sctx->b.set_global_binding = si_set_global_binding;
 954    sctx->b.launch_grid = si_launch_grid;
 955 }