src/gallium/drivers/radeonsi/si_compute.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include "si_compute.h"
  27
  28 #include "ac_rtld.h"
  29 #include "amd_kernel_code_t.h"
  30 #include "nir/tgsi_to_nir.h"
  31 #include "si_build_pm4.h"
  32 #include "util/u_async_debug.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_upload_mgr.h"
  35
  36 #define COMPUTE_DBG(sscreen, fmt, args...)                                                         \
  37    do {                                                                                            \
  38       if ((sscreen->debug_flags & DBG(COMPUTE)))                                                   \
  39          fprintf(stderr, fmt, ##args);                                                             \
  40    } while (0);
  41
  42 struct dispatch_packet {
  43    uint16_t header;
  44    uint16_t setup;
  45    uint16_t workgroup_size_x;
  46    uint16_t workgroup_size_y;
  47    uint16_t workgroup_size_z;
  48    uint16_t reserved0;
  49    uint32_t grid_size_x;
  50    uint32_t grid_size_y;
  51    uint32_t grid_size_z;
  52    uint32_t private_segment_size;
  53    uint32_t group_segment_size;
  54    uint64_t kernel_object;
  55    uint64_t kernarg_address;
  56    uint64_t reserved2;
  57 };
  58
  59 static const amd_kernel_code_t *si_compute_get_code_object(const struct si_compute *program,
  60                                                            uint64_t symbol_offset)
  61 {
  62    const struct si_shader_selector *sel = &program->sel;
  63
  64    if (program->ir_type != PIPE_SHADER_IR_NATIVE)
  65       return NULL;
  66
  67    struct ac_rtld_binary rtld;
  68    if (!ac_rtld_open(&rtld,
  69                      (struct ac_rtld_open_info){.info = &sel->screen->info,
  70                                                 .shader_type = MESA_SHADER_COMPUTE,
  71                                                 .wave_size = sel->screen->compute_wave_size,
  72                                                 .num_parts = 1,
  73                                                 .elf_ptrs = &program->shader.binary.elf_buffer,
  74                                                 .elf_sizes = &program->shader.binary.elf_size}))
  75       return NULL;
  76
  77    const amd_kernel_code_t *result = NULL;
  78    const char *text;
  79    size_t size;
  80    if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
  81       goto out;
  82
  83    if (symbol_offset + sizeof(amd_kernel_code_t) > size)
  84       goto out;
  85
  86    result = (const amd_kernel_code_t *)(text + symbol_offset);
  87
  88 out:
  89    ac_rtld_close(&rtld);
  90    return result;
  91 }
  92
  93 static void code_object_to_config(const amd_kernel_code_t *code_object,
  94                                   struct ac_shader_config *out_config)
  95 {
  96
  97    uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
  98    uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
  99    out_config->num_sgprs = code_object->wavefront_sgpr_count;
 100    out_config->num_vgprs = code_object->workitem_vgpr_count;
 101    out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
 102    out_config->rsrc1 = rsrc1;
 103    out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
 104    out_config->rsrc2 = rsrc2;
 105    out_config->scratch_bytes_per_wave =
 106       align(code_object->workitem_private_segment_byte_size * 64, 1024);
 107 }
 108
 109 /* Asynchronous compute shader compilation. */
 110 static void si_create_compute_state_async(void *job, int thread_index)
 111 {
 112    struct si_compute *program = (struct si_compute *)job;
 113    struct si_shader_selector *sel = &program->sel;
 114    struct si_shader *shader = &program->shader;
 115    struct ac_llvm_compiler *compiler;
 116    struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
 117    struct si_screen *sscreen = sel->screen;
 118
 119    assert(!debug->debug_message || debug->async);
 120    assert(thread_index >= 0);
 121    assert(thread_index < ARRAY_SIZE(sscreen->compiler));
 122    compiler = &sscreen->compiler[thread_index];
 123
 124    if (!compiler->passes)
 125       si_init_compiler(sscreen, compiler);
 126
 127    assert(program->ir_type == PIPE_SHADER_IR_NIR);
 128    si_nir_scan_shader(sel->nir, &sel->info);
 129
 130    /* Store the declared LDS size into si_shader_info for the shader
 131     * cache to include it.
 132     */
 133    sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
 134
 135    si_get_active_slot_masks(&sel->info, &sel->active_const_and_shader_buffers,
 136                             &sel->active_samplers_and_images);
 137
 138    program->shader.is_monolithic = true;
 139    program->reads_variable_block_size =
 140       sel->info.uses_block_size && sel->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
 141    program->num_cs_user_data_dwords =
 142       sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
 143
 144    unsigned char ir_sha1_cache_key[20];
 145    si_get_ir_cache_key(sel, false, false, ir_sha1_cache_key);
 146
 147    /* Try to load the shader from the shader cache. */
 148    simple_mtx_lock(&sscreen->shader_cache_mutex);
 149
 150    if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
 151       simple_mtx_unlock(&sscreen->shader_cache_mutex);
 152
 153       si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
 154       si_shader_dump(sscreen, shader, debug, stderr, true);
 155
 156       if (!si_shader_binary_upload(sscreen, shader, 0))
 157          program->shader.compilation_failed = true;
 158    } else {
 159       simple_mtx_unlock(&sscreen->shader_cache_mutex);
 160
 161       if (!si_create_shader_variant(sscreen, compiler, &program->shader, debug)) {
 162          program->shader.compilation_failed = true;
 163          return;
 164       }
 165
 166       bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
 167       unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS + (sel->info.uses_grid_size ? 3 : 0) +
 168                             (program->reads_variable_block_size ? 3 : 0) +
 169                             program->num_cs_user_data_dwords;
 170
 171       shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) /
 172                                             (sscreen->compute_wave_size == 32 ? 8 : 4)) |
 173                              S_00B848_DX10_CLAMP(1) |
 174                              S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
 175                              S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
 176                              S_00B848_FLOAT_MODE(shader->config.float_mode);
 177
 178       if (sscreen->info.chip_class < GFX10) {
 179          shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
 180       }
 181
 182       shader->config.rsrc2 = S_00B84C_USER_SGPR(user_sgprs) | S_00B84C_SCRATCH_EN(scratch_enabled) |
 183                              S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
 184                              S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
 185                              S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
 186                              S_00B84C_TG_SIZE_EN(sel->info.uses_subgroup_info) |
 187                              S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2]
 188                                                         ? 2
 189                                                         : sel->info.uses_thread_id[1] ? 1 : 0) |
 190                              S_00B84C_LDS_SIZE(shader->config.lds_size);
 191
 192       simple_mtx_lock(&sscreen->shader_cache_mutex);
 193       si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
 194       simple_mtx_unlock(&sscreen->shader_cache_mutex);
 195    }
 196
 197    ralloc_free(sel->nir);
 198    sel->nir = NULL;
 199 }
 200
 201 static void *si_create_compute_state(struct pipe_context *ctx, const struct pipe_compute_state *cso)
 202 {
 203    struct si_context *sctx = (struct si_context *)ctx;
 204    struct si_screen *sscreen = (struct si_screen *)ctx->screen;
 205    struct si_compute *program = CALLOC_STRUCT(si_compute);
 206    struct si_shader_selector *sel = &program->sel;
 207
 208    pipe_reference_init(&sel->base.reference, 1);
 209    sel->type = PIPE_SHADER_COMPUTE;
 210    sel->screen = sscreen;
 211    program->shader.selector = &program->sel;
 212    program->ir_type = cso->ir_type;
 213    program->local_size = cso->req_local_mem;
 214    program->private_size = cso->req_private_mem;
 215    program->input_size = cso->req_input_mem;
 216
 217    if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
 218       if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
 219          program->ir_type = PIPE_SHADER_IR_NIR;
 220          sel->nir = tgsi_to_nir(cso->prog, ctx->screen);
 221       } else {
 222          assert(cso->ir_type == PIPE_SHADER_IR_NIR);
 223          sel->nir = (struct nir_shader *)cso->prog;
 224       }
 225
 226       sel->compiler_ctx_state.debug = sctx->debug;
 227       sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
 228       p_atomic_inc(&sscreen->num_shaders_created);
 229
 230       si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE, &sel->ready, &sel->compiler_ctx_state,
 231                                   program, si_create_compute_state_async);
 232    } else {
 233       const struct pipe_binary_program_header *header;
 234       header = cso->prog;
 235
 236       program->shader.binary.elf_size = header->num_bytes;
 237       program->shader.binary.elf_buffer = malloc(header->num_bytes);
 238       if (!program->shader.binary.elf_buffer) {
 239          FREE(program);
 240          return NULL;
 241       }
 242       memcpy((void *)program->shader.binary.elf_buffer, header->blob, header->num_bytes);
 243
 244       const amd_kernel_code_t *code_object = si_compute_get_code_object(program, 0);
 245       code_object_to_config(code_object, &program->shader.config);
 246
 247       si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
 248       if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
 249          fprintf(stderr, "LLVM failed to upload shader\n");
 250          free((void *)program->shader.binary.elf_buffer);
 251          FREE(program);
 252          return NULL;
 253       }
 254    }
 255
 256    return program;
 257 }
 258
 259 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
 260 {
 261    struct si_context *sctx = (struct si_context *)ctx;
 262    struct si_compute *program = (struct si_compute *)state;
 263    struct si_shader_selector *sel = &program->sel;
 264
 265    sctx->cs_shader_state.program = program;
 266    if (!program)
 267       return;
 268
 269    /* Wait because we need active slot usage masks. */
 270    if (program->ir_type != PIPE_SHADER_IR_NATIVE)
 271       util_queue_fence_wait(&sel->ready);
 272
 273    si_set_active_descriptors(sctx,
 274                              SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
 275                              sel->active_const_and_shader_buffers);
 276    si_set_active_descriptors(sctx, SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
 277                              sel->active_samplers_and_images);
 278 }
 279
 280 static void si_set_global_binding(struct pipe_context *ctx, unsigned first, unsigned n,
 281                                   struct pipe_resource **resources, uint32_t **handles)
 282 {
 283    unsigned i;
 284    struct si_context *sctx = (struct si_context *)ctx;
 285    struct si_compute *program = sctx->cs_shader_state.program;
 286
 287    if (first + n > program->max_global_buffers) {
 288       unsigned old_max = program->max_global_buffers;
 289       program->max_global_buffers = first + n;
 290       program->global_buffers = realloc(
 291          program->global_buffers, program->max_global_buffers * sizeof(program->global_buffers[0]));
 292       if (!program->global_buffers) {
 293          fprintf(stderr, "radeonsi: failed to allocate compute global_buffers\n");
 294          return;
 295       }
 296
 297       memset(&program->global_buffers[old_max], 0,
 298              (program->max_global_buffers - old_max) * sizeof(program->global_buffers[0]));
 299    }
 300
 301    if (!resources) {
 302       for (i = 0; i < n; i++) {
 303          pipe_resource_reference(&program->global_buffers[first + i], NULL);
 304       }
 305       return;
 306    }
 307
 308    for (i = 0; i < n; i++) {
 309       uint64_t va;
 310       uint32_t offset;
 311       pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
 312       va = si_resource(resources[i])->gpu_address;
 313       offset = util_le32_to_cpu(*handles[i]);
 314       va += offset;
 315       va = util_cpu_to_le64(va);
 316       memcpy(handles[i], &va, sizeof(va));
 317    }
 318 }
 319
 320 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
 321 {
 322    uint64_t bc_va;
 323
 324    radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
 325    /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
 326     * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
 327    radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 328    radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 329
 330    if (sctx->chip_class >= GFX7) {
 331       /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
 332       radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
 333       radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 334       radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 335    }
 336
 337    if (sctx->chip_class >= GFX10)
 338       radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
 339
 340    /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
 341     * and is now per pipe, so it should be handled in the
 342     * kernel if we want to use something other than the default value,
 343     * which is now 0x22f.
 344     */
 345    if (sctx->chip_class <= GFX6) {
 346       /* XXX: This should be:
 347        * (number of compute units) * 4 * (waves per simd) - 1 */
 348
 349       radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
 350    }
 351
 352    /* Set the pointer to border colors. */
 353    bc_va = sctx->border_color_buffer->gpu_address;
 354
 355    if (sctx->chip_class >= GFX7) {
 356       radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
 357       radeon_emit(cs, bc_va >> 8);                    /* R_030E00_TA_CS_BC_BASE_ADDR */
 358       radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
 359    } else {
 360       if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
 361          radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
 362       }
 363    }
 364 }
 365
 366 static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_shader *shader,
 367                                             struct ac_shader_config *config)
 368 {
 369    uint64_t scratch_bo_size, scratch_needed;
 370    scratch_bo_size = 0;
 371    scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
 372    if (sctx->compute_scratch_buffer)
 373       scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
 374
 375    if (scratch_bo_size < scratch_needed) {
 376       si_resource_reference(&sctx->compute_scratch_buffer, NULL);
 377
 378       sctx->compute_scratch_buffer =
 379          si_aligned_buffer_create(&sctx->screen->b, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
 380                                   scratch_needed, sctx->screen->info.pte_fragment_size);
 381
 382       if (!sctx->compute_scratch_buffer)
 383          return false;
 384    }
 385
 386    if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
 387       uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 388
 389       if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
 390          return false;
 391
 392       si_resource_reference(&shader->scratch_bo, sctx->compute_scratch_buffer);
 393    }
 394
 395    return true;
 396 }
 397
 398 static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute *program,
 399                                      struct si_shader *shader, const amd_kernel_code_t *code_object,
 400                                      unsigned offset)
 401 {
 402    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 403    struct ac_shader_config inline_config = {0};
 404    struct ac_shader_config *config;
 405    uint64_t shader_va;
 406
 407    if (sctx->cs_shader_state.emitted_program == program && sctx->cs_shader_state.offset == offset)
 408       return true;
 409
 410    if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
 411       config = &shader->config;
 412    } else {
 413       unsigned lds_blocks;
 414
 415       config = &inline_config;
 416       code_object_to_config(code_object, config);
 417
 418       lds_blocks = config->lds_size;
 419       /* XXX: We are over allocating LDS.  For GFX6, the shader reports
 420        * LDS in blocks of 256 bytes, so if there are 4 bytes lds
 421        * allocated in the shader and 4 bytes allocated by the state
 422        * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
 423        */
 424       if (sctx->chip_class <= GFX6) {
 425          lds_blocks += align(program->local_size, 256) >> 8;
 426       } else {
 427          lds_blocks += align(program->local_size, 512) >> 9;
 428       }
 429
 430       /* TODO: use si_multiwave_lds_size_workaround */
 431       assert(lds_blocks <= 0xFF);
 432
 433       config->rsrc2 &= C_00B84C_LDS_SIZE;
 434       config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
 435    }
 436
 437    if (!si_setup_compute_scratch_buffer(sctx, shader, config))
 438       return false;
 439
 440    if (shader->scratch_bo) {
 441       COMPUTE_DBG(sctx->screen,
 442                   "Waves: %u; Scratch per wave: %u bytes; "
 443                   "Total Scratch: %u bytes\n",
 444                   sctx->scratch_waves, config->scratch_bytes_per_wave,
 445                   config->scratch_bytes_per_wave * sctx->scratch_waves);
 446
 447       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->scratch_bo, RADEON_USAGE_READWRITE,
 448                                 RADEON_PRIO_SCRATCH_BUFFER);
 449    }
 450
 451    /* Prefetch the compute shader to TC L2.
 452     *
 453     * We should also prefetch graphics shaders if a compute dispatch was
 454     * the last command, and the compute shader if a draw call was the last
 455     * command. However, that would add more complexity and we're likely
 456     * to get a shader state change in that case anyway.
 457     */
 458    if (sctx->chip_class >= GFX7) {
 459       cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b, 0, program->shader.bo->b.b.width0);
 460    }
 461
 462    shader_va = shader->bo->gpu_address + offset;
 463    if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
 464       /* Shader code is placed after the amd_kernel_code_t
 465        * struct. */
 466       shader_va += sizeof(amd_kernel_code_t);
 467    }
 468
 469    radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo, RADEON_USAGE_READ,
 470                              RADEON_PRIO_SHADER_BINARY);
 471
 472    radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
 473    radeon_emit(cs, shader_va >> 8);
 474    radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
 475
 476    radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
 477    radeon_emit(cs, config->rsrc1);
 478    radeon_emit(cs, config->rsrc2);
 479
 480    COMPUTE_DBG(sctx->screen,
 481                "COMPUTE_PGM_RSRC1: 0x%08x "
 482                "COMPUTE_PGM_RSRC2: 0x%08x\n",
 483                config->rsrc1, config->rsrc2);
 484
 485    sctx->max_seen_compute_scratch_bytes_per_wave =
 486       MAX2(sctx->max_seen_compute_scratch_bytes_per_wave, config->scratch_bytes_per_wave);
 487
 488    radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
 489                      S_00B860_WAVES(sctx->scratch_waves) |
 490                         S_00B860_WAVESIZE(sctx->max_seen_compute_scratch_bytes_per_wave >> 10));
 491
 492    sctx->cs_shader_state.emitted_program = program;
 493    sctx->cs_shader_state.offset = offset;
 494    sctx->cs_shader_state.uses_scratch = config->scratch_bytes_per_wave != 0;
 495
 496    return true;
 497 }
 498
 499 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
 500                                           const amd_kernel_code_t *code_object, unsigned user_sgpr)
 501 {
 502    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 503    uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
 504
 505    unsigned max_private_element_size =
 506       AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
 507
 508    uint32_t scratch_dword0 = scratch_va & 0xffffffff;
 509    uint32_t scratch_dword1 =
 510       S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) | S_008F04_SWIZZLE_ENABLE(1);
 511
 512    /* Disable address clamping */
 513    uint32_t scratch_dword2 = 0xffffffff;
 514    uint32_t scratch_dword3 = S_008F0C_INDEX_STRIDE(3) | S_008F0C_ADD_TID_ENABLE(1);
 515
 516    if (sctx->chip_class >= GFX9) {
 517       assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
 518    } else {
 519       scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
 520
 521       if (sctx->chip_class < GFX8) {
 522          /* BUF_DATA_FORMAT is ignored, but it cannot be
 523           * BUF_DATA_FORMAT_INVALID. */
 524          scratch_dword3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
 525       }
 526    }
 527
 528    radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 4);
 529    radeon_emit(cs, scratch_dword0);
 530    radeon_emit(cs, scratch_dword1);
 531    radeon_emit(cs, scratch_dword2);
 532    radeon_emit(cs, scratch_dword3);
 533 }
 534
 535 static void si_setup_user_sgprs_co_v2(struct si_context *sctx, const amd_kernel_code_t *code_object,
 536                                       const struct pipe_grid_info *info, uint64_t kernel_args_va)
 537 {
 538    struct si_compute *program = sctx->cs_shader_state.program;
 539    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 540
 541    static const enum amd_code_property_mask_t workgroup_count_masks[] = {
 542       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
 543       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
 544       AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z};
 545
 546    unsigned i, user_sgpr = 0;
 547    if (AMD_HSA_BITS_GET(code_object->code_properties,
 548                         AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
 549       if (code_object->workitem_private_segment_byte_size > 0) {
 550          setup_scratch_rsrc_user_sgprs(sctx, code_object, user_sgpr);
 551       }
 552       user_sgpr += 4;
 553    }
 554
 555    if (AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
 556       struct dispatch_packet dispatch;
 557       unsigned dispatch_offset;
 558       struct si_resource *dispatch_buf = NULL;
 559       uint64_t dispatch_va;
 560
 561       /* Upload dispatch ptr */
 562       memset(&dispatch, 0, sizeof(dispatch));
 563
 564       dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
 565       dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
 566       dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
 567
 568       dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
 569       dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
 570       dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
 571
 572       dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
 573       dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
 574
 575       dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
 576
 577       u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch), 256, &dispatch, &dispatch_offset,
 578                     (struct pipe_resource **)&dispatch_buf);
 579
 580       if (!dispatch_buf) {
 581          fprintf(stderr, "Error: Failed to allocate dispatch "
 582                          "packet.");
 583       }
 584       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf, RADEON_USAGE_READ,
 585                                 RADEON_PRIO_CONST_BUFFER);
 586
 587       dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
 588
 589       radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
 590       radeon_emit(cs, dispatch_va);
 591       radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) | S_008F04_STRIDE(0));
 592
 593       si_resource_reference(&dispatch_buf, NULL);
 594       user_sgpr += 2;
 595    }
 596
 597    if (AMD_HSA_BITS_GET(code_object->code_properties,
 598                         AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
 599       radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
 600       radeon_emit(cs, kernel_args_va);
 601       radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(kernel_args_va >> 32) | S_008F04_STRIDE(0));
 602       user_sgpr += 2;
 603    }
 604
 605    for (i = 0; i < 3 && user_sgpr < 16; i++) {
 606       if (code_object->code_properties & workgroup_count_masks[i]) {
 607          radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 1);
 608          radeon_emit(cs, info->grid[i]);
 609          user_sgpr += 1;
 610       }
 611    }
 612 }
 613
 614 static bool si_upload_compute_input(struct si_context *sctx, const amd_kernel_code_t *code_object,
 615                                     const struct pipe_grid_info *info)
 616 {
 617    struct si_compute *program = sctx->cs_shader_state.program;
 618    struct si_resource *input_buffer = NULL;
 619    uint32_t kernel_args_offset = 0;
 620    uint32_t *kernel_args;
 621    void *kernel_args_ptr;
 622    uint64_t kernel_args_va;
 623
 624    u_upload_alloc(sctx->b.const_uploader, 0, program->input_size,
 625                   sctx->screen->info.tcc_cache_line_size, &kernel_args_offset,
 626                   (struct pipe_resource **)&input_buffer, &kernel_args_ptr);
 627
 628    if (unlikely(!kernel_args_ptr))
 629       return false;
 630
 631    kernel_args = (uint32_t *)kernel_args_ptr;
 632    kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
 633
 634    memcpy(kernel_args, info->input, program->input_size);
 635
 636    for (unsigned i = 0; i < program->input_size / 4; i++) {
 637       COMPUTE_DBG(sctx->screen, "input %u : %u\n", i, kernel_args[i]);
 638    }
 639
 640    radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer, RADEON_USAGE_READ,
 641                              RADEON_PRIO_CONST_BUFFER);
 642
 643    si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
 644    si_resource_reference(&input_buffer, NULL);
 645    return true;
 646 }
 647
 648 static void si_setup_nir_user_data(struct si_context *sctx, const struct pipe_grid_info *info)
 649 {
 650    struct si_compute *program = sctx->cs_shader_state.program;
 651    struct si_shader_selector *sel = &program->sel;
 652    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 653    unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 + 4 * SI_NUM_RESOURCE_SGPRS;
 654    unsigned block_size_reg = grid_size_reg +
 655                              /* 12 bytes = 3 dwords. */
 656                              12 * sel->info.uses_grid_size;
 657    unsigned cs_user_data_reg = block_size_reg + 12 * program->reads_variable_block_size;
 658
 659    if (info->indirect) {
 660       if (sel->info.uses_grid_size) {
 661          for (unsigned i = 0; i < 3; ++i) {
 662             si_cp_copy_data(sctx, sctx->gfx_cs, COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
 663                             COPY_DATA_SRC_MEM, si_resource(info->indirect),
 664                             info->indirect_offset + 4 * i);
 665          }
 666       }
 667    } else {
 668       if (sel->info.uses_grid_size) {
 669          radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
 670          radeon_emit(cs, info->grid[0]);
 671          radeon_emit(cs, info->grid[1]);
 672          radeon_emit(cs, info->grid[2]);
 673       }
 674       if (program->reads_variable_block_size) {
 675          radeon_set_sh_reg_seq(cs, block_size_reg, 3);
 676          radeon_emit(cs, info->block[0]);
 677          radeon_emit(cs, info->block[1]);
 678          radeon_emit(cs, info->block[2]);
 679       }
 680    }
 681
 682    if (program->num_cs_user_data_dwords) {
 683       radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
 684       radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
 685    }
 686 }
 687
 688 static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_grid_info *info)
 689 {
 690    struct si_screen *sscreen = sctx->screen;
 691    struct radeon_cmdbuf *cs = sctx->gfx_cs;
 692    bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
 693    unsigned threads_per_threadgroup = info->block[0] * info->block[1] * info->block[2];
 694    unsigned waves_per_threadgroup =
 695       DIV_ROUND_UP(threads_per_threadgroup, sscreen->compute_wave_size);
 696    unsigned threadgroups_per_cu = 1;
 697
 698    if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1)
 699       threadgroups_per_cu = 2;
 700
 701    radeon_set_sh_reg(
 702       cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
 703       ac_get_compute_resource_limits(&sscreen->info, waves_per_threadgroup,
 704                                      sctx->cs_max_waves_per_sh, threadgroups_per_cu));
 705
 706    unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) | S_00B800_FORCE_START_AT_000(1) |
 707                                  /* If the KMD allows it (there is a KMD hw register for it),
 708                                   * allow launching waves out-of-order. (same as Vulkan) */
 709                                  S_00B800_ORDER_MODE(sctx->chip_class >= GFX7) |
 710                                  S_00B800_CS_W32_EN(sscreen->compute_wave_size == 32);
 711
 712    const uint *last_block = info->last_block;
 713    bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
 714
 715    radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
 716
 717    if (partial_block_en) {
 718       unsigned partial[3];
 719
 720       /* If no partial_block, these should be an entire block size, not 0. */
 721       partial[0] = last_block[0] ? last_block[0] : info->block[0];
 722       partial[1] = last_block[1] ? last_block[1] : info->block[1];
 723       partial[2] = last_block[2] ? last_block[2] : info->block[2];
 724
 725       radeon_emit(
 726          cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) | S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
 727       radeon_emit(
 728          cs, S_00B820_NUM_THREAD_FULL(info->block[1]) | S_00B820_NUM_THREAD_PARTIAL(partial[1]));
 729       radeon_emit(
 730          cs, S_00B824_NUM_THREAD_FULL(info->block[2]) | S_00B824_NUM_THREAD_PARTIAL(partial[2]));
 731
 732       dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
 733    } else {
 734       radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
 735       radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
 736       radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
 737    }
 738
 739    if (info->indirect) {
 740       uint64_t base_va = si_resource(info->indirect)->gpu_address;
 741
 742       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(info->indirect), RADEON_USAGE_READ,
 743                                 RADEON_PRIO_DRAW_INDIRECT);
 744
 745       radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) | PKT3_SHADER_TYPE_S(1));
 746       radeon_emit(cs, 1);
 747       radeon_emit(cs, base_va);
 748       radeon_emit(cs, base_va >> 32);
 749
 750       radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
 751       radeon_emit(cs, info->indirect_offset);
 752       radeon_emit(cs, dispatch_initiator);
 753    } else {
 754       radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
 755       radeon_emit(cs, info->grid[0]);
 756       radeon_emit(cs, info->grid[1]);
 757       radeon_emit(cs, info->grid[2]);
 758       radeon_emit(cs, dispatch_initiator);
 759    }
 760 }
 761
 762 static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
 763 {
 764    struct si_context *sctx = (struct si_context *)ctx;
 765    struct si_compute *program = sctx->cs_shader_state.program;
 766    const amd_kernel_code_t *code_object = si_compute_get_code_object(program, info->pc);
 767    int i;
 768    /* HW bug workaround when CS threadgroups > 256 threads and async
 769     * compute isn't used, i.e. only one compute job can run at a time.
 770     * If async compute is possible, the threadgroup size must be limited
 771     * to 256 threads on all queues to avoid the bug.
 772     * Only GFX6 and certain GFX7 chips are affected.
 773     */
 774    bool cs_regalloc_hang =
 775       (sctx->chip_class == GFX6 || sctx->family == CHIP_BONAIRE || sctx->family == CHIP_KABINI) &&
 776       info->block[0] * info->block[1] * info->block[2] > 256;
 777
 778    if (cs_regalloc_hang)
 779       sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH;
 780
 781    if (program->ir_type != PIPE_SHADER_IR_NATIVE && program->shader.compilation_failed)
 782       return;
 783
 784    if (sctx->has_graphics) {
 785       if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
 786          si_update_fb_dirtiness_after_rendering(sctx);
 787          sctx->last_num_draw_calls = sctx->num_draw_calls;
 788       }
 789
 790       si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
 791    }
 792
 793    /* Add buffer sizes for memory checking in need_cs_space. */
 794    si_context_add_resource_size(sctx, &program->shader.bo->b.b);
 795    /* TODO: add the scratch buffer */
 796
 797    if (info->indirect) {
 798       si_context_add_resource_size(sctx, info->indirect);
 799
 800       /* Indirect buffers use TC L2 on GFX9, but not older hw. */
 801       if (sctx->chip_class <= GFX8 && si_resource(info->indirect)->TC_L2_dirty) {
 802          sctx->flags |= SI_CONTEXT_WB_L2;
 803          si_resource(info->indirect)->TC_L2_dirty = false;
 804       }
 805    }
 806
 807    si_need_gfx_cs_space(sctx);
 808
 809    /* If we're using a secure context, determine if cs must be secure or not */
 810    if (unlikely(sctx->ws->ws_is_secure(sctx->ws))) {
 811       bool secure = si_compute_resources_check_encrypted(sctx);
 812       if (secure != sctx->ws->cs_is_secure(sctx->gfx_cs)) {
 813          si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
 814          sctx->ws->cs_set_secure(sctx->gfx_cs, secure);
 815       }
 816    }
 817
 818    if (sctx->bo_list_add_all_compute_resources)
 819       si_compute_resources_add_all_to_bo_list(sctx);
 820
 821    if (!sctx->cs_shader_state.initialized) {
 822       si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
 823
 824       sctx->cs_shader_state.emitted_program = NULL;
 825       sctx->cs_shader_state.initialized = true;
 826    }
 827
 828    if (sctx->flags)
 829       sctx->emit_cache_flush(sctx);
 830
 831    if (!si_switch_compute_shader(sctx, program, &program->shader, code_object, info->pc))
 832       return;
 833
 834    si_upload_compute_shader_descriptors(sctx);
 835    si_emit_compute_shader_pointers(sctx);
 836
 837    if (sctx->has_graphics && si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
 838       sctx->atoms.s.render_cond.emit(sctx);
 839       si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
 840    }
 841
 842    if (program->ir_type == PIPE_SHADER_IR_NATIVE &&
 843        unlikely(!si_upload_compute_input(sctx, code_object, info)))
 844       return;
 845
 846    /* Global buffers */
 847    for (i = 0; i < program->max_global_buffers; i++) {
 848       struct si_resource *buffer = si_resource(program->global_buffers[i]);
 849       if (!buffer) {
 850          continue;
 851       }
 852       radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer, RADEON_USAGE_READWRITE,
 853                                 RADEON_PRIO_COMPUTE_GLOBAL);
 854    }
 855
 856    if (program->ir_type != PIPE_SHADER_IR_NATIVE)
 857       si_setup_nir_user_data(sctx, info);
 858
 859    si_emit_dispatch_packets(sctx, info);
 860
 861    if (unlikely(sctx->current_saved_cs)) {
 862       si_trace_emit(sctx);
 863       si_log_compute_state(sctx, sctx->log);
 864    }
 865
 866    sctx->compute_is_busy = true;
 867    sctx->num_compute_calls++;
 868    if (sctx->cs_shader_state.uses_scratch)
 869       sctx->num_spill_compute_calls++;
 870
 871    if (cs_regalloc_hang)
 872       sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
 873 }
 874
 875 void si_destroy_compute(struct si_compute *program)
 876 {
 877    struct si_shader_selector *sel = &program->sel;
 878
 879    if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
 880       util_queue_drop_job(&sel->screen->shader_compiler_queue, &sel->ready);
 881       util_queue_fence_destroy(&sel->ready);
 882    }
 883
 884    for (unsigned i = 0; i < program->max_global_buffers; i++)
 885       pipe_resource_reference(&program->global_buffers[i], NULL);
 886    FREE(program->global_buffers);
 887
 888    si_shader_destroy(&program->shader);
 889    ralloc_free(program->sel.nir);
 890    FREE(program);
 891 }
 892
 893 static void si_delete_compute_state(struct pipe_context *ctx, void *state)
 894 {
 895    struct si_compute *program = (struct si_compute *)state;
 896    struct si_context *sctx = (struct si_context *)ctx;
 897
 898    if (!state)
 899       return;
 900
 901    if (program == sctx->cs_shader_state.program)
 902       sctx->cs_shader_state.program = NULL;
 903
 904    if (program == sctx->cs_shader_state.emitted_program)
 905       sctx->cs_shader_state.emitted_program = NULL;
 906
 907    si_compute_reference(&program, NULL);
 908 }
 909
 910 static void si_set_compute_resources(struct pipe_context *ctx_, unsigned start, unsigned count,
 911                                      struct pipe_surface **surfaces)
 912 {
 913 }
 914
 915 void si_init_compute_functions(struct si_context *sctx)
 916 {
 917    sctx->b.create_compute_state = si_create_compute_state;
 918    sctx->b.delete_compute_state = si_delete_compute_state;
 919    sctx->b.bind_compute_state = si_bind_compute_state;
 920    sctx->b.set_compute_resources = si_set_compute_resources;
 921    sctx->b.set_global_binding = si_set_global_binding;
 922    sctx->b.launch_grid = si_launch_grid;
 923 }