radeonsi/nir: call radeonsi nir opts before the scan pass
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "tgsi/tgsi_parse.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30
31 #include "amd_kernel_code_t.h"
32 #include "si_build_pm4.h"
33 #include "si_compute.h"
34
35 #define COMPUTE_DBG(sscreen, fmt, args...) \
36 do { \
37 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
38 } while (0);
39
40 struct dispatch_packet {
41 uint16_t header;
42 uint16_t setup;
43 uint16_t workgroup_size_x;
44 uint16_t workgroup_size_y;
45 uint16_t workgroup_size_z;
46 uint16_t reserved0;
47 uint32_t grid_size_x;
48 uint32_t grid_size_y;
49 uint32_t grid_size_z;
50 uint32_t private_segment_size;
51 uint32_t group_segment_size;
52 uint64_t kernel_object;
53 uint64_t kernarg_address;
54 uint64_t reserved2;
55 };
56
57 static const amd_kernel_code_t *si_compute_get_code_object(
58 const struct si_compute *program,
59 uint64_t symbol_offset)
60 {
61 if (!program->use_code_object_v2) {
62 return NULL;
63 }
64 return (const amd_kernel_code_t*)
65 (program->shader.binary.code + symbol_offset);
66 }
67
68 static void code_object_to_config(const amd_kernel_code_t *code_object,
69 struct si_shader_config *out_config) {
70
71 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
72 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
73 out_config->num_sgprs = code_object->wavefront_sgpr_count;
74 out_config->num_vgprs = code_object->workitem_vgpr_count;
75 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
76 out_config->rsrc1 = rsrc1;
77 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
78 out_config->rsrc2 = rsrc2;
79 out_config->scratch_bytes_per_wave =
80 align(code_object->workitem_private_segment_byte_size * 64, 1024);
81 }
82
83 /* Asynchronous compute shader compilation. */
84 static void si_create_compute_state_async(void *job, int thread_index)
85 {
86 struct si_compute *program = (struct si_compute *)job;
87 struct si_shader *shader = &program->shader;
88 struct si_shader_selector sel;
89 struct ac_llvm_compiler *compiler;
90 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
91 struct si_screen *sscreen = program->screen;
92
93 assert(!debug->debug_message || debug->async);
94 assert(thread_index >= 0);
95 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
96 compiler = &sscreen->compiler[thread_index];
97
98 memset(&sel, 0, sizeof(sel));
99
100 sel.screen = sscreen;
101
102 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
103 tgsi_scan_shader(program->ir.tgsi, &sel.info);
104 sel.tokens = program->ir.tgsi;
105 } else {
106 assert(program->ir_type == PIPE_SHADER_IR_NIR);
107 sel.nir = program->ir.nir;
108
109 si_nir_opts(sel.nir);
110 si_nir_scan_shader(sel.nir, &sel.info);
111 si_lower_nir(&sel);
112 }
113
114 /* Store the declared LDS size into tgsi_shader_info for the shader
115 * cache to include it.
116 */
117 sel.info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
118
119 sel.type = PIPE_SHADER_COMPUTE;
120 si_get_active_slot_masks(&sel.info,
121 &program->active_const_and_shader_buffers,
122 &program->active_samplers_and_images);
123
124 program->shader.selector = &sel;
125 program->shader.is_monolithic = true;
126 program->uses_grid_size = sel.info.uses_grid_size;
127 program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
128 program->uses_bindless_images = sel.info.uses_bindless_images;
129 program->reads_variable_block_size =
130 sel.info.uses_block_size &&
131 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
132 program->num_cs_user_data_dwords =
133 sel.info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
134
135 void *ir_binary = si_get_ir_binary(&sel);
136
137 /* Try to load the shader from the shader cache. */
138 mtx_lock(&sscreen->shader_cache_mutex);
139
140 if (ir_binary &&
141 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
142 mtx_unlock(&sscreen->shader_cache_mutex);
143
144 si_shader_dump_stats_for_shader_db(shader, debug);
145 si_shader_dump(sscreen, shader, debug, PIPE_SHADER_COMPUTE,
146 stderr, true);
147
148 if (si_shader_binary_upload(sscreen, shader))
149 program->shader.compilation_failed = true;
150 } else {
151 mtx_unlock(&sscreen->shader_cache_mutex);
152
153 if (si_shader_create(sscreen, compiler, &program->shader, debug)) {
154 program->shader.compilation_failed = true;
155
156 if (program->ir_type == PIPE_SHADER_IR_TGSI)
157 FREE(program->ir.tgsi);
158 program->shader.selector = NULL;
159 return;
160 }
161
162 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
163 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
164 (sel.info.uses_grid_size ? 3 : 0) +
165 (program->reads_variable_block_size ? 3 : 0) +
166 program->num_cs_user_data_dwords;
167
168 shader->config.rsrc1 =
169 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
170 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
171 S_00B848_DX10_CLAMP(1) |
172 S_00B848_FLOAT_MODE(shader->config.float_mode);
173
174 shader->config.rsrc2 =
175 S_00B84C_USER_SGPR(user_sgprs) |
176 S_00B84C_SCRATCH_EN(scratch_enabled) |
177 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
178 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
179 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
180 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
181 sel.info.uses_thread_id[1] ? 1 : 0) |
182 S_00B84C_LDS_SIZE(shader->config.lds_size);
183
184 if (ir_binary) {
185 mtx_lock(&sscreen->shader_cache_mutex);
186 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
187 FREE(ir_binary);
188 mtx_unlock(&sscreen->shader_cache_mutex);
189 }
190 }
191
192 if (program->ir_type == PIPE_SHADER_IR_TGSI)
193 FREE(program->ir.tgsi);
194
195 program->shader.selector = NULL;
196 }
197
198 static void *si_create_compute_state(
199 struct pipe_context *ctx,
200 const struct pipe_compute_state *cso)
201 {
202 struct si_context *sctx = (struct si_context *)ctx;
203 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
204 struct si_compute *program = CALLOC_STRUCT(si_compute);
205
206 pipe_reference_init(&program->reference, 1);
207 program->screen = (struct si_screen *)ctx->screen;
208 program->ir_type = cso->ir_type;
209 program->local_size = cso->req_local_mem;
210 program->private_size = cso->req_private_mem;
211 program->input_size = cso->req_input_mem;
212 program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
213
214 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
215 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
216 program->ir.tgsi = tgsi_dup_tokens(cso->prog);
217 if (!program->ir.tgsi) {
218 FREE(program);
219 return NULL;
220 }
221 } else {
222 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
223 program->ir.nir = (struct nir_shader *) cso->prog;
224 }
225
226 program->compiler_ctx_state.debug = sctx->debug;
227 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
228 p_atomic_inc(&sscreen->num_shaders_created);
229
230 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
231 &program->ready,
232 &program->compiler_ctx_state,
233 program, si_create_compute_state_async);
234 } else {
235 const struct pipe_llvm_program_header *header;
236 const char *code;
237 header = cso->prog;
238 code = cso->prog + sizeof(struct pipe_llvm_program_header);
239
240 ac_elf_read(code, header->num_bytes, &program->shader.binary);
241 if (program->use_code_object_v2) {
242 const amd_kernel_code_t *code_object =
243 si_compute_get_code_object(program, 0);
244 code_object_to_config(code_object, &program->shader.config);
245 if (program->shader.binary.reloc_count != 0) {
246 fprintf(stderr, "Error: %d unsupported relocations\n",
247 program->shader.binary.reloc_count);
248 FREE(program);
249 return NULL;
250 }
251 } else {
252 si_shader_binary_read_config(&program->shader.binary,
253 &program->shader.config, 0);
254 }
255 si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
256 PIPE_SHADER_COMPUTE, stderr, true);
257 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
258 fprintf(stderr, "LLVM failed to upload shader\n");
259 FREE(program);
260 return NULL;
261 }
262 }
263
264 return program;
265 }
266
267 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
268 {
269 struct si_context *sctx = (struct si_context*)ctx;
270 struct si_compute *program = (struct si_compute*)state;
271
272 sctx->cs_shader_state.program = program;
273 if (!program)
274 return;
275
276 /* Wait because we need active slot usage masks. */
277 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
278 util_queue_fence_wait(&program->ready);
279
280 si_set_active_descriptors(sctx,
281 SI_DESCS_FIRST_COMPUTE +
282 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
283 program->active_const_and_shader_buffers);
284 si_set_active_descriptors(sctx,
285 SI_DESCS_FIRST_COMPUTE +
286 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
287 program->active_samplers_and_images);
288 }
289
290 static void si_set_global_binding(
291 struct pipe_context *ctx, unsigned first, unsigned n,
292 struct pipe_resource **resources,
293 uint32_t **handles)
294 {
295 unsigned i;
296 struct si_context *sctx = (struct si_context*)ctx;
297 struct si_compute *program = sctx->cs_shader_state.program;
298
299 assert(first + n <= MAX_GLOBAL_BUFFERS);
300
301 if (!resources) {
302 for (i = 0; i < n; i++) {
303 pipe_resource_reference(&program->global_buffers[first + i], NULL);
304 }
305 return;
306 }
307
308 for (i = 0; i < n; i++) {
309 uint64_t va;
310 uint32_t offset;
311 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
312 va = si_resource(resources[i])->gpu_address;
313 offset = util_le32_to_cpu(*handles[i]);
314 va += offset;
315 va = util_cpu_to_le64(va);
316 memcpy(handles[i], &va, sizeof(va));
317 }
318 }
319
320 static void si_initialize_compute(struct si_context *sctx)
321 {
322 struct radeon_cmdbuf *cs = sctx->gfx_cs;
323 uint64_t bc_va;
324
325 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
326 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
327 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
328 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
329
330 if (sctx->chip_class >= CIK) {
331 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
332 radeon_set_sh_reg_seq(cs,
333 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
334 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
335 S_00B864_SH1_CU_EN(0xffff));
336 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
337 S_00B868_SH1_CU_EN(0xffff));
338 }
339
340 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
341 * and is now per pipe, so it should be handled in the
342 * kernel if we want to use something other than the default value,
343 * which is now 0x22f.
344 */
345 if (sctx->chip_class <= SI) {
346 /* XXX: This should be:
347 * (number of compute units) * 4 * (waves per simd) - 1 */
348
349 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
350 0x190 /* Default value */);
351 }
352
353 /* Set the pointer to border colors. */
354 bc_va = sctx->border_color_buffer->gpu_address;
355
356 if (sctx->chip_class >= CIK) {
357 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
358 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
359 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
360 } else {
361 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
362 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
363 bc_va >> 8);
364 }
365 }
366
367 sctx->cs_shader_state.emitted_program = NULL;
368 sctx->cs_shader_state.initialized = true;
369 }
370
371 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
372 struct si_shader *shader,
373 struct si_shader_config *config)
374 {
375 uint64_t scratch_bo_size, scratch_needed;
376 scratch_bo_size = 0;
377 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
378 if (sctx->compute_scratch_buffer)
379 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
380
381 if (scratch_bo_size < scratch_needed) {
382 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
383
384 sctx->compute_scratch_buffer =
385 si_aligned_buffer_create(&sctx->screen->b,
386 SI_RESOURCE_FLAG_UNMAPPABLE,
387 PIPE_USAGE_DEFAULT,
388 scratch_needed, 256);
389
390 if (!sctx->compute_scratch_buffer)
391 return false;
392 }
393
394 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
395 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
396
397 si_shader_apply_scratch_relocs(shader, scratch_va);
398
399 if (si_shader_binary_upload(sctx->screen, shader))
400 return false;
401
402 si_resource_reference(&shader->scratch_bo,
403 sctx->compute_scratch_buffer);
404 }
405
406 return true;
407 }
408
409 static bool si_switch_compute_shader(struct si_context *sctx,
410 struct si_compute *program,
411 struct si_shader *shader,
412 const amd_kernel_code_t *code_object,
413 unsigned offset)
414 {
415 struct radeon_cmdbuf *cs = sctx->gfx_cs;
416 struct si_shader_config inline_config = {0};
417 struct si_shader_config *config;
418 uint64_t shader_va;
419
420 if (sctx->cs_shader_state.emitted_program == program &&
421 sctx->cs_shader_state.offset == offset)
422 return true;
423
424 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
425 config = &shader->config;
426 } else {
427 unsigned lds_blocks;
428
429 config = &inline_config;
430 if (code_object) {
431 code_object_to_config(code_object, config);
432 } else {
433 si_shader_binary_read_config(&shader->binary, config, offset);
434 }
435
436 lds_blocks = config->lds_size;
437 /* XXX: We are over allocating LDS. For SI, the shader reports
438 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
439 * allocated in the shader and 4 bytes allocated by the state
440 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
441 */
442 if (sctx->chip_class <= SI) {
443 lds_blocks += align(program->local_size, 256) >> 8;
444 } else {
445 lds_blocks += align(program->local_size, 512) >> 9;
446 }
447
448 /* TODO: use si_multiwave_lds_size_workaround */
449 assert(lds_blocks <= 0xFF);
450
451 config->rsrc2 &= C_00B84C_LDS_SIZE;
452 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
453 }
454
455 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
456 return false;
457
458 if (shader->scratch_bo) {
459 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
460 "Total Scratch: %u bytes\n", sctx->scratch_waves,
461 config->scratch_bytes_per_wave,
462 config->scratch_bytes_per_wave *
463 sctx->scratch_waves);
464
465 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
466 shader->scratch_bo, RADEON_USAGE_READWRITE,
467 RADEON_PRIO_SCRATCH_BUFFER);
468 }
469
470 /* Prefetch the compute shader to TC L2.
471 *
472 * We should also prefetch graphics shaders if a compute dispatch was
473 * the last command, and the compute shader if a draw call was the last
474 * command. However, that would add more complexity and we're likely
475 * to get a shader state change in that case anyway.
476 */
477 if (sctx->chip_class >= CIK) {
478 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
479 0, program->shader.bo->b.b.width0);
480 }
481
482 shader_va = shader->bo->gpu_address + offset;
483 if (program->use_code_object_v2) {
484 /* Shader code is placed after the amd_kernel_code_t
485 * struct. */
486 shader_va += sizeof(amd_kernel_code_t);
487 }
488
489 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
490 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
491
492 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
493 radeon_emit(cs, shader_va >> 8);
494 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
495
496 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
497 radeon_emit(cs, config->rsrc1);
498 radeon_emit(cs, config->rsrc2);
499
500 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
501 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
502
503 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
504 S_00B860_WAVES(sctx->scratch_waves)
505 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
506
507 sctx->cs_shader_state.emitted_program = program;
508 sctx->cs_shader_state.offset = offset;
509 sctx->cs_shader_state.uses_scratch =
510 config->scratch_bytes_per_wave != 0;
511
512 return true;
513 }
514
515 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
516 const amd_kernel_code_t *code_object,
517 unsigned user_sgpr)
518 {
519 struct radeon_cmdbuf *cs = sctx->gfx_cs;
520 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
521
522 unsigned max_private_element_size = AMD_HSA_BITS_GET(
523 code_object->code_properties,
524 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
525
526 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
527 uint32_t scratch_dword1 =
528 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
529 S_008F04_SWIZZLE_ENABLE(1);
530
531 /* Disable address clamping */
532 uint32_t scratch_dword2 = 0xffffffff;
533 uint32_t scratch_dword3 =
534 S_008F0C_INDEX_STRIDE(3) |
535 S_008F0C_ADD_TID_ENABLE(1);
536
537 if (sctx->chip_class >= GFX9) {
538 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
539 } else {
540 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
541
542 if (sctx->chip_class < VI) {
543 /* BUF_DATA_FORMAT is ignored, but it cannot be
544 * BUF_DATA_FORMAT_INVALID. */
545 scratch_dword3 |=
546 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
547 }
548 }
549
550 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
551 (user_sgpr * 4), 4);
552 radeon_emit(cs, scratch_dword0);
553 radeon_emit(cs, scratch_dword1);
554 radeon_emit(cs, scratch_dword2);
555 radeon_emit(cs, scratch_dword3);
556 }
557
558 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
559 const amd_kernel_code_t *code_object,
560 const struct pipe_grid_info *info,
561 uint64_t kernel_args_va)
562 {
563 struct si_compute *program = sctx->cs_shader_state.program;
564 struct radeon_cmdbuf *cs = sctx->gfx_cs;
565
566 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
567 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
568 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
569 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
570 };
571
572 unsigned i, user_sgpr = 0;
573 if (AMD_HSA_BITS_GET(code_object->code_properties,
574 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
575 if (code_object->workitem_private_segment_byte_size > 0) {
576 setup_scratch_rsrc_user_sgprs(sctx, code_object,
577 user_sgpr);
578 }
579 user_sgpr += 4;
580 }
581
582 if (AMD_HSA_BITS_GET(code_object->code_properties,
583 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
584 struct dispatch_packet dispatch;
585 unsigned dispatch_offset;
586 struct si_resource *dispatch_buf = NULL;
587 uint64_t dispatch_va;
588
589 /* Upload dispatch ptr */
590 memset(&dispatch, 0, sizeof(dispatch));
591
592 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
593 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
594 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
595
596 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
597 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
598 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
599
600 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
601 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
602
603 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
604
605 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
606 256, &dispatch, &dispatch_offset,
607 (struct pipe_resource**)&dispatch_buf);
608
609 if (!dispatch_buf) {
610 fprintf(stderr, "Error: Failed to allocate dispatch "
611 "packet.");
612 }
613 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
614 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
615
616 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
617
618 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
619 (user_sgpr * 4), 2);
620 radeon_emit(cs, dispatch_va);
621 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
622 S_008F04_STRIDE(0));
623
624 si_resource_reference(&dispatch_buf, NULL);
625 user_sgpr += 2;
626 }
627
628 if (AMD_HSA_BITS_GET(code_object->code_properties,
629 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
630 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
631 (user_sgpr * 4), 2);
632 radeon_emit(cs, kernel_args_va);
633 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
634 S_008F04_STRIDE(0));
635 user_sgpr += 2;
636 }
637
638 for (i = 0; i < 3 && user_sgpr < 16; i++) {
639 if (code_object->code_properties & workgroup_count_masks[i]) {
640 radeon_set_sh_reg_seq(cs,
641 R_00B900_COMPUTE_USER_DATA_0 +
642 (user_sgpr * 4), 1);
643 radeon_emit(cs, info->grid[i]);
644 user_sgpr += 1;
645 }
646 }
647 }
648
649 static bool si_upload_compute_input(struct si_context *sctx,
650 const amd_kernel_code_t *code_object,
651 const struct pipe_grid_info *info)
652 {
653 struct radeon_cmdbuf *cs = sctx->gfx_cs;
654 struct si_compute *program = sctx->cs_shader_state.program;
655 struct si_resource *input_buffer = NULL;
656 unsigned kernel_args_size;
657 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
658 uint32_t kernel_args_offset = 0;
659 uint32_t *kernel_args;
660 void *kernel_args_ptr;
661 uint64_t kernel_args_va;
662 unsigned i;
663
664 /* The extra num_work_size_bytes are for work group / work item size information */
665 kernel_args_size = program->input_size + num_work_size_bytes;
666
667 u_upload_alloc(sctx->b.const_uploader, 0, kernel_args_size,
668 sctx->screen->info.tcc_cache_line_size,
669 &kernel_args_offset,
670 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
671
672 if (unlikely(!kernel_args_ptr))
673 return false;
674
675 kernel_args = (uint32_t*)kernel_args_ptr;
676 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
677
678 if (!code_object) {
679 for (i = 0; i < 3; i++) {
680 kernel_args[i] = util_cpu_to_le32(info->grid[i]);
681 kernel_args[i + 3] = util_cpu_to_le32(info->grid[i] * info->block[i]);
682 kernel_args[i + 6] = util_cpu_to_le32(info->block[i]);
683 }
684 }
685
686 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
687 program->input_size);
688
689
690 for (i = 0; i < (kernel_args_size / 4); i++) {
691 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
692 kernel_args[i]);
693 }
694
695
696 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
697 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
698
699 if (code_object) {
700 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
701 } else {
702 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
703 radeon_emit(cs, kernel_args_va);
704 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
705 S_008F04_STRIDE(0));
706 }
707
708 si_resource_reference(&input_buffer, NULL);
709
710 return true;
711 }
712
713 static void si_setup_tgsi_user_data(struct si_context *sctx,
714 const struct pipe_grid_info *info)
715 {
716 struct si_compute *program = sctx->cs_shader_state.program;
717 struct radeon_cmdbuf *cs = sctx->gfx_cs;
718 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
719 4 * SI_NUM_RESOURCE_SGPRS;
720 unsigned block_size_reg = grid_size_reg +
721 /* 12 bytes = 3 dwords. */
722 12 * program->uses_grid_size;
723 unsigned cs_user_data_reg = block_size_reg +
724 12 * program->reads_variable_block_size;
725
726 if (info->indirect) {
727 if (program->uses_grid_size) {
728 for (unsigned i = 0; i < 3; ++i) {
729 si_cp_copy_data(sctx,
730 COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
731 COPY_DATA_SRC_MEM, si_resource(info->indirect),
732 info->indirect_offset + 4 * i);
733 }
734 }
735 } else {
736 if (program->uses_grid_size) {
737 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
738 radeon_emit(cs, info->grid[0]);
739 radeon_emit(cs, info->grid[1]);
740 radeon_emit(cs, info->grid[2]);
741 }
742 if (program->reads_variable_block_size) {
743 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
744 radeon_emit(cs, info->block[0]);
745 radeon_emit(cs, info->block[1]);
746 radeon_emit(cs, info->block[2]);
747 }
748 }
749
750 if (program->num_cs_user_data_dwords) {
751 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
752 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
753 }
754 }
755
756 static void si_emit_dispatch_packets(struct si_context *sctx,
757 const struct pipe_grid_info *info)
758 {
759 struct si_screen *sscreen = sctx->screen;
760 struct radeon_cmdbuf *cs = sctx->gfx_cs;
761 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
762 unsigned waves_per_threadgroup =
763 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
764 unsigned compute_resource_limits =
765 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
766
767 if (sctx->chip_class >= CIK) {
768 unsigned num_cu_per_se = sscreen->info.num_good_compute_units /
769 sscreen->info.max_se;
770
771 /* Force even distribution on all SIMDs in CU if the workgroup
772 * size is 64. This has shown some good improvements if # of CUs
773 * per SE is not a multiple of 4.
774 */
775 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
776 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
777
778 compute_resource_limits |= S_00B854_WAVES_PER_SH(sctx->cs_max_waves_per_sh);
779 } else {
780 /* SI */
781 if (sctx->cs_max_waves_per_sh) {
782 unsigned limit_div16 = DIV_ROUND_UP(sctx->cs_max_waves_per_sh, 16);
783 compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
784 }
785 }
786
787 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
788 compute_resource_limits);
789
790 unsigned dispatch_initiator =
791 S_00B800_COMPUTE_SHADER_EN(1) |
792 S_00B800_FORCE_START_AT_000(1) |
793 /* If the KMD allows it (there is a KMD hw register for it),
794 * allow launching waves out-of-order. (same as Vulkan) */
795 S_00B800_ORDER_MODE(sctx->chip_class >= CIK);
796
797 const uint *last_block = info->last_block;
798 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
799
800 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
801
802 if (partial_block_en) {
803 unsigned partial[3];
804
805 /* If no partial_block, these should be an entire block size, not 0. */
806 partial[0] = last_block[0] ? last_block[0] : info->block[0];
807 partial[1] = last_block[1] ? last_block[1] : info->block[1];
808 partial[2] = last_block[2] ? last_block[2] : info->block[2];
809
810 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
811 S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
812 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
813 S_00B820_NUM_THREAD_PARTIAL(partial[1]));
814 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
815 S_00B824_NUM_THREAD_PARTIAL(partial[2]));
816
817 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
818 } else {
819 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
820 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
821 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
822 }
823
824 if (info->indirect) {
825 uint64_t base_va = si_resource(info->indirect)->gpu_address;
826
827 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
828 si_resource(info->indirect),
829 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
830
831 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
832 PKT3_SHADER_TYPE_S(1));
833 radeon_emit(cs, 1);
834 radeon_emit(cs, base_va);
835 radeon_emit(cs, base_va >> 32);
836
837 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
838 PKT3_SHADER_TYPE_S(1));
839 radeon_emit(cs, info->indirect_offset);
840 radeon_emit(cs, dispatch_initiator);
841 } else {
842 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
843 PKT3_SHADER_TYPE_S(1));
844 radeon_emit(cs, info->grid[0]);
845 radeon_emit(cs, info->grid[1]);
846 radeon_emit(cs, info->grid[2]);
847 radeon_emit(cs, dispatch_initiator);
848 }
849 }
850
851
852 static void si_launch_grid(
853 struct pipe_context *ctx, const struct pipe_grid_info *info)
854 {
855 struct si_context *sctx = (struct si_context*)ctx;
856 struct si_compute *program = sctx->cs_shader_state.program;
857 const amd_kernel_code_t *code_object =
858 si_compute_get_code_object(program, info->pc);
859 int i;
860 /* HW bug workaround when CS threadgroups > 256 threads and async
861 * compute isn't used, i.e. only one compute job can run at a time.
862 * If async compute is possible, the threadgroup size must be limited
863 * to 256 threads on all queues to avoid the bug.
864 * Only SI and certain CIK chips are affected.
865 */
866 bool cs_regalloc_hang =
867 (sctx->chip_class == SI ||
868 sctx->family == CHIP_BONAIRE ||
869 sctx->family == CHIP_KABINI) &&
870 info->block[0] * info->block[1] * info->block[2] > 256;
871
872 if (cs_regalloc_hang)
873 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
874 SI_CONTEXT_CS_PARTIAL_FLUSH;
875
876 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
877 program->shader.compilation_failed)
878 return;
879
880 if (sctx->has_graphics) {
881 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
882 si_update_fb_dirtiness_after_rendering(sctx);
883 sctx->last_num_draw_calls = sctx->num_draw_calls;
884 }
885
886 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
887 }
888
889 /* Add buffer sizes for memory checking in need_cs_space. */
890 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
891 /* TODO: add the scratch buffer */
892
893 if (info->indirect) {
894 si_context_add_resource_size(sctx, info->indirect);
895
896 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
897 if (sctx->chip_class <= VI &&
898 si_resource(info->indirect)->TC_L2_dirty) {
899 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
900 si_resource(info->indirect)->TC_L2_dirty = false;
901 }
902 }
903
904 si_need_gfx_cs_space(sctx);
905
906 if (sctx->bo_list_add_all_compute_resources)
907 si_compute_resources_add_all_to_bo_list(sctx);
908
909 if (!sctx->cs_shader_state.initialized)
910 si_initialize_compute(sctx);
911
912 if (sctx->flags)
913 si_emit_cache_flush(sctx);
914
915 if (!si_switch_compute_shader(sctx, program, &program->shader,
916 code_object, info->pc))
917 return;
918
919 si_upload_compute_shader_descriptors(sctx);
920 si_emit_compute_shader_pointers(sctx);
921
922 if (sctx->has_graphics &&
923 si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
924 sctx->atoms.s.render_cond.emit(sctx);
925 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
926 }
927
928 if ((program->input_size ||
929 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
930 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
931 return;
932 }
933
934 /* Global buffers */
935 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
936 struct si_resource *buffer =
937 si_resource(program->global_buffers[i]);
938 if (!buffer) {
939 continue;
940 }
941 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
942 RADEON_USAGE_READWRITE,
943 RADEON_PRIO_COMPUTE_GLOBAL);
944 }
945
946 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
947 si_setup_tgsi_user_data(sctx, info);
948
949 si_emit_dispatch_packets(sctx, info);
950
951 if (unlikely(sctx->current_saved_cs)) {
952 si_trace_emit(sctx);
953 si_log_compute_state(sctx, sctx->log);
954 }
955
956 sctx->compute_is_busy = true;
957 sctx->num_compute_calls++;
958 if (sctx->cs_shader_state.uses_scratch)
959 sctx->num_spill_compute_calls++;
960
961 if (cs_regalloc_hang)
962 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
963 }
964
965 void si_destroy_compute(struct si_compute *program)
966 {
967 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
968 util_queue_drop_job(&program->screen->shader_compiler_queue,
969 &program->ready);
970 util_queue_fence_destroy(&program->ready);
971 }
972
973 si_shader_destroy(&program->shader);
974 FREE(program);
975 }
976
977 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
978 struct si_compute *program = (struct si_compute *)state;
979 struct si_context *sctx = (struct si_context*)ctx;
980
981 if (!state)
982 return;
983
984 if (program == sctx->cs_shader_state.program)
985 sctx->cs_shader_state.program = NULL;
986
987 if (program == sctx->cs_shader_state.emitted_program)
988 sctx->cs_shader_state.emitted_program = NULL;
989
990 si_compute_reference(&program, NULL);
991 }
992
993 static void si_set_compute_resources(struct pipe_context * ctx_,
994 unsigned start, unsigned count,
995 struct pipe_surface ** surfaces) { }
996
997 void si_init_compute_functions(struct si_context *sctx)
998 {
999 sctx->b.create_compute_state = si_create_compute_state;
1000 sctx->b.delete_compute_state = si_delete_compute_state;
1001 sctx->b.bind_compute_state = si_bind_compute_state;
1002 sctx->b.set_compute_resources = si_set_compute_resources;
1003 sctx->b.set_global_binding = si_set_global_binding;
1004 sctx->b.launch_grid = si_launch_grid;
1005 }