projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium/radeon: use TCC line size as alignment in other places
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
28 #include "radeon/radeon_elf_util.h"
29
30 #include "amd_kernel_code_t.h"
31 #include "radeon/r600_cs.h"
32 #include "si_pipe.h"
33 #include "sid.h"
34
35 #define MAX_GLOBAL_BUFFERS 22
36
37 struct si_compute {
38 unsigned ir_type;
39 unsigned local_size;
40 unsigned private_size;
41 unsigned input_size;
42 struct si_shader shader;
43
44 struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
45 unsigned use_code_object_v2 : 1;
46 unsigned variable_group_size : 1;
47 };
48
49 struct dispatch_packet {
50 uint16_t header;
51 uint16_t setup;
52 uint16_t workgroup_size_x;
53 uint16_t workgroup_size_y;
54 uint16_t workgroup_size_z;
55 uint16_t reserved0;
56 uint32_t grid_size_x;
57 uint32_t grid_size_y;
58 uint32_t grid_size_z;
59 uint32_t private_segment_size;
60 uint32_t group_segment_size;
61 uint64_t kernel_object;
62 uint64_t kernarg_address;
63 uint64_t reserved2;
64 };
65
66 static const amd_kernel_code_t *si_compute_get_code_object(
67 const struct si_compute *program,
68 uint64_t symbol_offset)
69 {
70 if (!program->use_code_object_v2) {
71 return NULL;
72 }
73 return (const amd_kernel_code_t*)
74 (program->shader.binary.code + symbol_offset);
75 }
76
77 static void code_object_to_config(const amd_kernel_code_t *code_object,
78 struct si_shader_config *out_config) {
79
80 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
81 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
82 out_config->num_sgprs = code_object->wavefront_sgpr_count;
83 out_config->num_vgprs = code_object->workitem_vgpr_count;
84 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
85 out_config->rsrc1 = rsrc1;
86 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
87 out_config->rsrc2 = rsrc2;
88 out_config->scratch_bytes_per_wave =
89 align(code_object->workitem_private_segment_byte_size * 64, 1024);
90 }
91
92 static void *si_create_compute_state(
93 struct pipe_context *ctx,
94 const struct pipe_compute_state *cso)
95 {
96 struct si_context *sctx = (struct si_context *)ctx;
97 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
98 struct si_compute *program = CALLOC_STRUCT(si_compute);
99 struct si_shader *shader = &program->shader;
100
101
102 program->ir_type = cso->ir_type;
103 program->local_size = cso->req_local_mem;
104 program->private_size = cso->req_private_mem;
105 program->input_size = cso->req_input_mem;
106 program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
107 cso->ir_type == PIPE_SHADER_IR_NATIVE;
108
109
110 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
111 struct si_shader_selector sel;
112 bool scratch_enabled;
113
114 memset(&sel, 0, sizeof(sel));
115
116 sel.tokens = tgsi_dup_tokens(cso->prog);
117 if (!sel.tokens) {
118 FREE(program);
119 return NULL;
120 }
121
122 tgsi_scan_shader(cso->prog, &sel.info);
123 sel.type = PIPE_SHADER_COMPUTE;
124 sel.local_size = cso->req_local_mem;
125
126 p_atomic_inc(&sscreen->b.num_shaders_created);
127
128 program->shader.selector = &sel;
129 program->shader.is_monolithic = true;
130
131 if (si_shader_create(sscreen, sctx->tm, &program->shader,
132 &sctx->b.debug)) {
133 FREE(sel.tokens);
134 FREE(program);
135 return NULL;
136 }
137
138 scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
139
140 shader->config.rsrc1 =
141 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
142 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
143 S_00B848_DX10_CLAMP(1) |
144 S_00B848_FLOAT_MODE(shader->config.float_mode);
145
146 shader->config.rsrc2 = S_00B84C_USER_SGPR(SI_CS_NUM_USER_SGPR) |
147 S_00B84C_SCRATCH_EN(scratch_enabled) |
148 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
149 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
150 S_00B84C_LDS_SIZE(shader->config.lds_size);
151
152 program->variable_group_size =
153 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
154
155 FREE(sel.tokens);
156 program->shader.selector = NULL;
157 } else {
158 const struct pipe_llvm_program_header *header;
159 const char *code;
160 header = cso->prog;
161 code = cso->prog + sizeof(struct pipe_llvm_program_header);
162
163 radeon_elf_read(code, header->num_bytes, &program->shader.binary);
164 if (program->use_code_object_v2) {
165 const amd_kernel_code_t *code_object =
166 si_compute_get_code_object(program, 0);
167 code_object_to_config(code_object, &program->shader.config);
168 } else {
169 si_shader_binary_read_config(&program->shader.binary,
170 &program->shader.config, 0);
171 }
172 si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
173 PIPE_SHADER_COMPUTE, stderr, true);
174 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
175 fprintf(stderr, "LLVM failed to upload shader\n");
176 FREE(program);
177 return NULL;
178 }
179 }
180
181 return program;
182 }
183
184 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
185 {
186 struct si_context *sctx = (struct si_context*)ctx;
187 sctx->cs_shader_state.program = (struct si_compute*)state;
188 }
189
190 static void si_set_global_binding(
191 struct pipe_context *ctx, unsigned first, unsigned n,
192 struct pipe_resource **resources,
193 uint32_t **handles)
194 {
195 unsigned i;
196 struct si_context *sctx = (struct si_context*)ctx;
197 struct si_compute *program = sctx->cs_shader_state.program;
198
199 assert(first + n <= MAX_GLOBAL_BUFFERS);
200
201 if (!resources) {
202 for (i = 0; i < n; i++) {
203 pipe_resource_reference(&program->global_buffers[first + i], NULL);
204 }
205 return;
206 }
207
208 for (i = 0; i < n; i++) {
209 uint64_t va;
210 uint32_t offset;
211 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
212 va = r600_resource(resources[i])->gpu_address;
213 offset = util_le32_to_cpu(*handles[i]);
214 va += offset;
215 va = util_cpu_to_le64(va);
216 memcpy(handles[i], &va, sizeof(va));
217 }
218 }
219
220 static void si_initialize_compute(struct si_context *sctx)
221 {
222 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
223 uint64_t bc_va;
224
225 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
226 radeon_emit(cs, 0);
227 radeon_emit(cs, 0);
228 radeon_emit(cs, 0);
229
230 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
231 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
232 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
233 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
234
235 if (sctx->b.chip_class >= CIK) {
236 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
237 radeon_set_sh_reg_seq(cs,
238 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
239 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
240 S_00B864_SH1_CU_EN(0xffff));
241 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
242 S_00B868_SH1_CU_EN(0xffff));
243 }
244
245 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
246 * and is now per pipe, so it should be handled in the
247 * kernel if we want to use something other than the default value,
248 * which is now 0x22f.
249 */
250 if (sctx->b.chip_class <= SI) {
251 /* XXX: This should be:
252 * (number of compute units) * 4 * (waves per simd) - 1 */
253
254 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
255 0x190 /* Default value */);
256 }
257
258 /* Set the pointer to border colors. */
259 bc_va = sctx->border_color_buffer->gpu_address;
260
261 if (sctx->b.chip_class >= CIK) {
262 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
263 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
264 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
265 } else {
266 if (sctx->screen->b.info.drm_major == 3 ||
267 (sctx->screen->b.info.drm_major == 2 &&
268 sctx->screen->b.info.drm_minor >= 48)) {
269 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
270 bc_va >> 8);
271 }
272 }
273
274 sctx->cs_shader_state.emitted_program = NULL;
275 sctx->cs_shader_state.initialized = true;
276 }
277
278 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
279 struct si_shader *shader,
280 struct si_shader_config *config)
281 {
282 uint64_t scratch_bo_size, scratch_needed;
283 scratch_bo_size = 0;
284 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
285 if (sctx->compute_scratch_buffer)
286 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
287
288 if (scratch_bo_size < scratch_needed) {
289 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
290
291 sctx->compute_scratch_buffer = (struct r600_resource*)
292 pipe_buffer_create(&sctx->screen->b.b, 0,
293 PIPE_USAGE_DEFAULT, scratch_needed);
294
295 if (!sctx->compute_scratch_buffer)
296 return false;
297 }
298
299 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
300 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
301
302 si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
303
304 if (si_shader_binary_upload(sctx->screen, shader))
305 return false;
306
307 r600_resource_reference(&shader->scratch_bo,
308 sctx->compute_scratch_buffer);
309 }
310
311 return true;
312 }
313
314 static bool si_switch_compute_shader(struct si_context *sctx,
315 struct si_compute *program,
316 struct si_shader *shader,
317 const amd_kernel_code_t *code_object,
318 unsigned offset)
319 {
320 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
321 struct si_shader_config inline_config = {0};
322 struct si_shader_config *config;
323 uint64_t shader_va;
324
325 if (sctx->cs_shader_state.emitted_program == program &&
326 sctx->cs_shader_state.offset == offset)
327 return true;
328
329 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
330 config = &shader->config;
331 } else {
332 unsigned lds_blocks;
333
334 config = &inline_config;
335 if (code_object) {
336 code_object_to_config(code_object, config);
337 } else {
338 si_shader_binary_read_config(&shader->binary, config, offset);
339 }
340
341 lds_blocks = config->lds_size;
342 /* XXX: We are over allocating LDS. For SI, the shader reports
343 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
344 * allocated in the shader and 4 bytes allocated by the state
345 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
346 */
347 if (sctx->b.chip_class <= SI) {
348 lds_blocks += align(program->local_size, 256) >> 8;
349 } else {
350 lds_blocks += align(program->local_size, 512) >> 9;
351 }
352
353 /* TODO: use si_multiwave_lds_size_workaround */
354 assert(lds_blocks <= 0xFF);
355
356 config->rsrc2 &= C_00B84C_LDS_SIZE;
357 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
358 }
359
360 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
361 return false;
362
363 if (shader->scratch_bo) {
364 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
365 "Total Scratch: %u bytes\n", sctx->scratch_waves,
366 config->scratch_bytes_per_wave,
367 config->scratch_bytes_per_wave *
368 sctx->scratch_waves);
369
370 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
371 shader->scratch_bo, RADEON_USAGE_READWRITE,
372 RADEON_PRIO_SCRATCH_BUFFER);
373 }
374
375 /* Prefetch the compute shader to TC L2.
376 *
377 * We should also prefetch graphics shaders if a compute dispatch was
378 * the last command, and the compute shader if a draw call was the last
379 * command. However, that would add more complexity and we're likely
380 * to get a shader state change in that case anyway.
381 */
382 if (sctx->b.chip_class >= CIK) {
383 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
384 0, program->shader.bo->b.b.width0);
385 }
386
387 shader_va = shader->bo->gpu_address + offset;
388 if (program->use_code_object_v2) {
389 /* Shader code is placed after the amd_kernel_code_t
390 * struct. */
391 shader_va += sizeof(amd_kernel_code_t);
392 }
393
394 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
395 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
396
397 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
398 radeon_emit(cs, shader_va >> 8);
399 radeon_emit(cs, shader_va >> 40);
400
401 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
402 radeon_emit(cs, config->rsrc1);
403 radeon_emit(cs, config->rsrc2);
404
405 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
406 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
407
408 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
409 S_00B860_WAVES(sctx->scratch_waves)
410 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
411
412 sctx->cs_shader_state.emitted_program = program;
413 sctx->cs_shader_state.offset = offset;
414 sctx->cs_shader_state.uses_scratch =
415 config->scratch_bytes_per_wave != 0;
416
417 return true;
418 }
419
420 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
421 const amd_kernel_code_t *code_object,
422 unsigned user_sgpr)
423 {
424 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
425 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
426
427 unsigned max_private_element_size = AMD_HSA_BITS_GET(
428 code_object->code_properties,
429 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
430
431 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
432 uint32_t scratch_dword1 =
433 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
434 S_008F04_SWIZZLE_ENABLE(1);
435
436 /* Disable address clamping */
437 uint32_t scratch_dword2 = 0xffffffff;
438 uint32_t scratch_dword3 =
439 S_008F0C_ELEMENT_SIZE(max_private_element_size) |
440 S_008F0C_INDEX_STRIDE(3) |
441 S_008F0C_ADD_TID_ENABLE(1);
442
443
444 if (sctx->screen->b.chip_class < VI) {
445 /* BUF_DATA_FORMAT is ignored, but it cannot be
446 BUF_DATA_FORMAT_INVALID. */
447 scratch_dword3 |=
448 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
449 }
450
451 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
452 (user_sgpr * 4), 4);
453 radeon_emit(cs, scratch_dword0);
454 radeon_emit(cs, scratch_dword1);
455 radeon_emit(cs, scratch_dword2);
456 radeon_emit(cs, scratch_dword3);
457 }
458
459 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
460 const amd_kernel_code_t *code_object,
461 const struct pipe_grid_info *info,
462 uint64_t kernel_args_va)
463 {
464 struct si_compute *program = sctx->cs_shader_state.program;
465 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
466
467 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
468 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
469 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
470 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
471 };
472
473 unsigned i, user_sgpr = 0;
474 if (AMD_HSA_BITS_GET(code_object->code_properties,
475 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
476 if (code_object->workitem_private_segment_byte_size > 0) {
477 setup_scratch_rsrc_user_sgprs(sctx, code_object,
478 user_sgpr);
479 }
480 user_sgpr += 4;
481 }
482
483 if (AMD_HSA_BITS_GET(code_object->code_properties,
484 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
485 struct dispatch_packet dispatch;
486 unsigned dispatch_offset;
487 struct r600_resource *dispatch_buf = NULL;
488 uint64_t dispatch_va;
489
490 /* Upload dispatch ptr */
491 memset(&dispatch, 0, sizeof(dispatch));
492
493 dispatch.workgroup_size_x = info->block[0];
494 dispatch.workgroup_size_y = info->block[1];
495 dispatch.workgroup_size_z = info->block[2];
496
497 dispatch.grid_size_x = info->grid[0] * info->block[0];
498 dispatch.grid_size_y = info->grid[1] * info->block[1];
499 dispatch.grid_size_z = info->grid[2] * info->block[2];
500
501 dispatch.private_segment_size = program->private_size;
502 dispatch.group_segment_size = program->local_size;
503
504 dispatch.kernarg_address = kernel_args_va;
505
506 u_upload_data(sctx->b.b.stream_uploader, 0, sizeof(dispatch),
507 256, &dispatch, &dispatch_offset,
508 (struct pipe_resource**)&dispatch_buf);
509
510 if (!dispatch_buf) {
511 fprintf(stderr, "Error: Failed to allocate dispatch "
512 "packet.");
513 }
514 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
515 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
516
517 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
518
519 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
520 (user_sgpr * 4), 2);
521 radeon_emit(cs, dispatch_va);
522 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
523 S_008F04_STRIDE(0));
524
525 r600_resource_reference(&dispatch_buf, NULL);
526 user_sgpr += 2;
527 }
528
529 if (AMD_HSA_BITS_GET(code_object->code_properties,
530 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
531 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
532 (user_sgpr * 4), 2);
533 radeon_emit(cs, kernel_args_va);
534 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
535 S_008F04_STRIDE(0));
536 user_sgpr += 2;
537 }
538
539 for (i = 0; i < 3 && user_sgpr < 16; i++) {
540 if (code_object->code_properties & workgroup_count_masks[i]) {
541 radeon_set_sh_reg_seq(cs,
542 R_00B900_COMPUTE_USER_DATA_0 +
543 (user_sgpr * 4), 1);
544 radeon_emit(cs, info->grid[i]);
545 user_sgpr += 1;
546 }
547 }
548 }
549
550 static void si_upload_compute_input(struct si_context *sctx,
551 const amd_kernel_code_t *code_object,
552 const struct pipe_grid_info *info)
553 {
554 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
555 struct si_compute *program = sctx->cs_shader_state.program;
556 struct r600_resource *input_buffer = NULL;
557 unsigned kernel_args_size;
558 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
559 uint32_t kernel_args_offset = 0;
560 uint32_t *kernel_args;
561 void *kernel_args_ptr;
562 uint64_t kernel_args_va;
563 unsigned i;
564
565 /* The extra num_work_size_bytes are for work group / work item size information */
566 kernel_args_size = program->input_size + num_work_size_bytes;
567
568 u_upload_alloc(sctx->b.b.stream_uploader, 0, kernel_args_size,
569 sctx->screen->b.info.tcc_cache_line_size,
570 &kernel_args_offset,
571 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
572
573 kernel_args = (uint32_t*)kernel_args_ptr;
574 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
575
576 if (!code_object) {
577 for (i = 0; i < 3; i++) {
578 kernel_args[i] = info->grid[i];
579 kernel_args[i + 3] = info->grid[i] * info->block[i];
580 kernel_args[i + 6] = info->block[i];
581 }
582 }
583
584 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
585 program->input_size);
586
587
588 for (i = 0; i < (kernel_args_size / 4); i++) {
589 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
590 kernel_args[i]);
591 }
592
593
594 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
595 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
596
597 if (code_object) {
598 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
599 } else {
600 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
601 radeon_emit(cs, kernel_args_va);
602 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
603 S_008F04_STRIDE(0));
604 }
605
606 r600_resource_reference(&input_buffer, NULL);
607 }
608
609 static void si_setup_tgsi_grid(struct si_context *sctx,
610 const struct pipe_grid_info *info)
611 {
612 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
613 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
614 4 * SI_SGPR_GRID_SIZE;
615
616 if (info->indirect) {
617 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
618 uint64_t va = base_va + info->indirect_offset;
619 int i;
620
621 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
622 (struct r600_resource *)info->indirect,
623 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
624
625 for (i = 0; i < 3; ++i) {
626 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
627 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
628 COPY_DATA_DST_SEL(COPY_DATA_REG));
629 radeon_emit(cs, (va + 4 * i));
630 radeon_emit(cs, (va + 4 * i) >> 32);
631 radeon_emit(cs, (grid_size_reg >> 2) + i);
632 radeon_emit(cs, 0);
633 }
634 } else {
635 struct si_compute *program = sctx->cs_shader_state.program;
636
637 radeon_set_sh_reg_seq(cs, grid_size_reg, program->variable_group_size ? 6 : 3);
638 radeon_emit(cs, info->grid[0]);
639 radeon_emit(cs, info->grid[1]);
640 radeon_emit(cs, info->grid[2]);
641 if (program->variable_group_size) {
642 radeon_emit(cs, info->block[0]);
643 radeon_emit(cs, info->block[1]);
644 radeon_emit(cs, info->block[2]);
645 }
646 }
647 }
648
649 static void si_emit_dispatch_packets(struct si_context *sctx,
650 const struct pipe_grid_info *info)
651 {
652 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
653 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
654 unsigned waves_per_threadgroup =
655 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
656
657 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
658 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
659
660 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
661 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
662 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
663 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
664
665 if (info->indirect) {
666 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
667
668 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
669 (struct r600_resource *)info->indirect,
670 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
671
672 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
673 PKT3_SHADER_TYPE_S(1));
674 radeon_emit(cs, 1);
675 radeon_emit(cs, base_va);
676 radeon_emit(cs, base_va >> 32);
677
678 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
679 PKT3_SHADER_TYPE_S(1));
680 radeon_emit(cs, info->indirect_offset);
681 radeon_emit(cs, 1);
682 } else {
683 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
684 PKT3_SHADER_TYPE_S(1));
685 radeon_emit(cs, info->grid[0]);
686 radeon_emit(cs, info->grid[1]);
687 radeon_emit(cs, info->grid[2]);
688 radeon_emit(cs, 1);
689 }
690 }
691
692
693 static void si_launch_grid(
694 struct pipe_context *ctx, const struct pipe_grid_info *info)
695 {
696 struct si_context *sctx = (struct si_context*)ctx;
697 struct si_compute *program = sctx->cs_shader_state.program;
698 const amd_kernel_code_t *code_object =
699 si_compute_get_code_object(program, info->pc);
700 int i;
701 /* HW bug workaround when CS threadgroups > 256 threads and async
702 * compute isn't used, i.e. only one compute job can run at a time.
703 * If async compute is possible, the threadgroup size must be limited
704 * to 256 threads on all queues to avoid the bug.
705 * Only SI and certain CIK chips are affected.
706 */
707 bool cs_regalloc_hang =
708 (sctx->b.chip_class == SI ||
709 sctx->b.family == CHIP_BONAIRE ||
710 sctx->b.family == CHIP_KABINI) &&
711 info->block[0] * info->block[1] * info->block[2] > 256;
712
713 if (cs_regalloc_hang)
714 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
715 SI_CONTEXT_CS_PARTIAL_FLUSH;
716
717 si_decompress_compute_textures(sctx);
718
719 /* Add buffer sizes for memory checking in need_cs_space. */
720 r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
721 /* TODO: add the scratch buffer */
722
723 if (info->indirect) {
724 r600_context_add_resource_size(ctx, info->indirect);
725
726 /* The hw doesn't read the indirect buffer via TC L2. */
727 if (r600_resource(info->indirect)->TC_L2_dirty) {
728 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
729 r600_resource(info->indirect)->TC_L2_dirty = false;
730 }
731 }
732
733 si_need_cs_space(sctx);
734
735 if (!sctx->cs_shader_state.initialized)
736 si_initialize_compute(sctx);
737
738 if (sctx->b.flags)
739 si_emit_cache_flush(sctx);
740
741 if (!si_switch_compute_shader(sctx, program, &program->shader,
742 code_object, info->pc))
743 return;
744
745 si_upload_compute_shader_descriptors(sctx);
746 si_emit_compute_shader_userdata(sctx);
747
748 if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
749 sctx->atoms.s.render_cond->emit(&sctx->b,
750 sctx->atoms.s.render_cond);
751 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
752 }
753
754 if (program->input_size || program->ir_type == PIPE_SHADER_IR_NATIVE)
755 si_upload_compute_input(sctx, code_object, info);
756
757 /* Global buffers */
758 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
759 struct r600_resource *buffer =
760 (struct r600_resource*)program->global_buffers[i];
761 if (!buffer) {
762 continue;
763 }
764 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
765 RADEON_USAGE_READWRITE,
766 RADEON_PRIO_COMPUTE_GLOBAL);
767 }
768
769 if (program->ir_type == PIPE_SHADER_IR_TGSI)
770 si_setup_tgsi_grid(sctx, info);
771
772 si_ce_pre_draw_synchronization(sctx);
773
774 si_emit_dispatch_packets(sctx, info);
775
776 si_ce_post_draw_synchronization(sctx);
777
778 sctx->compute_is_busy = true;
779 sctx->b.num_compute_calls++;
780 if (sctx->cs_shader_state.uses_scratch)
781 sctx->b.num_spill_compute_calls++;
782
783 if (cs_regalloc_hang)
784 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
785 }
786
787
788 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
789 struct si_compute *program = (struct si_compute *)state;
790 struct si_context *sctx = (struct si_context*)ctx;
791
792 if (!state) {
793 return;
794 }
795
796 if (program == sctx->cs_shader_state.program)
797 sctx->cs_shader_state.program = NULL;
798
799 if (program == sctx->cs_shader_state.emitted_program)
800 sctx->cs_shader_state.emitted_program = NULL;
801
802 si_shader_destroy(&program->shader);
803 FREE(program);
804 }
805
806 static void si_set_compute_resources(struct pipe_context * ctx_,
807 unsigned start, unsigned count,
808 struct pipe_surface ** surfaces) { }
809
810 void si_init_compute_functions(struct si_context *sctx)
811 {
812 sctx->b.b.create_compute_state = si_create_compute_state;
813 sctx->b.b.delete_compute_state = si_delete_compute_state;
814 sctx->b.b.bind_compute_state = si_bind_compute_state;
815 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
816 sctx->b.b.set_compute_resources = si_set_compute_resources;
817 sctx->b.b.set_global_binding = si_set_global_binding;
818 sctx->b.b.launch_grid = si_launch_grid;
819 }