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radeonsi: fix leaked compute shader NIR
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "tgsi/tgsi_parse.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30
31 #include "ac_rtld.h"
32 #include "amd_kernel_code_t.h"
33 #include "si_build_pm4.h"
34 #include "si_compute.h"
35
36 #define COMPUTE_DBG(sscreen, fmt, args...) \
37 do { \
38 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
39 } while (0);
40
41 struct dispatch_packet {
42 uint16_t header;
43 uint16_t setup;
44 uint16_t workgroup_size_x;
45 uint16_t workgroup_size_y;
46 uint16_t workgroup_size_z;
47 uint16_t reserved0;
48 uint32_t grid_size_x;
49 uint32_t grid_size_y;
50 uint32_t grid_size_z;
51 uint32_t private_segment_size;
52 uint32_t group_segment_size;
53 uint64_t kernel_object;
54 uint64_t kernarg_address;
55 uint64_t reserved2;
56 };
57
58 static const amd_kernel_code_t *si_compute_get_code_object(
59 const struct si_compute *program,
60 uint64_t symbol_offset)
61 {
62 if (!program->use_code_object_v2) {
63 return NULL;
64 }
65
66 struct ac_rtld_binary rtld;
67 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
68 .info = &program->screen->info,
69 .shader_type = MESA_SHADER_COMPUTE,
70 .num_parts = 1,
71 .elf_ptrs = &program->shader.binary.elf_buffer,
72 .elf_sizes = &program->shader.binary.elf_size }))
73 return NULL;
74
75 const amd_kernel_code_t *result = NULL;
76 const char *text;
77 size_t size;
78 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
79 goto out;
80
81 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
82 goto out;
83
84 result = (const amd_kernel_code_t*)(text + symbol_offset);
85
86 out:
87 ac_rtld_close(&rtld);
88 return result;
89 }
90
91 static void code_object_to_config(const amd_kernel_code_t *code_object,
92 struct ac_shader_config *out_config) {
93
94 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
95 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
96 out_config->num_sgprs = code_object->wavefront_sgpr_count;
97 out_config->num_vgprs = code_object->workitem_vgpr_count;
98 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
99 out_config->rsrc1 = rsrc1;
100 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
101 out_config->rsrc2 = rsrc2;
102 out_config->scratch_bytes_per_wave =
103 align(code_object->workitem_private_segment_byte_size * 64, 1024);
104 }
105
106 /* Asynchronous compute shader compilation. */
107 static void si_create_compute_state_async(void *job, int thread_index)
108 {
109 struct si_compute *program = (struct si_compute *)job;
110 struct si_shader *shader = &program->shader;
111 struct si_shader_selector sel;
112 struct ac_llvm_compiler *compiler;
113 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
114 struct si_screen *sscreen = program->screen;
115
116 assert(!debug->debug_message || debug->async);
117 assert(thread_index >= 0);
118 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
119 compiler = &sscreen->compiler[thread_index];
120
121 memset(&sel, 0, sizeof(sel));
122
123 sel.screen = sscreen;
124
125 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
126 tgsi_scan_shader(program->ir.tgsi, &sel.info);
127 sel.tokens = program->ir.tgsi;
128 } else {
129 assert(program->ir_type == PIPE_SHADER_IR_NIR);
130 sel.nir = program->ir.nir;
131
132 si_nir_opts(sel.nir);
133 si_nir_scan_shader(sel.nir, &sel.info);
134 si_lower_nir(&sel);
135 }
136
137 /* Store the declared LDS size into tgsi_shader_info for the shader
138 * cache to include it.
139 */
140 sel.info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
141
142 sel.type = PIPE_SHADER_COMPUTE;
143 si_get_active_slot_masks(&sel.info,
144 &program->active_const_and_shader_buffers,
145 &program->active_samplers_and_images);
146
147 program->shader.selector = &sel;
148 program->shader.is_monolithic = true;
149 program->uses_grid_size = sel.info.uses_grid_size;
150 program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
151 program->uses_bindless_images = sel.info.uses_bindless_images;
152 program->reads_variable_block_size =
153 sel.info.uses_block_size &&
154 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
155 program->num_cs_user_data_dwords =
156 sel.info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
157
158 void *ir_binary = si_get_ir_binary(&sel);
159
160 /* Try to load the shader from the shader cache. */
161 mtx_lock(&sscreen->shader_cache_mutex);
162
163 if (ir_binary &&
164 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
165 mtx_unlock(&sscreen->shader_cache_mutex);
166
167 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
168 si_shader_dump(sscreen, shader, debug, stderr, true);
169
170 if (!si_shader_binary_upload(sscreen, shader, 0))
171 program->shader.compilation_failed = true;
172 } else {
173 mtx_unlock(&sscreen->shader_cache_mutex);
174
175 if (!si_shader_create(sscreen, compiler, &program->shader, debug)) {
176 program->shader.compilation_failed = true;
177
178 if (program->ir_type == PIPE_SHADER_IR_TGSI)
179 FREE(program->ir.tgsi);
180 program->shader.selector = NULL;
181 return;
182 }
183
184 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
185 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
186 (sel.info.uses_grid_size ? 3 : 0) +
187 (program->reads_variable_block_size ? 3 : 0) +
188 program->num_cs_user_data_dwords;
189
190 shader->config.rsrc1 =
191 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
192 S_00B848_DX10_CLAMP(1) |
193 S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
194 S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
195 S_00B848_FLOAT_MODE(shader->config.float_mode);
196
197 if (program->screen->info.chip_class < GFX10) {
198 shader->config.rsrc1 |=
199 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
200 }
201
202 shader->config.rsrc2 =
203 S_00B84C_USER_SGPR(user_sgprs) |
204 S_00B84C_SCRATCH_EN(scratch_enabled) |
205 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
206 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
207 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
208 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
209 sel.info.uses_thread_id[1] ? 1 : 0) |
210 S_00B84C_LDS_SIZE(shader->config.lds_size);
211
212 if (ir_binary) {
213 mtx_lock(&sscreen->shader_cache_mutex);
214 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
215 FREE(ir_binary);
216 mtx_unlock(&sscreen->shader_cache_mutex);
217 }
218 }
219
220 if (program->ir_type == PIPE_SHADER_IR_TGSI)
221 FREE(program->ir.tgsi);
222
223 program->shader.selector = NULL;
224 }
225
226 static void *si_create_compute_state(
227 struct pipe_context *ctx,
228 const struct pipe_compute_state *cso)
229 {
230 struct si_context *sctx = (struct si_context *)ctx;
231 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
232 struct si_compute *program = CALLOC_STRUCT(si_compute);
233
234 pipe_reference_init(&program->reference, 1);
235 program->screen = (struct si_screen *)ctx->screen;
236 program->ir_type = cso->ir_type;
237 program->local_size = cso->req_local_mem;
238 program->private_size = cso->req_private_mem;
239 program->input_size = cso->req_input_mem;
240 program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
241
242 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
243 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
244 program->ir.tgsi = tgsi_dup_tokens(cso->prog);
245 if (!program->ir.tgsi) {
246 FREE(program);
247 return NULL;
248 }
249 } else {
250 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
251 program->ir.nir = (struct nir_shader *) cso->prog;
252 }
253
254 program->compiler_ctx_state.debug = sctx->debug;
255 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
256 p_atomic_inc(&sscreen->num_shaders_created);
257
258 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
259 &program->ready,
260 &program->compiler_ctx_state,
261 program, si_create_compute_state_async);
262 } else {
263 const struct pipe_llvm_program_header *header;
264 const char *code;
265 header = cso->prog;
266 code = cso->prog + sizeof(struct pipe_llvm_program_header);
267
268 program->shader.binary.elf_size = header->num_bytes;
269 program->shader.binary.elf_buffer = malloc(header->num_bytes);
270 if (!program->shader.binary.elf_buffer) {
271 FREE(program);
272 return NULL;
273 }
274 memcpy((void *)program->shader.binary.elf_buffer, code, header->num_bytes);
275
276 const amd_kernel_code_t *code_object =
277 si_compute_get_code_object(program, 0);
278 code_object_to_config(code_object, &program->shader.config);
279
280 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
281 if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
282 fprintf(stderr, "LLVM failed to upload shader\n");
283 free((void *)program->shader.binary.elf_buffer);
284 FREE(program);
285 return NULL;
286 }
287 }
288
289 return program;
290 }
291
292 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
293 {
294 struct si_context *sctx = (struct si_context*)ctx;
295 struct si_compute *program = (struct si_compute*)state;
296
297 sctx->cs_shader_state.program = program;
298 if (!program)
299 return;
300
301 /* Wait because we need active slot usage masks. */
302 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
303 util_queue_fence_wait(&program->ready);
304
305 si_set_active_descriptors(sctx,
306 SI_DESCS_FIRST_COMPUTE +
307 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
308 program->active_const_and_shader_buffers);
309 si_set_active_descriptors(sctx,
310 SI_DESCS_FIRST_COMPUTE +
311 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
312 program->active_samplers_and_images);
313 }
314
315 static void si_set_global_binding(
316 struct pipe_context *ctx, unsigned first, unsigned n,
317 struct pipe_resource **resources,
318 uint32_t **handles)
319 {
320 unsigned i;
321 struct si_context *sctx = (struct si_context*)ctx;
322 struct si_compute *program = sctx->cs_shader_state.program;
323
324 assert(first + n <= MAX_GLOBAL_BUFFERS);
325
326 if (!resources) {
327 for (i = 0; i < n; i++) {
328 pipe_resource_reference(&program->global_buffers[first + i], NULL);
329 }
330 return;
331 }
332
333 for (i = 0; i < n; i++) {
334 uint64_t va;
335 uint32_t offset;
336 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
337 va = si_resource(resources[i])->gpu_address;
338 offset = util_le32_to_cpu(*handles[i]);
339 va += offset;
340 va = util_cpu_to_le64(va);
341 memcpy(handles[i], &va, sizeof(va));
342 }
343 }
344
345 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
346 {
347 uint64_t bc_va;
348
349 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
350 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
351 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
352 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
353 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
354
355 if (sctx->chip_class >= GFX7) {
356 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
357 radeon_set_sh_reg_seq(cs,
358 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
359 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
360 S_00B858_SH1_CU_EN(0xffff));
361 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
362 S_00B858_SH1_CU_EN(0xffff));
363 }
364
365 if (sctx->chip_class >= GFX10)
366 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
367
368 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
369 * and is now per pipe, so it should be handled in the
370 * kernel if we want to use something other than the default value,
371 * which is now 0x22f.
372 */
373 if (sctx->chip_class <= GFX6) {
374 /* XXX: This should be:
375 * (number of compute units) * 4 * (waves per simd) - 1 */
376
377 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
378 0x190 /* Default value */);
379 }
380
381 /* Set the pointer to border colors. */
382 bc_va = sctx->border_color_buffer->gpu_address;
383
384 if (sctx->chip_class >= GFX7) {
385 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
386 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
387 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
388 } else {
389 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
390 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
391 bc_va >> 8);
392 }
393 }
394 }
395
396 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
397 struct si_shader *shader,
398 struct ac_shader_config *config)
399 {
400 uint64_t scratch_bo_size, scratch_needed;
401 scratch_bo_size = 0;
402 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
403 if (sctx->compute_scratch_buffer)
404 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
405
406 if (scratch_bo_size < scratch_needed) {
407 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
408
409 sctx->compute_scratch_buffer =
410 si_aligned_buffer_create(&sctx->screen->b,
411 SI_RESOURCE_FLAG_UNMAPPABLE,
412 PIPE_USAGE_DEFAULT,
413 scratch_needed, 256);
414
415 if (!sctx->compute_scratch_buffer)
416 return false;
417 }
418
419 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
420 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
421
422 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
423 return false;
424
425 si_resource_reference(&shader->scratch_bo,
426 sctx->compute_scratch_buffer);
427 }
428
429 return true;
430 }
431
432 static bool si_switch_compute_shader(struct si_context *sctx,
433 struct si_compute *program,
434 struct si_shader *shader,
435 const amd_kernel_code_t *code_object,
436 unsigned offset)
437 {
438 struct radeon_cmdbuf *cs = sctx->gfx_cs;
439 struct ac_shader_config inline_config = {0};
440 struct ac_shader_config *config;
441 uint64_t shader_va;
442
443 if (sctx->cs_shader_state.emitted_program == program &&
444 sctx->cs_shader_state.offset == offset)
445 return true;
446
447 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
448 config = &shader->config;
449 } else {
450 unsigned lds_blocks;
451
452 config = &inline_config;
453 code_object_to_config(code_object, config);
454
455 lds_blocks = config->lds_size;
456 /* XXX: We are over allocating LDS. For GFX6, the shader reports
457 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
458 * allocated in the shader and 4 bytes allocated by the state
459 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
460 */
461 if (sctx->chip_class <= GFX6) {
462 lds_blocks += align(program->local_size, 256) >> 8;
463 } else {
464 lds_blocks += align(program->local_size, 512) >> 9;
465 }
466
467 /* TODO: use si_multiwave_lds_size_workaround */
468 assert(lds_blocks <= 0xFF);
469
470 config->rsrc2 &= C_00B84C_LDS_SIZE;
471 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
472 }
473
474 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
475 return false;
476
477 if (shader->scratch_bo) {
478 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
479 "Total Scratch: %u bytes\n", sctx->scratch_waves,
480 config->scratch_bytes_per_wave,
481 config->scratch_bytes_per_wave *
482 sctx->scratch_waves);
483
484 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
485 shader->scratch_bo, RADEON_USAGE_READWRITE,
486 RADEON_PRIO_SCRATCH_BUFFER);
487 }
488
489 /* Prefetch the compute shader to TC L2.
490 *
491 * We should also prefetch graphics shaders if a compute dispatch was
492 * the last command, and the compute shader if a draw call was the last
493 * command. However, that would add more complexity and we're likely
494 * to get a shader state change in that case anyway.
495 */
496 if (sctx->chip_class >= GFX7) {
497 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
498 0, program->shader.bo->b.b.width0);
499 }
500
501 shader_va = shader->bo->gpu_address + offset;
502 if (program->use_code_object_v2) {
503 /* Shader code is placed after the amd_kernel_code_t
504 * struct. */
505 shader_va += sizeof(amd_kernel_code_t);
506 }
507
508 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
509 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
510
511 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
512 radeon_emit(cs, shader_va >> 8);
513 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
514
515 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
516 radeon_emit(cs, config->rsrc1);
517 radeon_emit(cs, config->rsrc2);
518
519 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
520 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
521
522 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
523 S_00B860_WAVES(sctx->scratch_waves)
524 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
525
526 sctx->cs_shader_state.emitted_program = program;
527 sctx->cs_shader_state.offset = offset;
528 sctx->cs_shader_state.uses_scratch =
529 config->scratch_bytes_per_wave != 0;
530
531 return true;
532 }
533
534 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
535 const amd_kernel_code_t *code_object,
536 unsigned user_sgpr)
537 {
538 struct radeon_cmdbuf *cs = sctx->gfx_cs;
539 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
540
541 unsigned max_private_element_size = AMD_HSA_BITS_GET(
542 code_object->code_properties,
543 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
544
545 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
546 uint32_t scratch_dword1 =
547 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
548 S_008F04_SWIZZLE_ENABLE(1);
549
550 /* Disable address clamping */
551 uint32_t scratch_dword2 = 0xffffffff;
552 uint32_t scratch_dword3 =
553 S_008F0C_INDEX_STRIDE(3) |
554 S_008F0C_ADD_TID_ENABLE(1);
555
556 if (sctx->chip_class >= GFX9) {
557 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
558 } else {
559 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
560
561 if (sctx->chip_class < GFX8) {
562 /* BUF_DATA_FORMAT is ignored, but it cannot be
563 * BUF_DATA_FORMAT_INVALID. */
564 scratch_dword3 |=
565 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
566 }
567 }
568
569 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
570 (user_sgpr * 4), 4);
571 radeon_emit(cs, scratch_dword0);
572 radeon_emit(cs, scratch_dword1);
573 radeon_emit(cs, scratch_dword2);
574 radeon_emit(cs, scratch_dword3);
575 }
576
577 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
578 const amd_kernel_code_t *code_object,
579 const struct pipe_grid_info *info,
580 uint64_t kernel_args_va)
581 {
582 struct si_compute *program = sctx->cs_shader_state.program;
583 struct radeon_cmdbuf *cs = sctx->gfx_cs;
584
585 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
586 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
587 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
588 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
589 };
590
591 unsigned i, user_sgpr = 0;
592 if (AMD_HSA_BITS_GET(code_object->code_properties,
593 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
594 if (code_object->workitem_private_segment_byte_size > 0) {
595 setup_scratch_rsrc_user_sgprs(sctx, code_object,
596 user_sgpr);
597 }
598 user_sgpr += 4;
599 }
600
601 if (AMD_HSA_BITS_GET(code_object->code_properties,
602 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
603 struct dispatch_packet dispatch;
604 unsigned dispatch_offset;
605 struct si_resource *dispatch_buf = NULL;
606 uint64_t dispatch_va;
607
608 /* Upload dispatch ptr */
609 memset(&dispatch, 0, sizeof(dispatch));
610
611 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
612 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
613 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
614
615 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
616 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
617 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
618
619 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
620 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
621
622 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
623
624 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
625 256, &dispatch, &dispatch_offset,
626 (struct pipe_resource**)&dispatch_buf);
627
628 if (!dispatch_buf) {
629 fprintf(stderr, "Error: Failed to allocate dispatch "
630 "packet.");
631 }
632 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
633 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
634
635 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
636
637 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
638 (user_sgpr * 4), 2);
639 radeon_emit(cs, dispatch_va);
640 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
641 S_008F04_STRIDE(0));
642
643 si_resource_reference(&dispatch_buf, NULL);
644 user_sgpr += 2;
645 }
646
647 if (AMD_HSA_BITS_GET(code_object->code_properties,
648 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
649 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
650 (user_sgpr * 4), 2);
651 radeon_emit(cs, kernel_args_va);
652 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
653 S_008F04_STRIDE(0));
654 user_sgpr += 2;
655 }
656
657 for (i = 0; i < 3 && user_sgpr < 16; i++) {
658 if (code_object->code_properties & workgroup_count_masks[i]) {
659 radeon_set_sh_reg_seq(cs,
660 R_00B900_COMPUTE_USER_DATA_0 +
661 (user_sgpr * 4), 1);
662 radeon_emit(cs, info->grid[i]);
663 user_sgpr += 1;
664 }
665 }
666 }
667
668 static bool si_upload_compute_input(struct si_context *sctx,
669 const amd_kernel_code_t *code_object,
670 const struct pipe_grid_info *info)
671 {
672 struct radeon_cmdbuf *cs = sctx->gfx_cs;
673 struct si_compute *program = sctx->cs_shader_state.program;
674 struct si_resource *input_buffer = NULL;
675 unsigned kernel_args_size;
676 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
677 uint32_t kernel_args_offset = 0;
678 uint32_t *kernel_args;
679 void *kernel_args_ptr;
680 uint64_t kernel_args_va;
681 unsigned i;
682
683 /* The extra num_work_size_bytes are for work group / work item size information */
684 kernel_args_size = program->input_size + num_work_size_bytes;
685
686 u_upload_alloc(sctx->b.const_uploader, 0, kernel_args_size,
687 sctx->screen->info.tcc_cache_line_size,
688 &kernel_args_offset,
689 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
690
691 if (unlikely(!kernel_args_ptr))
692 return false;
693
694 kernel_args = (uint32_t*)kernel_args_ptr;
695 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
696
697 if (!code_object) {
698 for (i = 0; i < 3; i++) {
699 kernel_args[i] = util_cpu_to_le32(info->grid[i]);
700 kernel_args[i + 3] = util_cpu_to_le32(info->grid[i] * info->block[i]);
701 kernel_args[i + 6] = util_cpu_to_le32(info->block[i]);
702 }
703 }
704
705 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
706 program->input_size);
707
708
709 for (i = 0; i < (kernel_args_size / 4); i++) {
710 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
711 kernel_args[i]);
712 }
713
714
715 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
716 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
717
718 if (code_object) {
719 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
720 } else {
721 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
722 radeon_emit(cs, kernel_args_va);
723 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
724 S_008F04_STRIDE(0));
725 }
726
727 si_resource_reference(&input_buffer, NULL);
728
729 return true;
730 }
731
732 static void si_setup_tgsi_user_data(struct si_context *sctx,
733 const struct pipe_grid_info *info)
734 {
735 struct si_compute *program = sctx->cs_shader_state.program;
736 struct radeon_cmdbuf *cs = sctx->gfx_cs;
737 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
738 4 * SI_NUM_RESOURCE_SGPRS;
739 unsigned block_size_reg = grid_size_reg +
740 /* 12 bytes = 3 dwords. */
741 12 * program->uses_grid_size;
742 unsigned cs_user_data_reg = block_size_reg +
743 12 * program->reads_variable_block_size;
744
745 if (info->indirect) {
746 if (program->uses_grid_size) {
747 for (unsigned i = 0; i < 3; ++i) {
748 si_cp_copy_data(sctx, sctx->gfx_cs,
749 COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
750 COPY_DATA_SRC_MEM, si_resource(info->indirect),
751 info->indirect_offset + 4 * i);
752 }
753 }
754 } else {
755 if (program->uses_grid_size) {
756 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
757 radeon_emit(cs, info->grid[0]);
758 radeon_emit(cs, info->grid[1]);
759 radeon_emit(cs, info->grid[2]);
760 }
761 if (program->reads_variable_block_size) {
762 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
763 radeon_emit(cs, info->block[0]);
764 radeon_emit(cs, info->block[1]);
765 radeon_emit(cs, info->block[2]);
766 }
767 }
768
769 if (program->num_cs_user_data_dwords) {
770 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
771 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
772 }
773 }
774
775 static void si_emit_dispatch_packets(struct si_context *sctx,
776 const struct pipe_grid_info *info)
777 {
778 struct si_screen *sscreen = sctx->screen;
779 struct radeon_cmdbuf *cs = sctx->gfx_cs;
780 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
781 unsigned threads_per_threadgroup =
782 info->block[0] * info->block[1] * info->block[2];
783 unsigned waves_per_threadgroup =
784 DIV_ROUND_UP(threads_per_threadgroup, 64);
785 unsigned threadgroups_per_cu = 1;
786
787 if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1)
788 threadgroups_per_cu = 2;
789
790 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
791 ac_get_compute_resource_limits(&sscreen->info,
792 waves_per_threadgroup,
793 sctx->cs_max_waves_per_sh,
794 threadgroups_per_cu));
795
796 unsigned dispatch_initiator =
797 S_00B800_COMPUTE_SHADER_EN(1) |
798 S_00B800_FORCE_START_AT_000(1) |
799 /* If the KMD allows it (there is a KMD hw register for it),
800 * allow launching waves out-of-order. (same as Vulkan) */
801 S_00B800_ORDER_MODE(sctx->chip_class >= GFX7);
802
803 const uint *last_block = info->last_block;
804 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
805
806 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
807
808 if (partial_block_en) {
809 unsigned partial[3];
810
811 /* If no partial_block, these should be an entire block size, not 0. */
812 partial[0] = last_block[0] ? last_block[0] : info->block[0];
813 partial[1] = last_block[1] ? last_block[1] : info->block[1];
814 partial[2] = last_block[2] ? last_block[2] : info->block[2];
815
816 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
817 S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
818 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
819 S_00B820_NUM_THREAD_PARTIAL(partial[1]));
820 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
821 S_00B824_NUM_THREAD_PARTIAL(partial[2]));
822
823 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
824 } else {
825 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
826 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
827 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
828 }
829
830 if (info->indirect) {
831 uint64_t base_va = si_resource(info->indirect)->gpu_address;
832
833 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
834 si_resource(info->indirect),
835 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
836
837 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
838 PKT3_SHADER_TYPE_S(1));
839 radeon_emit(cs, 1);
840 radeon_emit(cs, base_va);
841 radeon_emit(cs, base_va >> 32);
842
843 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
844 PKT3_SHADER_TYPE_S(1));
845 radeon_emit(cs, info->indirect_offset);
846 radeon_emit(cs, dispatch_initiator);
847 } else {
848 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
849 PKT3_SHADER_TYPE_S(1));
850 radeon_emit(cs, info->grid[0]);
851 radeon_emit(cs, info->grid[1]);
852 radeon_emit(cs, info->grid[2]);
853 radeon_emit(cs, dispatch_initiator);
854 }
855 }
856
857
858 static void si_launch_grid(
859 struct pipe_context *ctx, const struct pipe_grid_info *info)
860 {
861 struct si_context *sctx = (struct si_context*)ctx;
862 struct si_compute *program = sctx->cs_shader_state.program;
863 const amd_kernel_code_t *code_object =
864 si_compute_get_code_object(program, info->pc);
865 int i;
866 /* HW bug workaround when CS threadgroups > 256 threads and async
867 * compute isn't used, i.e. only one compute job can run at a time.
868 * If async compute is possible, the threadgroup size must be limited
869 * to 256 threads on all queues to avoid the bug.
870 * Only GFX6 and certain GFX7 chips are affected.
871 */
872 bool cs_regalloc_hang =
873 (sctx->chip_class == GFX6 ||
874 sctx->family == CHIP_BONAIRE ||
875 sctx->family == CHIP_KABINI) &&
876 info->block[0] * info->block[1] * info->block[2] > 256;
877
878 if (cs_regalloc_hang)
879 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
880 SI_CONTEXT_CS_PARTIAL_FLUSH;
881
882 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
883 program->shader.compilation_failed)
884 return;
885
886 if (sctx->has_graphics) {
887 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
888 si_update_fb_dirtiness_after_rendering(sctx);
889 sctx->last_num_draw_calls = sctx->num_draw_calls;
890 }
891
892 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
893 }
894
895 /* Add buffer sizes for memory checking in need_cs_space. */
896 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
897 /* TODO: add the scratch buffer */
898
899 if (info->indirect) {
900 si_context_add_resource_size(sctx, info->indirect);
901
902 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
903 if (sctx->chip_class <= GFX8 &&
904 si_resource(info->indirect)->TC_L2_dirty) {
905 sctx->flags |= SI_CONTEXT_WB_L2;
906 si_resource(info->indirect)->TC_L2_dirty = false;
907 }
908 }
909
910 si_need_gfx_cs_space(sctx);
911
912 if (sctx->bo_list_add_all_compute_resources)
913 si_compute_resources_add_all_to_bo_list(sctx);
914
915 if (!sctx->cs_shader_state.initialized) {
916 si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
917
918 sctx->cs_shader_state.emitted_program = NULL;
919 sctx->cs_shader_state.initialized = true;
920 }
921
922 if (sctx->flags)
923 sctx->emit_cache_flush(sctx);
924
925 if (!si_switch_compute_shader(sctx, program, &program->shader,
926 code_object, info->pc))
927 return;
928
929 si_upload_compute_shader_descriptors(sctx);
930 si_emit_compute_shader_pointers(sctx);
931
932 if (sctx->has_graphics &&
933 si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
934 sctx->atoms.s.render_cond.emit(sctx);
935 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
936 }
937
938 if ((program->input_size ||
939 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
940 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
941 return;
942 }
943
944 /* Global buffers */
945 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
946 struct si_resource *buffer =
947 si_resource(program->global_buffers[i]);
948 if (!buffer) {
949 continue;
950 }
951 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
952 RADEON_USAGE_READWRITE,
953 RADEON_PRIO_COMPUTE_GLOBAL);
954 }
955
956 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
957 si_setup_tgsi_user_data(sctx, info);
958
959 si_emit_dispatch_packets(sctx, info);
960
961 if (unlikely(sctx->current_saved_cs)) {
962 si_trace_emit(sctx);
963 si_log_compute_state(sctx, sctx->log);
964 }
965
966 sctx->compute_is_busy = true;
967 sctx->num_compute_calls++;
968 if (sctx->cs_shader_state.uses_scratch)
969 sctx->num_spill_compute_calls++;
970
971 if (cs_regalloc_hang)
972 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
973 }
974
975 void si_destroy_compute(struct si_compute *program)
976 {
977 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
978 util_queue_drop_job(&program->screen->shader_compiler_queue,
979 &program->ready);
980 util_queue_fence_destroy(&program->ready);
981 }
982
983 si_shader_destroy(&program->shader);
984 FREE(program);
985 }
986
987 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
988 struct si_compute *program = (struct si_compute *)state;
989 struct si_context *sctx = (struct si_context*)ctx;
990
991 if (!state)
992 return;
993
994 if (program == sctx->cs_shader_state.program)
995 sctx->cs_shader_state.program = NULL;
996
997 if (program == sctx->cs_shader_state.emitted_program)
998 sctx->cs_shader_state.emitted_program = NULL;
999
1000 ralloc_free(program->sel.nir);
1001 si_compute_reference(&program, NULL);
1002 }
1003
1004 static void si_set_compute_resources(struct pipe_context * ctx_,
1005 unsigned start, unsigned count,
1006 struct pipe_surface ** surfaces) { }
1007
1008 void si_init_compute_functions(struct si_context *sctx)
1009 {
1010 sctx->b.create_compute_state = si_create_compute_state;
1011 sctx->b.delete_compute_state = si_delete_compute_state;
1012 sctx->b.bind_compute_state = si_bind_compute_state;
1013 sctx->b.set_compute_resources = si_set_compute_resources;
1014 sctx->b.set_global_binding = si_set_global_binding;
1015 sctx->b.launch_grid = si_launch_grid;
1016 }