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radeonsi: don't keep compute shader IR after compilation
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "nir/tgsi_to_nir.h"
27 #include "tgsi/tgsi_parse.h"
28 #include "util/u_async_debug.h"
29 #include "util/u_memory.h"
30 #include "util/u_upload_mgr.h"
31
32 #include "ac_rtld.h"
33 #include "amd_kernel_code_t.h"
34 #include "si_build_pm4.h"
35 #include "si_compute.h"
36
37 #define COMPUTE_DBG(sscreen, fmt, args...) \
38 do { \
39 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
40 } while (0);
41
42 struct dispatch_packet {
43 uint16_t header;
44 uint16_t setup;
45 uint16_t workgroup_size_x;
46 uint16_t workgroup_size_y;
47 uint16_t workgroup_size_z;
48 uint16_t reserved0;
49 uint32_t grid_size_x;
50 uint32_t grid_size_y;
51 uint32_t grid_size_z;
52 uint32_t private_segment_size;
53 uint32_t group_segment_size;
54 uint64_t kernel_object;
55 uint64_t kernarg_address;
56 uint64_t reserved2;
57 };
58
59 static const amd_kernel_code_t *si_compute_get_code_object(
60 const struct si_compute *program,
61 uint64_t symbol_offset)
62 {
63 const struct si_shader_selector *sel = &program->sel;
64
65 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
66 return NULL;
67
68 struct ac_rtld_binary rtld;
69 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
70 .info = &sel->screen->info,
71 .shader_type = MESA_SHADER_COMPUTE,
72 .wave_size = sel->screen->compute_wave_size,
73 .num_parts = 1,
74 .elf_ptrs = &program->shader.binary.elf_buffer,
75 .elf_sizes = &program->shader.binary.elf_size }))
76 return NULL;
77
78 const amd_kernel_code_t *result = NULL;
79 const char *text;
80 size_t size;
81 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
82 goto out;
83
84 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
85 goto out;
86
87 result = (const amd_kernel_code_t*)(text + symbol_offset);
88
89 out:
90 ac_rtld_close(&rtld);
91 return result;
92 }
93
94 static void code_object_to_config(const amd_kernel_code_t *code_object,
95 struct ac_shader_config *out_config) {
96
97 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
98 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
99 out_config->num_sgprs = code_object->wavefront_sgpr_count;
100 out_config->num_vgprs = code_object->workitem_vgpr_count;
101 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
102 out_config->rsrc1 = rsrc1;
103 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
104 out_config->rsrc2 = rsrc2;
105 out_config->scratch_bytes_per_wave =
106 align(code_object->workitem_private_segment_byte_size * 64, 1024);
107 }
108
109 /* Asynchronous compute shader compilation. */
110 static void si_create_compute_state_async(void *job, int thread_index)
111 {
112 struct si_compute *program = (struct si_compute *)job;
113 struct si_shader_selector *sel = &program->sel;
114 struct si_shader *shader = &program->shader;
115 struct ac_llvm_compiler *compiler;
116 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
117 struct si_screen *sscreen = sel->screen;
118
119 assert(!debug->debug_message || debug->async);
120 assert(thread_index >= 0);
121 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
122 compiler = &sscreen->compiler[thread_index];
123
124 if (!compiler->passes)
125 si_init_compiler(sscreen, compiler);
126
127 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
128 tgsi_scan_shader(sel->tokens, &sel->info);
129 } else {
130 assert(program->ir_type == PIPE_SHADER_IR_NIR);
131
132 si_nir_scan_shader(sel->nir, &sel->info);
133 }
134
135 /* Store the declared LDS size into tgsi_shader_info for the shader
136 * cache to include it.
137 */
138 sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
139
140 si_get_active_slot_masks(&sel->info,
141 &sel->active_const_and_shader_buffers,
142 &sel->active_samplers_and_images);
143
144 program->shader.is_monolithic = true;
145 program->reads_variable_block_size =
146 sel->info.uses_block_size &&
147 sel->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
148 program->num_cs_user_data_dwords =
149 sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
150
151 unsigned char ir_sha1_cache_key[20];
152 si_get_ir_cache_key(sel, false, false, ir_sha1_cache_key);
153
154 /* Try to load the shader from the shader cache. */
155 simple_mtx_lock(&sscreen->shader_cache_mutex);
156
157 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
158 simple_mtx_unlock(&sscreen->shader_cache_mutex);
159
160 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
161 si_shader_dump(sscreen, shader, debug, stderr, true);
162
163 if (!si_shader_binary_upload(sscreen, shader, 0))
164 program->shader.compilation_failed = true;
165 } else {
166 simple_mtx_unlock(&sscreen->shader_cache_mutex);
167
168 if (!si_shader_create(sscreen, compiler, &program->shader, debug)) {
169 program->shader.compilation_failed = true;
170
171 if (program->ir_type == PIPE_SHADER_IR_TGSI)
172 FREE(sel->tokens);
173 return;
174 }
175
176 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
177 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
178 (sel->info.uses_grid_size ? 3 : 0) +
179 (program->reads_variable_block_size ? 3 : 0) +
180 program->num_cs_user_data_dwords;
181
182 shader->config.rsrc1 =
183 S_00B848_VGPRS((shader->config.num_vgprs - 1) /
184 (sscreen->compute_wave_size == 32 ? 8 : 4)) |
185 S_00B848_DX10_CLAMP(1) |
186 S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
187 S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
188 S_00B848_FLOAT_MODE(shader->config.float_mode);
189
190 if (sscreen->info.chip_class < GFX10) {
191 shader->config.rsrc1 |=
192 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
193 }
194
195 shader->config.rsrc2 =
196 S_00B84C_USER_SGPR(user_sgprs) |
197 S_00B84C_SCRATCH_EN(scratch_enabled) |
198 S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
199 S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
200 S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
201 S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2] ? 2 :
202 sel->info.uses_thread_id[1] ? 1 : 0) |
203 S_00B84C_LDS_SIZE(shader->config.lds_size);
204
205 simple_mtx_lock(&sscreen->shader_cache_mutex);
206 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
207 shader, true);
208 simple_mtx_unlock(&sscreen->shader_cache_mutex);
209 }
210
211 FREE(sel->tokens);
212 sel->tokens = NULL;
213 ralloc_free(sel->nir);
214 sel->nir = NULL;
215 }
216
217 static void *si_create_compute_state(
218 struct pipe_context *ctx,
219 const struct pipe_compute_state *cso)
220 {
221 struct si_context *sctx = (struct si_context *)ctx;
222 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
223 struct si_compute *program = CALLOC_STRUCT(si_compute);
224 struct si_shader_selector *sel = &program->sel;
225
226 pipe_reference_init(&sel->reference, 1);
227 sel->type = PIPE_SHADER_COMPUTE;
228 sel->screen = sscreen;
229 program->shader.selector = &program->sel;
230 program->ir_type = cso->ir_type;
231 program->local_size = cso->req_local_mem;
232 program->private_size = cso->req_private_mem;
233 program->input_size = cso->req_input_mem;
234
235 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
236 if (sscreen->options.enable_nir &&
237 cso->ir_type == PIPE_SHADER_IR_TGSI) {
238 program->ir_type = PIPE_SHADER_IR_NIR;
239 sel->nir = tgsi_to_nir(cso->prog, ctx->screen);
240 } else if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
241 sel->tokens = tgsi_dup_tokens(cso->prog);
242 if (!sel->tokens) {
243 FREE(program);
244 return NULL;
245 }
246 } else {
247 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
248 sel->nir = (struct nir_shader *) cso->prog;
249 }
250
251 sel->compiler_ctx_state.debug = sctx->debug;
252 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
253 p_atomic_inc(&sscreen->num_shaders_created);
254
255 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
256 &sel->ready,
257 &sel->compiler_ctx_state,
258 program, si_create_compute_state_async);
259 } else {
260 const struct pipe_binary_program_header *header;
261 header = cso->prog;
262
263 program->shader.binary.elf_size = header->num_bytes;
264 program->shader.binary.elf_buffer = malloc(header->num_bytes);
265 if (!program->shader.binary.elf_buffer) {
266 FREE(program);
267 return NULL;
268 }
269 memcpy((void *)program->shader.binary.elf_buffer, header->blob, header->num_bytes);
270
271 const amd_kernel_code_t *code_object =
272 si_compute_get_code_object(program, 0);
273 code_object_to_config(code_object, &program->shader.config);
274
275 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
276 if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
277 fprintf(stderr, "LLVM failed to upload shader\n");
278 free((void *)program->shader.binary.elf_buffer);
279 FREE(program);
280 return NULL;
281 }
282 }
283
284 return program;
285 }
286
287 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
288 {
289 struct si_context *sctx = (struct si_context*)ctx;
290 struct si_compute *program = (struct si_compute*)state;
291 struct si_shader_selector *sel = &program->sel;
292
293 sctx->cs_shader_state.program = program;
294 if (!program)
295 return;
296
297 /* Wait because we need active slot usage masks. */
298 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
299 util_queue_fence_wait(&sel->ready);
300
301 si_set_active_descriptors(sctx,
302 SI_DESCS_FIRST_COMPUTE +
303 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
304 sel->active_const_and_shader_buffers);
305 si_set_active_descriptors(sctx,
306 SI_DESCS_FIRST_COMPUTE +
307 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
308 sel->active_samplers_and_images);
309 }
310
311 static void si_set_global_binding(
312 struct pipe_context *ctx, unsigned first, unsigned n,
313 struct pipe_resource **resources,
314 uint32_t **handles)
315 {
316 unsigned i;
317 struct si_context *sctx = (struct si_context*)ctx;
318 struct si_compute *program = sctx->cs_shader_state.program;
319
320 if (first + n > program->max_global_buffers) {
321 unsigned old_max = program->max_global_buffers;
322 program->max_global_buffers = first + n;
323 program->global_buffers =
324 realloc(program->global_buffers,
325 program->max_global_buffers *
326 sizeof(program->global_buffers[0]));
327 if (!program->global_buffers) {
328 fprintf(stderr, "radeonsi: failed to allocate compute global_buffers\n");
329 return;
330 }
331
332 memset(&program->global_buffers[old_max], 0,
333 (program->max_global_buffers - old_max) *
334 sizeof(program->global_buffers[0]));
335 }
336
337 if (!resources) {
338 for (i = 0; i < n; i++) {
339 pipe_resource_reference(&program->global_buffers[first + i], NULL);
340 }
341 return;
342 }
343
344 for (i = 0; i < n; i++) {
345 uint64_t va;
346 uint32_t offset;
347 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
348 va = si_resource(resources[i])->gpu_address;
349 offset = util_le32_to_cpu(*handles[i]);
350 va += offset;
351 va = util_cpu_to_le64(va);
352 memcpy(handles[i], &va, sizeof(va));
353 }
354 }
355
356 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
357 {
358 uint64_t bc_va;
359
360 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
361 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
362 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
363 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
364 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
365
366 if (sctx->chip_class >= GFX7) {
367 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
368 radeon_set_sh_reg_seq(cs,
369 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
370 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
371 S_00B858_SH1_CU_EN(0xffff));
372 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
373 S_00B858_SH1_CU_EN(0xffff));
374 }
375
376 if (sctx->chip_class >= GFX10)
377 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
378
379 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
380 * and is now per pipe, so it should be handled in the
381 * kernel if we want to use something other than the default value,
382 * which is now 0x22f.
383 */
384 if (sctx->chip_class <= GFX6) {
385 /* XXX: This should be:
386 * (number of compute units) * 4 * (waves per simd) - 1 */
387
388 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
389 0x190 /* Default value */);
390 }
391
392 /* Set the pointer to border colors. */
393 bc_va = sctx->border_color_buffer->gpu_address;
394
395 if (sctx->chip_class >= GFX7) {
396 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
397 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
398 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
399 } else {
400 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
401 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
402 bc_va >> 8);
403 }
404 }
405 }
406
407 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
408 struct si_shader *shader,
409 struct ac_shader_config *config)
410 {
411 uint64_t scratch_bo_size, scratch_needed;
412 scratch_bo_size = 0;
413 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
414 if (sctx->compute_scratch_buffer)
415 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
416
417 if (scratch_bo_size < scratch_needed) {
418 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
419
420 sctx->compute_scratch_buffer =
421 si_aligned_buffer_create(&sctx->screen->b,
422 SI_RESOURCE_FLAG_UNMAPPABLE,
423 PIPE_USAGE_DEFAULT,
424 scratch_needed,
425 sctx->screen->info.pte_fragment_size);
426
427 if (!sctx->compute_scratch_buffer)
428 return false;
429 }
430
431 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
432 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
433
434 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
435 return false;
436
437 si_resource_reference(&shader->scratch_bo,
438 sctx->compute_scratch_buffer);
439 }
440
441 return true;
442 }
443
444 static bool si_switch_compute_shader(struct si_context *sctx,
445 struct si_compute *program,
446 struct si_shader *shader,
447 const amd_kernel_code_t *code_object,
448 unsigned offset)
449 {
450 struct radeon_cmdbuf *cs = sctx->gfx_cs;
451 struct ac_shader_config inline_config = {0};
452 struct ac_shader_config *config;
453 uint64_t shader_va;
454
455 if (sctx->cs_shader_state.emitted_program == program &&
456 sctx->cs_shader_state.offset == offset)
457 return true;
458
459 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
460 config = &shader->config;
461 } else {
462 unsigned lds_blocks;
463
464 config = &inline_config;
465 code_object_to_config(code_object, config);
466
467 lds_blocks = config->lds_size;
468 /* XXX: We are over allocating LDS. For GFX6, the shader reports
469 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
470 * allocated in the shader and 4 bytes allocated by the state
471 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
472 */
473 if (sctx->chip_class <= GFX6) {
474 lds_blocks += align(program->local_size, 256) >> 8;
475 } else {
476 lds_blocks += align(program->local_size, 512) >> 9;
477 }
478
479 /* TODO: use si_multiwave_lds_size_workaround */
480 assert(lds_blocks <= 0xFF);
481
482 config->rsrc2 &= C_00B84C_LDS_SIZE;
483 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
484 }
485
486 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
487 return false;
488
489 if (shader->scratch_bo) {
490 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
491 "Total Scratch: %u bytes\n", sctx->scratch_waves,
492 config->scratch_bytes_per_wave,
493 config->scratch_bytes_per_wave *
494 sctx->scratch_waves);
495
496 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
497 shader->scratch_bo, RADEON_USAGE_READWRITE,
498 RADEON_PRIO_SCRATCH_BUFFER);
499 }
500
501 /* Prefetch the compute shader to TC L2.
502 *
503 * We should also prefetch graphics shaders if a compute dispatch was
504 * the last command, and the compute shader if a draw call was the last
505 * command. However, that would add more complexity and we're likely
506 * to get a shader state change in that case anyway.
507 */
508 if (sctx->chip_class >= GFX7) {
509 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
510 0, program->shader.bo->b.b.width0);
511 }
512
513 shader_va = shader->bo->gpu_address + offset;
514 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
515 /* Shader code is placed after the amd_kernel_code_t
516 * struct. */
517 shader_va += sizeof(amd_kernel_code_t);
518 }
519
520 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
521 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
522
523 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
524 radeon_emit(cs, shader_va >> 8);
525 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
526
527 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
528 radeon_emit(cs, config->rsrc1);
529 radeon_emit(cs, config->rsrc2);
530
531 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
532 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
533
534 sctx->max_seen_compute_scratch_bytes_per_wave =
535 MAX2(sctx->max_seen_compute_scratch_bytes_per_wave,
536 config->scratch_bytes_per_wave);
537
538 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
539 S_00B860_WAVES(sctx->scratch_waves)
540 | S_00B860_WAVESIZE(sctx->max_seen_compute_scratch_bytes_per_wave >> 10));
541
542 sctx->cs_shader_state.emitted_program = program;
543 sctx->cs_shader_state.offset = offset;
544 sctx->cs_shader_state.uses_scratch =
545 config->scratch_bytes_per_wave != 0;
546
547 return true;
548 }
549
550 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
551 const amd_kernel_code_t *code_object,
552 unsigned user_sgpr)
553 {
554 struct radeon_cmdbuf *cs = sctx->gfx_cs;
555 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
556
557 unsigned max_private_element_size = AMD_HSA_BITS_GET(
558 code_object->code_properties,
559 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
560
561 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
562 uint32_t scratch_dword1 =
563 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
564 S_008F04_SWIZZLE_ENABLE(1);
565
566 /* Disable address clamping */
567 uint32_t scratch_dword2 = 0xffffffff;
568 uint32_t scratch_dword3 =
569 S_008F0C_INDEX_STRIDE(3) |
570 S_008F0C_ADD_TID_ENABLE(1);
571
572 if (sctx->chip_class >= GFX9) {
573 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
574 } else {
575 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
576
577 if (sctx->chip_class < GFX8) {
578 /* BUF_DATA_FORMAT is ignored, but it cannot be
579 * BUF_DATA_FORMAT_INVALID. */
580 scratch_dword3 |=
581 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
582 }
583 }
584
585 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
586 (user_sgpr * 4), 4);
587 radeon_emit(cs, scratch_dword0);
588 radeon_emit(cs, scratch_dword1);
589 radeon_emit(cs, scratch_dword2);
590 radeon_emit(cs, scratch_dword3);
591 }
592
593 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
594 const amd_kernel_code_t *code_object,
595 const struct pipe_grid_info *info,
596 uint64_t kernel_args_va)
597 {
598 struct si_compute *program = sctx->cs_shader_state.program;
599 struct radeon_cmdbuf *cs = sctx->gfx_cs;
600
601 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
602 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
603 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
604 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
605 };
606
607 unsigned i, user_sgpr = 0;
608 if (AMD_HSA_BITS_GET(code_object->code_properties,
609 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
610 if (code_object->workitem_private_segment_byte_size > 0) {
611 setup_scratch_rsrc_user_sgprs(sctx, code_object,
612 user_sgpr);
613 }
614 user_sgpr += 4;
615 }
616
617 if (AMD_HSA_BITS_GET(code_object->code_properties,
618 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
619 struct dispatch_packet dispatch;
620 unsigned dispatch_offset;
621 struct si_resource *dispatch_buf = NULL;
622 uint64_t dispatch_va;
623
624 /* Upload dispatch ptr */
625 memset(&dispatch, 0, sizeof(dispatch));
626
627 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
628 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
629 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
630
631 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
632 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
633 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
634
635 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
636 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
637
638 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
639
640 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
641 256, &dispatch, &dispatch_offset,
642 (struct pipe_resource**)&dispatch_buf);
643
644 if (!dispatch_buf) {
645 fprintf(stderr, "Error: Failed to allocate dispatch "
646 "packet.");
647 }
648 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
649 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
650
651 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
652
653 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
654 (user_sgpr * 4), 2);
655 radeon_emit(cs, dispatch_va);
656 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
657 S_008F04_STRIDE(0));
658
659 si_resource_reference(&dispatch_buf, NULL);
660 user_sgpr += 2;
661 }
662
663 if (AMD_HSA_BITS_GET(code_object->code_properties,
664 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
665 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
666 (user_sgpr * 4), 2);
667 radeon_emit(cs, kernel_args_va);
668 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
669 S_008F04_STRIDE(0));
670 user_sgpr += 2;
671 }
672
673 for (i = 0; i < 3 && user_sgpr < 16; i++) {
674 if (code_object->code_properties & workgroup_count_masks[i]) {
675 radeon_set_sh_reg_seq(cs,
676 R_00B900_COMPUTE_USER_DATA_0 +
677 (user_sgpr * 4), 1);
678 radeon_emit(cs, info->grid[i]);
679 user_sgpr += 1;
680 }
681 }
682 }
683
684 static bool si_upload_compute_input(struct si_context *sctx,
685 const amd_kernel_code_t *code_object,
686 const struct pipe_grid_info *info)
687 {
688 struct si_compute *program = sctx->cs_shader_state.program;
689 struct si_resource *input_buffer = NULL;
690 uint32_t kernel_args_offset = 0;
691 uint32_t *kernel_args;
692 void *kernel_args_ptr;
693 uint64_t kernel_args_va;
694
695 u_upload_alloc(sctx->b.const_uploader, 0, program->input_size,
696 sctx->screen->info.tcc_cache_line_size,
697 &kernel_args_offset,
698 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
699
700 if (unlikely(!kernel_args_ptr))
701 return false;
702
703 kernel_args = (uint32_t*)kernel_args_ptr;
704 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
705
706 memcpy(kernel_args, info->input, program->input_size);
707
708 for (unsigned i = 0; i < program->input_size / 4; i++) {
709 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
710 kernel_args[i]);
711 }
712
713 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
714 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
715
716 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
717 si_resource_reference(&input_buffer, NULL);
718 return true;
719 }
720
721 static void si_setup_tgsi_user_data(struct si_context *sctx,
722 const struct pipe_grid_info *info)
723 {
724 struct si_compute *program = sctx->cs_shader_state.program;
725 struct si_shader_selector *sel = &program->sel;
726 struct radeon_cmdbuf *cs = sctx->gfx_cs;
727 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
728 4 * SI_NUM_RESOURCE_SGPRS;
729 unsigned block_size_reg = grid_size_reg +
730 /* 12 bytes = 3 dwords. */
731 12 * sel->info.uses_grid_size;
732 unsigned cs_user_data_reg = block_size_reg +
733 12 * program->reads_variable_block_size;
734
735 if (info->indirect) {
736 if (sel->info.uses_grid_size) {
737 for (unsigned i = 0; i < 3; ++i) {
738 si_cp_copy_data(sctx, sctx->gfx_cs,
739 COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
740 COPY_DATA_SRC_MEM, si_resource(info->indirect),
741 info->indirect_offset + 4 * i);
742 }
743 }
744 } else {
745 if (sel->info.uses_grid_size) {
746 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
747 radeon_emit(cs, info->grid[0]);
748 radeon_emit(cs, info->grid[1]);
749 radeon_emit(cs, info->grid[2]);
750 }
751 if (program->reads_variable_block_size) {
752 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
753 radeon_emit(cs, info->block[0]);
754 radeon_emit(cs, info->block[1]);
755 radeon_emit(cs, info->block[2]);
756 }
757 }
758
759 if (program->num_cs_user_data_dwords) {
760 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
761 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
762 }
763 }
764
765 static void si_emit_dispatch_packets(struct si_context *sctx,
766 const struct pipe_grid_info *info)
767 {
768 struct si_screen *sscreen = sctx->screen;
769 struct radeon_cmdbuf *cs = sctx->gfx_cs;
770 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
771 unsigned threads_per_threadgroup =
772 info->block[0] * info->block[1] * info->block[2];
773 unsigned waves_per_threadgroup =
774 DIV_ROUND_UP(threads_per_threadgroup, sscreen->compute_wave_size);
775 unsigned threadgroups_per_cu = 1;
776
777 if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1)
778 threadgroups_per_cu = 2;
779
780 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
781 ac_get_compute_resource_limits(&sscreen->info,
782 waves_per_threadgroup,
783 sctx->cs_max_waves_per_sh,
784 threadgroups_per_cu));
785
786 unsigned dispatch_initiator =
787 S_00B800_COMPUTE_SHADER_EN(1) |
788 S_00B800_FORCE_START_AT_000(1) |
789 /* If the KMD allows it (there is a KMD hw register for it),
790 * allow launching waves out-of-order. (same as Vulkan) */
791 S_00B800_ORDER_MODE(sctx->chip_class >= GFX7) |
792 S_00B800_CS_W32_EN(sscreen->compute_wave_size == 32);
793
794 const uint *last_block = info->last_block;
795 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
796
797 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
798
799 if (partial_block_en) {
800 unsigned partial[3];
801
802 /* If no partial_block, these should be an entire block size, not 0. */
803 partial[0] = last_block[0] ? last_block[0] : info->block[0];
804 partial[1] = last_block[1] ? last_block[1] : info->block[1];
805 partial[2] = last_block[2] ? last_block[2] : info->block[2];
806
807 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
808 S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
809 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
810 S_00B820_NUM_THREAD_PARTIAL(partial[1]));
811 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
812 S_00B824_NUM_THREAD_PARTIAL(partial[2]));
813
814 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
815 } else {
816 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
817 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
818 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
819 }
820
821 if (info->indirect) {
822 uint64_t base_va = si_resource(info->indirect)->gpu_address;
823
824 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
825 si_resource(info->indirect),
826 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
827
828 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
829 PKT3_SHADER_TYPE_S(1));
830 radeon_emit(cs, 1);
831 radeon_emit(cs, base_va);
832 radeon_emit(cs, base_va >> 32);
833
834 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
835 PKT3_SHADER_TYPE_S(1));
836 radeon_emit(cs, info->indirect_offset);
837 radeon_emit(cs, dispatch_initiator);
838 } else {
839 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
840 PKT3_SHADER_TYPE_S(1));
841 radeon_emit(cs, info->grid[0]);
842 radeon_emit(cs, info->grid[1]);
843 radeon_emit(cs, info->grid[2]);
844 radeon_emit(cs, dispatch_initiator);
845 }
846 }
847
848
849 static void si_launch_grid(
850 struct pipe_context *ctx, const struct pipe_grid_info *info)
851 {
852 struct si_context *sctx = (struct si_context*)ctx;
853 struct si_compute *program = sctx->cs_shader_state.program;
854 const amd_kernel_code_t *code_object =
855 si_compute_get_code_object(program, info->pc);
856 int i;
857 /* HW bug workaround when CS threadgroups > 256 threads and async
858 * compute isn't used, i.e. only one compute job can run at a time.
859 * If async compute is possible, the threadgroup size must be limited
860 * to 256 threads on all queues to avoid the bug.
861 * Only GFX6 and certain GFX7 chips are affected.
862 */
863 bool cs_regalloc_hang =
864 (sctx->chip_class == GFX6 ||
865 sctx->family == CHIP_BONAIRE ||
866 sctx->family == CHIP_KABINI) &&
867 info->block[0] * info->block[1] * info->block[2] > 256;
868
869 if (cs_regalloc_hang)
870 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
871 SI_CONTEXT_CS_PARTIAL_FLUSH;
872
873 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
874 program->shader.compilation_failed)
875 return;
876
877 if (sctx->has_graphics) {
878 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
879 si_update_fb_dirtiness_after_rendering(sctx);
880 sctx->last_num_draw_calls = sctx->num_draw_calls;
881 }
882
883 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
884 }
885
886 /* Add buffer sizes for memory checking in need_cs_space. */
887 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
888 /* TODO: add the scratch buffer */
889
890 if (info->indirect) {
891 si_context_add_resource_size(sctx, info->indirect);
892
893 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
894 if (sctx->chip_class <= GFX8 &&
895 si_resource(info->indirect)->TC_L2_dirty) {
896 sctx->flags |= SI_CONTEXT_WB_L2;
897 si_resource(info->indirect)->TC_L2_dirty = false;
898 }
899 }
900
901 si_need_gfx_cs_space(sctx);
902
903 if (sctx->bo_list_add_all_compute_resources)
904 si_compute_resources_add_all_to_bo_list(sctx);
905
906 if (!sctx->cs_shader_state.initialized) {
907 si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
908
909 sctx->cs_shader_state.emitted_program = NULL;
910 sctx->cs_shader_state.initialized = true;
911 }
912
913 if (sctx->flags)
914 sctx->emit_cache_flush(sctx);
915
916 if (!si_switch_compute_shader(sctx, program, &program->shader,
917 code_object, info->pc))
918 return;
919
920 si_upload_compute_shader_descriptors(sctx);
921 si_emit_compute_shader_pointers(sctx);
922
923 if (sctx->has_graphics &&
924 si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
925 sctx->atoms.s.render_cond.emit(sctx);
926 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
927 }
928
929 if (program->ir_type == PIPE_SHADER_IR_NATIVE &&
930 unlikely(!si_upload_compute_input(sctx, code_object, info)))
931 return;
932
933 /* Global buffers */
934 for (i = 0; i < program->max_global_buffers; i++) {
935 struct si_resource *buffer =
936 si_resource(program->global_buffers[i]);
937 if (!buffer) {
938 continue;
939 }
940 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
941 RADEON_USAGE_READWRITE,
942 RADEON_PRIO_COMPUTE_GLOBAL);
943 }
944
945 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
946 si_setup_tgsi_user_data(sctx, info);
947
948 si_emit_dispatch_packets(sctx, info);
949
950 if (unlikely(sctx->current_saved_cs)) {
951 si_trace_emit(sctx);
952 si_log_compute_state(sctx, sctx->log);
953 }
954
955 sctx->compute_is_busy = true;
956 sctx->num_compute_calls++;
957 if (sctx->cs_shader_state.uses_scratch)
958 sctx->num_spill_compute_calls++;
959
960 if (cs_regalloc_hang)
961 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
962 }
963
964 void si_destroy_compute(struct si_compute *program)
965 {
966 struct si_shader_selector *sel = &program->sel;
967
968 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
969 util_queue_drop_job(&sel->screen->shader_compiler_queue,
970 &sel->ready);
971 util_queue_fence_destroy(&sel->ready);
972 }
973
974 for (unsigned i = 0; i < program->max_global_buffers; i++)
975 pipe_resource_reference(&program->global_buffers[i], NULL);
976 FREE(program->global_buffers);
977
978 si_shader_destroy(&program->shader);
979 FREE(program->sel.tokens);
980 ralloc_free(program->sel.nir);
981 FREE(program);
982 }
983
984 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
985 struct si_compute *program = (struct si_compute *)state;
986 struct si_context *sctx = (struct si_context*)ctx;
987
988 if (!state)
989 return;
990
991 if (program == sctx->cs_shader_state.program)
992 sctx->cs_shader_state.program = NULL;
993
994 if (program == sctx->cs_shader_state.emitted_program)
995 sctx->cs_shader_state.emitted_program = NULL;
996
997 si_compute_reference(&program, NULL);
998 }
999
1000 static void si_set_compute_resources(struct pipe_context * ctx_,
1001 unsigned start, unsigned count,
1002 struct pipe_surface ** surfaces) { }
1003
1004 void si_init_compute_functions(struct si_context *sctx)
1005 {
1006 sctx->b.create_compute_state = si_create_compute_state;
1007 sctx->b.delete_compute_state = si_delete_compute_state;
1008 sctx->b.bind_compute_state = si_bind_compute_state;
1009 sctx->b.set_compute_resources = si_set_compute_resources;
1010 sctx->b.set_global_binding = si_set_global_binding;
1011 sctx->b.launch_grid = si_launch_grid;
1012 }