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radeonsi: remove si_program::use_code_object_v2
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "tgsi/tgsi_parse.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30
31 #include "ac_rtld.h"
32 #include "amd_kernel_code_t.h"
33 #include "si_build_pm4.h"
34 #include "si_compute.h"
35
36 #define COMPUTE_DBG(sscreen, fmt, args...) \
37 do { \
38 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
39 } while (0);
40
41 struct dispatch_packet {
42 uint16_t header;
43 uint16_t setup;
44 uint16_t workgroup_size_x;
45 uint16_t workgroup_size_y;
46 uint16_t workgroup_size_z;
47 uint16_t reserved0;
48 uint32_t grid_size_x;
49 uint32_t grid_size_y;
50 uint32_t grid_size_z;
51 uint32_t private_segment_size;
52 uint32_t group_segment_size;
53 uint64_t kernel_object;
54 uint64_t kernarg_address;
55 uint64_t reserved2;
56 };
57
58 static const amd_kernel_code_t *si_compute_get_code_object(
59 const struct si_compute *program,
60 uint64_t symbol_offset)
61 {
62 const struct si_shader_selector *sel = &program->sel;
63
64 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
65 return NULL;
66
67 struct ac_rtld_binary rtld;
68 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
69 .info = &sel->screen->info,
70 .shader_type = MESA_SHADER_COMPUTE,
71 .num_parts = 1,
72 .elf_ptrs = &program->shader.binary.elf_buffer,
73 .elf_sizes = &program->shader.binary.elf_size }))
74 return NULL;
75
76 const amd_kernel_code_t *result = NULL;
77 const char *text;
78 size_t size;
79 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
80 goto out;
81
82 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
83 goto out;
84
85 result = (const amd_kernel_code_t*)(text + symbol_offset);
86
87 out:
88 ac_rtld_close(&rtld);
89 return result;
90 }
91
92 static void code_object_to_config(const amd_kernel_code_t *code_object,
93 struct ac_shader_config *out_config) {
94
95 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
96 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
97 out_config->num_sgprs = code_object->wavefront_sgpr_count;
98 out_config->num_vgprs = code_object->workitem_vgpr_count;
99 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
100 out_config->rsrc1 = rsrc1;
101 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
102 out_config->rsrc2 = rsrc2;
103 out_config->scratch_bytes_per_wave =
104 align(code_object->workitem_private_segment_byte_size * 64, 1024);
105 }
106
107 /* Asynchronous compute shader compilation. */
108 static void si_create_compute_state_async(void *job, int thread_index)
109 {
110 struct si_compute *program = (struct si_compute *)job;
111 struct si_shader_selector *sel = &program->sel;
112 struct si_shader *shader = &program->shader;
113 struct ac_llvm_compiler *compiler;
114 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
115 struct si_screen *sscreen = sel->screen;
116
117 assert(!debug->debug_message || debug->async);
118 assert(thread_index >= 0);
119 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
120 compiler = &sscreen->compiler[thread_index];
121
122 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
123 tgsi_scan_shader(sel->tokens, &sel->info);
124 } else {
125 assert(program->ir_type == PIPE_SHADER_IR_NIR);
126
127 si_nir_opts(sel->nir);
128 si_nir_scan_shader(sel->nir, &sel->info);
129 si_lower_nir(sel);
130 }
131
132 /* Store the declared LDS size into tgsi_shader_info for the shader
133 * cache to include it.
134 */
135 sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
136
137 si_get_active_slot_masks(&sel->info,
138 &sel->active_const_and_shader_buffers,
139 &sel->active_samplers_and_images);
140
141 program->shader.is_monolithic = true;
142 program->reads_variable_block_size =
143 sel->info.uses_block_size &&
144 sel->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
145 program->num_cs_user_data_dwords =
146 sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
147
148 void *ir_binary = si_get_ir_binary(sel);
149
150 /* Try to load the shader from the shader cache. */
151 mtx_lock(&sscreen->shader_cache_mutex);
152
153 if (ir_binary &&
154 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
155 mtx_unlock(&sscreen->shader_cache_mutex);
156
157 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
158 si_shader_dump(sscreen, shader, debug, stderr, true);
159
160 if (!si_shader_binary_upload(sscreen, shader, 0))
161 program->shader.compilation_failed = true;
162 } else {
163 mtx_unlock(&sscreen->shader_cache_mutex);
164
165 if (!si_shader_create(sscreen, compiler, &program->shader, debug)) {
166 program->shader.compilation_failed = true;
167
168 if (program->ir_type == PIPE_SHADER_IR_TGSI)
169 FREE(sel->tokens);
170 return;
171 }
172
173 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
174 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
175 (sel->info.uses_grid_size ? 3 : 0) +
176 (program->reads_variable_block_size ? 3 : 0) +
177 program->num_cs_user_data_dwords;
178
179 shader->config.rsrc1 =
180 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
181 S_00B848_DX10_CLAMP(1) |
182 S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
183 S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
184 S_00B848_FLOAT_MODE(shader->config.float_mode);
185
186 if (sscreen->info.chip_class < GFX10) {
187 shader->config.rsrc1 |=
188 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
189 }
190
191 shader->config.rsrc2 =
192 S_00B84C_USER_SGPR(user_sgprs) |
193 S_00B84C_SCRATCH_EN(scratch_enabled) |
194 S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
195 S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
196 S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
197 S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2] ? 2 :
198 sel->info.uses_thread_id[1] ? 1 : 0) |
199 S_00B84C_LDS_SIZE(shader->config.lds_size);
200
201 if (ir_binary) {
202 mtx_lock(&sscreen->shader_cache_mutex);
203 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
204 FREE(ir_binary);
205 mtx_unlock(&sscreen->shader_cache_mutex);
206 }
207 }
208
209 if (program->ir_type == PIPE_SHADER_IR_TGSI)
210 FREE(sel->tokens);
211 }
212
213 static void *si_create_compute_state(
214 struct pipe_context *ctx,
215 const struct pipe_compute_state *cso)
216 {
217 struct si_context *sctx = (struct si_context *)ctx;
218 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
219 struct si_compute *program = CALLOC_STRUCT(si_compute);
220 struct si_shader_selector *sel = &program->sel;
221
222 pipe_reference_init(&sel->reference, 1);
223 sel->type = PIPE_SHADER_COMPUTE;
224 sel->screen = sscreen;
225 program->shader.selector = &program->sel;
226 program->ir_type = cso->ir_type;
227 program->local_size = cso->req_local_mem;
228 program->private_size = cso->req_private_mem;
229 program->input_size = cso->req_input_mem;
230
231 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
232 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
233 sel->tokens = tgsi_dup_tokens(cso->prog);
234 if (!sel->tokens) {
235 FREE(program);
236 return NULL;
237 }
238 } else {
239 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
240 sel->nir = (struct nir_shader *) cso->prog;
241 }
242
243 sel->compiler_ctx_state.debug = sctx->debug;
244 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
245 p_atomic_inc(&sscreen->num_shaders_created);
246
247 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
248 &sel->ready,
249 &sel->compiler_ctx_state,
250 program, si_create_compute_state_async);
251 } else {
252 const struct pipe_llvm_program_header *header;
253 const char *code;
254 header = cso->prog;
255 code = cso->prog + sizeof(struct pipe_llvm_program_header);
256
257 program->shader.binary.elf_size = header->num_bytes;
258 program->shader.binary.elf_buffer = malloc(header->num_bytes);
259 if (!program->shader.binary.elf_buffer) {
260 FREE(program);
261 return NULL;
262 }
263 memcpy((void *)program->shader.binary.elf_buffer, code, header->num_bytes);
264
265 const amd_kernel_code_t *code_object =
266 si_compute_get_code_object(program, 0);
267 code_object_to_config(code_object, &program->shader.config);
268
269 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
270 if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
271 fprintf(stderr, "LLVM failed to upload shader\n");
272 free((void *)program->shader.binary.elf_buffer);
273 FREE(program);
274 return NULL;
275 }
276 }
277
278 return program;
279 }
280
281 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
282 {
283 struct si_context *sctx = (struct si_context*)ctx;
284 struct si_compute *program = (struct si_compute*)state;
285 struct si_shader_selector *sel = &program->sel;
286
287 sctx->cs_shader_state.program = program;
288 if (!program)
289 return;
290
291 /* Wait because we need active slot usage masks. */
292 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
293 util_queue_fence_wait(&sel->ready);
294
295 si_set_active_descriptors(sctx,
296 SI_DESCS_FIRST_COMPUTE +
297 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
298 sel->active_const_and_shader_buffers);
299 si_set_active_descriptors(sctx,
300 SI_DESCS_FIRST_COMPUTE +
301 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
302 sel->active_samplers_and_images);
303 }
304
305 static void si_set_global_binding(
306 struct pipe_context *ctx, unsigned first, unsigned n,
307 struct pipe_resource **resources,
308 uint32_t **handles)
309 {
310 unsigned i;
311 struct si_context *sctx = (struct si_context*)ctx;
312 struct si_compute *program = sctx->cs_shader_state.program;
313
314 assert(first + n <= MAX_GLOBAL_BUFFERS);
315
316 if (!resources) {
317 for (i = 0; i < n; i++) {
318 pipe_resource_reference(&program->global_buffers[first + i], NULL);
319 }
320 return;
321 }
322
323 for (i = 0; i < n; i++) {
324 uint64_t va;
325 uint32_t offset;
326 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
327 va = si_resource(resources[i])->gpu_address;
328 offset = util_le32_to_cpu(*handles[i]);
329 va += offset;
330 va = util_cpu_to_le64(va);
331 memcpy(handles[i], &va, sizeof(va));
332 }
333 }
334
335 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
336 {
337 uint64_t bc_va;
338
339 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
340 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
341 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
342 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
343 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
344
345 if (sctx->chip_class >= GFX7) {
346 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
347 radeon_set_sh_reg_seq(cs,
348 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
349 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
350 S_00B858_SH1_CU_EN(0xffff));
351 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
352 S_00B858_SH1_CU_EN(0xffff));
353 }
354
355 if (sctx->chip_class >= GFX10)
356 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
357
358 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
359 * and is now per pipe, so it should be handled in the
360 * kernel if we want to use something other than the default value,
361 * which is now 0x22f.
362 */
363 if (sctx->chip_class <= GFX6) {
364 /* XXX: This should be:
365 * (number of compute units) * 4 * (waves per simd) - 1 */
366
367 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
368 0x190 /* Default value */);
369 }
370
371 /* Set the pointer to border colors. */
372 bc_va = sctx->border_color_buffer->gpu_address;
373
374 if (sctx->chip_class >= GFX7) {
375 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
376 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
377 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
378 } else {
379 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
380 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
381 bc_va >> 8);
382 }
383 }
384 }
385
386 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
387 struct si_shader *shader,
388 struct ac_shader_config *config)
389 {
390 uint64_t scratch_bo_size, scratch_needed;
391 scratch_bo_size = 0;
392 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
393 if (sctx->compute_scratch_buffer)
394 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
395
396 if (scratch_bo_size < scratch_needed) {
397 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
398
399 sctx->compute_scratch_buffer =
400 si_aligned_buffer_create(&sctx->screen->b,
401 SI_RESOURCE_FLAG_UNMAPPABLE,
402 PIPE_USAGE_DEFAULT,
403 scratch_needed, 256);
404
405 if (!sctx->compute_scratch_buffer)
406 return false;
407 }
408
409 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
410 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
411
412 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
413 return false;
414
415 si_resource_reference(&shader->scratch_bo,
416 sctx->compute_scratch_buffer);
417 }
418
419 return true;
420 }
421
422 static bool si_switch_compute_shader(struct si_context *sctx,
423 struct si_compute *program,
424 struct si_shader *shader,
425 const amd_kernel_code_t *code_object,
426 unsigned offset)
427 {
428 struct radeon_cmdbuf *cs = sctx->gfx_cs;
429 struct ac_shader_config inline_config = {0};
430 struct ac_shader_config *config;
431 uint64_t shader_va;
432
433 if (sctx->cs_shader_state.emitted_program == program &&
434 sctx->cs_shader_state.offset == offset)
435 return true;
436
437 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
438 config = &shader->config;
439 } else {
440 unsigned lds_blocks;
441
442 config = &inline_config;
443 code_object_to_config(code_object, config);
444
445 lds_blocks = config->lds_size;
446 /* XXX: We are over allocating LDS. For GFX6, the shader reports
447 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
448 * allocated in the shader and 4 bytes allocated by the state
449 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
450 */
451 if (sctx->chip_class <= GFX6) {
452 lds_blocks += align(program->local_size, 256) >> 8;
453 } else {
454 lds_blocks += align(program->local_size, 512) >> 9;
455 }
456
457 /* TODO: use si_multiwave_lds_size_workaround */
458 assert(lds_blocks <= 0xFF);
459
460 config->rsrc2 &= C_00B84C_LDS_SIZE;
461 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
462 }
463
464 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
465 return false;
466
467 if (shader->scratch_bo) {
468 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
469 "Total Scratch: %u bytes\n", sctx->scratch_waves,
470 config->scratch_bytes_per_wave,
471 config->scratch_bytes_per_wave *
472 sctx->scratch_waves);
473
474 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
475 shader->scratch_bo, RADEON_USAGE_READWRITE,
476 RADEON_PRIO_SCRATCH_BUFFER);
477 }
478
479 /* Prefetch the compute shader to TC L2.
480 *
481 * We should also prefetch graphics shaders if a compute dispatch was
482 * the last command, and the compute shader if a draw call was the last
483 * command. However, that would add more complexity and we're likely
484 * to get a shader state change in that case anyway.
485 */
486 if (sctx->chip_class >= GFX7) {
487 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
488 0, program->shader.bo->b.b.width0);
489 }
490
491 shader_va = shader->bo->gpu_address + offset;
492 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
493 /* Shader code is placed after the amd_kernel_code_t
494 * struct. */
495 shader_va += sizeof(amd_kernel_code_t);
496 }
497
498 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
499 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
500
501 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
502 radeon_emit(cs, shader_va >> 8);
503 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
504
505 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
506 radeon_emit(cs, config->rsrc1);
507 radeon_emit(cs, config->rsrc2);
508
509 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
510 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
511
512 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
513 S_00B860_WAVES(sctx->scratch_waves)
514 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
515
516 sctx->cs_shader_state.emitted_program = program;
517 sctx->cs_shader_state.offset = offset;
518 sctx->cs_shader_state.uses_scratch =
519 config->scratch_bytes_per_wave != 0;
520
521 return true;
522 }
523
524 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
525 const amd_kernel_code_t *code_object,
526 unsigned user_sgpr)
527 {
528 struct radeon_cmdbuf *cs = sctx->gfx_cs;
529 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
530
531 unsigned max_private_element_size = AMD_HSA_BITS_GET(
532 code_object->code_properties,
533 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
534
535 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
536 uint32_t scratch_dword1 =
537 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
538 S_008F04_SWIZZLE_ENABLE(1);
539
540 /* Disable address clamping */
541 uint32_t scratch_dword2 = 0xffffffff;
542 uint32_t scratch_dword3 =
543 S_008F0C_INDEX_STRIDE(3) |
544 S_008F0C_ADD_TID_ENABLE(1);
545
546 if (sctx->chip_class >= GFX9) {
547 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
548 } else {
549 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
550
551 if (sctx->chip_class < GFX8) {
552 /* BUF_DATA_FORMAT is ignored, but it cannot be
553 * BUF_DATA_FORMAT_INVALID. */
554 scratch_dword3 |=
555 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
556 }
557 }
558
559 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
560 (user_sgpr * 4), 4);
561 radeon_emit(cs, scratch_dword0);
562 radeon_emit(cs, scratch_dword1);
563 radeon_emit(cs, scratch_dword2);
564 radeon_emit(cs, scratch_dword3);
565 }
566
567 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
568 const amd_kernel_code_t *code_object,
569 const struct pipe_grid_info *info,
570 uint64_t kernel_args_va)
571 {
572 struct si_compute *program = sctx->cs_shader_state.program;
573 struct radeon_cmdbuf *cs = sctx->gfx_cs;
574
575 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
576 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
577 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
578 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
579 };
580
581 unsigned i, user_sgpr = 0;
582 if (AMD_HSA_BITS_GET(code_object->code_properties,
583 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
584 if (code_object->workitem_private_segment_byte_size > 0) {
585 setup_scratch_rsrc_user_sgprs(sctx, code_object,
586 user_sgpr);
587 }
588 user_sgpr += 4;
589 }
590
591 if (AMD_HSA_BITS_GET(code_object->code_properties,
592 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
593 struct dispatch_packet dispatch;
594 unsigned dispatch_offset;
595 struct si_resource *dispatch_buf = NULL;
596 uint64_t dispatch_va;
597
598 /* Upload dispatch ptr */
599 memset(&dispatch, 0, sizeof(dispatch));
600
601 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
602 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
603 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
604
605 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
606 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
607 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
608
609 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
610 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
611
612 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
613
614 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
615 256, &dispatch, &dispatch_offset,
616 (struct pipe_resource**)&dispatch_buf);
617
618 if (!dispatch_buf) {
619 fprintf(stderr, "Error: Failed to allocate dispatch "
620 "packet.");
621 }
622 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
623 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
624
625 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
626
627 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
628 (user_sgpr * 4), 2);
629 radeon_emit(cs, dispatch_va);
630 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
631 S_008F04_STRIDE(0));
632
633 si_resource_reference(&dispatch_buf, NULL);
634 user_sgpr += 2;
635 }
636
637 if (AMD_HSA_BITS_GET(code_object->code_properties,
638 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
639 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
640 (user_sgpr * 4), 2);
641 radeon_emit(cs, kernel_args_va);
642 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
643 S_008F04_STRIDE(0));
644 user_sgpr += 2;
645 }
646
647 for (i = 0; i < 3 && user_sgpr < 16; i++) {
648 if (code_object->code_properties & workgroup_count_masks[i]) {
649 radeon_set_sh_reg_seq(cs,
650 R_00B900_COMPUTE_USER_DATA_0 +
651 (user_sgpr * 4), 1);
652 radeon_emit(cs, info->grid[i]);
653 user_sgpr += 1;
654 }
655 }
656 }
657
658 static bool si_upload_compute_input(struct si_context *sctx,
659 const amd_kernel_code_t *code_object,
660 const struct pipe_grid_info *info)
661 {
662 struct radeon_cmdbuf *cs = sctx->gfx_cs;
663 struct si_compute *program = sctx->cs_shader_state.program;
664 struct si_resource *input_buffer = NULL;
665 unsigned kernel_args_size;
666 unsigned num_work_size_bytes = program->ir_type == PIPE_SHADER_IR_NATIVE ? 0 : 36;
667 uint32_t kernel_args_offset = 0;
668 uint32_t *kernel_args;
669 void *kernel_args_ptr;
670 uint64_t kernel_args_va;
671 unsigned i;
672
673 /* The extra num_work_size_bytes are for work group / work item size information */
674 kernel_args_size = program->input_size + num_work_size_bytes;
675
676 u_upload_alloc(sctx->b.const_uploader, 0, kernel_args_size,
677 sctx->screen->info.tcc_cache_line_size,
678 &kernel_args_offset,
679 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
680
681 if (unlikely(!kernel_args_ptr))
682 return false;
683
684 kernel_args = (uint32_t*)kernel_args_ptr;
685 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
686
687 if (!code_object) {
688 for (i = 0; i < 3; i++) {
689 kernel_args[i] = util_cpu_to_le32(info->grid[i]);
690 kernel_args[i + 3] = util_cpu_to_le32(info->grid[i] * info->block[i]);
691 kernel_args[i + 6] = util_cpu_to_le32(info->block[i]);
692 }
693 }
694
695 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
696 program->input_size);
697
698
699 for (i = 0; i < (kernel_args_size / 4); i++) {
700 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
701 kernel_args[i]);
702 }
703
704
705 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
706 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
707
708 if (code_object) {
709 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
710 } else {
711 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
712 radeon_emit(cs, kernel_args_va);
713 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
714 S_008F04_STRIDE(0));
715 }
716
717 si_resource_reference(&input_buffer, NULL);
718
719 return true;
720 }
721
722 static void si_setup_tgsi_user_data(struct si_context *sctx,
723 const struct pipe_grid_info *info)
724 {
725 struct si_compute *program = sctx->cs_shader_state.program;
726 struct si_shader_selector *sel = &program->sel;
727 struct radeon_cmdbuf *cs = sctx->gfx_cs;
728 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
729 4 * SI_NUM_RESOURCE_SGPRS;
730 unsigned block_size_reg = grid_size_reg +
731 /* 12 bytes = 3 dwords. */
732 12 * sel->info.uses_grid_size;
733 unsigned cs_user_data_reg = block_size_reg +
734 12 * program->reads_variable_block_size;
735
736 if (info->indirect) {
737 if (sel->info.uses_grid_size) {
738 for (unsigned i = 0; i < 3; ++i) {
739 si_cp_copy_data(sctx, sctx->gfx_cs,
740 COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
741 COPY_DATA_SRC_MEM, si_resource(info->indirect),
742 info->indirect_offset + 4 * i);
743 }
744 }
745 } else {
746 if (sel->info.uses_grid_size) {
747 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
748 radeon_emit(cs, info->grid[0]);
749 radeon_emit(cs, info->grid[1]);
750 radeon_emit(cs, info->grid[2]);
751 }
752 if (program->reads_variable_block_size) {
753 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
754 radeon_emit(cs, info->block[0]);
755 radeon_emit(cs, info->block[1]);
756 radeon_emit(cs, info->block[2]);
757 }
758 }
759
760 if (program->num_cs_user_data_dwords) {
761 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
762 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
763 }
764 }
765
766 static void si_emit_dispatch_packets(struct si_context *sctx,
767 const struct pipe_grid_info *info)
768 {
769 struct si_screen *sscreen = sctx->screen;
770 struct radeon_cmdbuf *cs = sctx->gfx_cs;
771 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
772 unsigned threads_per_threadgroup =
773 info->block[0] * info->block[1] * info->block[2];
774 unsigned waves_per_threadgroup =
775 DIV_ROUND_UP(threads_per_threadgroup, 64);
776 unsigned threadgroups_per_cu = 1;
777
778 if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1)
779 threadgroups_per_cu = 2;
780
781 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
782 ac_get_compute_resource_limits(&sscreen->info,
783 waves_per_threadgroup,
784 sctx->cs_max_waves_per_sh,
785 threadgroups_per_cu));
786
787 unsigned dispatch_initiator =
788 S_00B800_COMPUTE_SHADER_EN(1) |
789 S_00B800_FORCE_START_AT_000(1) |
790 /* If the KMD allows it (there is a KMD hw register for it),
791 * allow launching waves out-of-order. (same as Vulkan) */
792 S_00B800_ORDER_MODE(sctx->chip_class >= GFX7);
793
794 const uint *last_block = info->last_block;
795 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
796
797 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
798
799 if (partial_block_en) {
800 unsigned partial[3];
801
802 /* If no partial_block, these should be an entire block size, not 0. */
803 partial[0] = last_block[0] ? last_block[0] : info->block[0];
804 partial[1] = last_block[1] ? last_block[1] : info->block[1];
805 partial[2] = last_block[2] ? last_block[2] : info->block[2];
806
807 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
808 S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
809 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
810 S_00B820_NUM_THREAD_PARTIAL(partial[1]));
811 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
812 S_00B824_NUM_THREAD_PARTIAL(partial[2]));
813
814 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
815 } else {
816 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
817 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
818 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
819 }
820
821 if (info->indirect) {
822 uint64_t base_va = si_resource(info->indirect)->gpu_address;
823
824 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
825 si_resource(info->indirect),
826 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
827
828 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
829 PKT3_SHADER_TYPE_S(1));
830 radeon_emit(cs, 1);
831 radeon_emit(cs, base_va);
832 radeon_emit(cs, base_va >> 32);
833
834 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
835 PKT3_SHADER_TYPE_S(1));
836 radeon_emit(cs, info->indirect_offset);
837 radeon_emit(cs, dispatch_initiator);
838 } else {
839 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
840 PKT3_SHADER_TYPE_S(1));
841 radeon_emit(cs, info->grid[0]);
842 radeon_emit(cs, info->grid[1]);
843 radeon_emit(cs, info->grid[2]);
844 radeon_emit(cs, dispatch_initiator);
845 }
846 }
847
848
849 static void si_launch_grid(
850 struct pipe_context *ctx, const struct pipe_grid_info *info)
851 {
852 struct si_context *sctx = (struct si_context*)ctx;
853 struct si_compute *program = sctx->cs_shader_state.program;
854 const amd_kernel_code_t *code_object =
855 si_compute_get_code_object(program, info->pc);
856 int i;
857 /* HW bug workaround when CS threadgroups > 256 threads and async
858 * compute isn't used, i.e. only one compute job can run at a time.
859 * If async compute is possible, the threadgroup size must be limited
860 * to 256 threads on all queues to avoid the bug.
861 * Only GFX6 and certain GFX7 chips are affected.
862 */
863 bool cs_regalloc_hang =
864 (sctx->chip_class == GFX6 ||
865 sctx->family == CHIP_BONAIRE ||
866 sctx->family == CHIP_KABINI) &&
867 info->block[0] * info->block[1] * info->block[2] > 256;
868
869 if (cs_regalloc_hang)
870 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
871 SI_CONTEXT_CS_PARTIAL_FLUSH;
872
873 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
874 program->shader.compilation_failed)
875 return;
876
877 if (sctx->has_graphics) {
878 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
879 si_update_fb_dirtiness_after_rendering(sctx);
880 sctx->last_num_draw_calls = sctx->num_draw_calls;
881 }
882
883 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
884 }
885
886 /* Add buffer sizes for memory checking in need_cs_space. */
887 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
888 /* TODO: add the scratch buffer */
889
890 if (info->indirect) {
891 si_context_add_resource_size(sctx, info->indirect);
892
893 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
894 if (sctx->chip_class <= GFX8 &&
895 si_resource(info->indirect)->TC_L2_dirty) {
896 sctx->flags |= SI_CONTEXT_WB_L2;
897 si_resource(info->indirect)->TC_L2_dirty = false;
898 }
899 }
900
901 si_need_gfx_cs_space(sctx);
902
903 if (sctx->bo_list_add_all_compute_resources)
904 si_compute_resources_add_all_to_bo_list(sctx);
905
906 if (!sctx->cs_shader_state.initialized) {
907 si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
908
909 sctx->cs_shader_state.emitted_program = NULL;
910 sctx->cs_shader_state.initialized = true;
911 }
912
913 if (sctx->flags)
914 sctx->emit_cache_flush(sctx);
915
916 if (!si_switch_compute_shader(sctx, program, &program->shader,
917 code_object, info->pc))
918 return;
919
920 si_upload_compute_shader_descriptors(sctx);
921 si_emit_compute_shader_pointers(sctx);
922
923 if (sctx->has_graphics &&
924 si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
925 sctx->atoms.s.render_cond.emit(sctx);
926 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
927 }
928
929 if ((program->input_size ||
930 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
931 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
932 return;
933 }
934
935 /* Global buffers */
936 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
937 struct si_resource *buffer =
938 si_resource(program->global_buffers[i]);
939 if (!buffer) {
940 continue;
941 }
942 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
943 RADEON_USAGE_READWRITE,
944 RADEON_PRIO_COMPUTE_GLOBAL);
945 }
946
947 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
948 si_setup_tgsi_user_data(sctx, info);
949
950 si_emit_dispatch_packets(sctx, info);
951
952 if (unlikely(sctx->current_saved_cs)) {
953 si_trace_emit(sctx);
954 si_log_compute_state(sctx, sctx->log);
955 }
956
957 sctx->compute_is_busy = true;
958 sctx->num_compute_calls++;
959 if (sctx->cs_shader_state.uses_scratch)
960 sctx->num_spill_compute_calls++;
961
962 if (cs_regalloc_hang)
963 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
964 }
965
966 void si_destroy_compute(struct si_compute *program)
967 {
968 struct si_shader_selector *sel = &program->sel;
969
970 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
971 util_queue_drop_job(&sel->screen->shader_compiler_queue,
972 &sel->ready);
973 util_queue_fence_destroy(&sel->ready);
974 }
975
976 si_shader_destroy(&program->shader);
977 FREE(program);
978 }
979
980 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
981 struct si_compute *program = (struct si_compute *)state;
982 struct si_context *sctx = (struct si_context*)ctx;
983
984 if (!state)
985 return;
986
987 if (program == sctx->cs_shader_state.program)
988 sctx->cs_shader_state.program = NULL;
989
990 if (program == sctx->cs_shader_state.emitted_program)
991 sctx->cs_shader_state.emitted_program = NULL;
992
993 ralloc_free(program->sel.nir);
994 si_compute_reference(&program, NULL);
995 }
996
997 static void si_set_compute_resources(struct pipe_context * ctx_,
998 unsigned start, unsigned count,
999 struct pipe_surface ** surfaces) { }
1000
1001 void si_init_compute_functions(struct si_context *sctx)
1002 {
1003 sctx->b.create_compute_state = si_create_compute_state;
1004 sctx->b.delete_compute_state = si_delete_compute_state;
1005 sctx->b.bind_compute_state = si_bind_compute_state;
1006 sctx->b.set_compute_resources = si_set_compute_resources;
1007 sctx->b.set_global_binding = si_set_global_binding;
1008 sctx->b.launch_grid = si_launch_grid;
1009 }