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radeonsi: use the new run-time linker for shaders
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "tgsi/tgsi_parse.h"
27 #include "util/u_async_debug.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30
31 #include "ac_rtld.h"
32 #include "amd_kernel_code_t.h"
33 #include "si_build_pm4.h"
34 #include "si_compute.h"
35
36 #define COMPUTE_DBG(sscreen, fmt, args...) \
37 do { \
38 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
39 } while (0);
40
41 struct dispatch_packet {
42 uint16_t header;
43 uint16_t setup;
44 uint16_t workgroup_size_x;
45 uint16_t workgroup_size_y;
46 uint16_t workgroup_size_z;
47 uint16_t reserved0;
48 uint32_t grid_size_x;
49 uint32_t grid_size_y;
50 uint32_t grid_size_z;
51 uint32_t private_segment_size;
52 uint32_t group_segment_size;
53 uint64_t kernel_object;
54 uint64_t kernarg_address;
55 uint64_t reserved2;
56 };
57
58 static const amd_kernel_code_t *si_compute_get_code_object(
59 const struct si_compute *program,
60 uint64_t symbol_offset)
61 {
62 if (!program->use_code_object_v2) {
63 return NULL;
64 }
65
66 struct ac_rtld_binary rtld;
67 if (!ac_rtld_open(&rtld, 1, &program->shader.binary.elf_buffer,
68 &program->shader.binary.elf_size))
69 return NULL;
70
71 const amd_kernel_code_t *result = NULL;
72 const char *text;
73 size_t size;
74 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
75 goto out;
76
77 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
78 goto out;
79
80 result = (const amd_kernel_code_t*)(text + symbol_offset);
81
82 out:
83 ac_rtld_close(&rtld);
84 return result;
85 }
86
87 static void code_object_to_config(const amd_kernel_code_t *code_object,
88 struct ac_shader_config *out_config) {
89
90 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
91 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
92 out_config->num_sgprs = code_object->wavefront_sgpr_count;
93 out_config->num_vgprs = code_object->workitem_vgpr_count;
94 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
95 out_config->rsrc1 = rsrc1;
96 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
97 out_config->rsrc2 = rsrc2;
98 out_config->scratch_bytes_per_wave =
99 align(code_object->workitem_private_segment_byte_size * 64, 1024);
100 }
101
102 /* Asynchronous compute shader compilation. */
103 static void si_create_compute_state_async(void *job, int thread_index)
104 {
105 struct si_compute *program = (struct si_compute *)job;
106 struct si_shader *shader = &program->shader;
107 struct si_shader_selector sel;
108 struct ac_llvm_compiler *compiler;
109 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
110 struct si_screen *sscreen = program->screen;
111
112 assert(!debug->debug_message || debug->async);
113 assert(thread_index >= 0);
114 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
115 compiler = &sscreen->compiler[thread_index];
116
117 memset(&sel, 0, sizeof(sel));
118
119 sel.screen = sscreen;
120
121 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
122 tgsi_scan_shader(program->ir.tgsi, &sel.info);
123 sel.tokens = program->ir.tgsi;
124 } else {
125 assert(program->ir_type == PIPE_SHADER_IR_NIR);
126 sel.nir = program->ir.nir;
127
128 si_nir_opts(sel.nir);
129 si_nir_scan_shader(sel.nir, &sel.info);
130 si_lower_nir(&sel);
131 }
132
133 /* Store the declared LDS size into tgsi_shader_info for the shader
134 * cache to include it.
135 */
136 sel.info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
137
138 sel.type = PIPE_SHADER_COMPUTE;
139 si_get_active_slot_masks(&sel.info,
140 &program->active_const_and_shader_buffers,
141 &program->active_samplers_and_images);
142
143 program->shader.selector = &sel;
144 program->shader.is_monolithic = true;
145 program->uses_grid_size = sel.info.uses_grid_size;
146 program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
147 program->uses_bindless_images = sel.info.uses_bindless_images;
148 program->reads_variable_block_size =
149 sel.info.uses_block_size &&
150 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
151 program->num_cs_user_data_dwords =
152 sel.info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
153
154 void *ir_binary = si_get_ir_binary(&sel);
155
156 /* Try to load the shader from the shader cache. */
157 mtx_lock(&sscreen->shader_cache_mutex);
158
159 if (ir_binary &&
160 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
161 mtx_unlock(&sscreen->shader_cache_mutex);
162
163 si_shader_dump_stats_for_shader_db(shader, debug);
164 si_shader_dump(sscreen, shader, debug, PIPE_SHADER_COMPUTE,
165 stderr, true);
166
167 if (!si_shader_binary_upload(sscreen, shader, 0))
168 program->shader.compilation_failed = true;
169 } else {
170 mtx_unlock(&sscreen->shader_cache_mutex);
171
172 if (!si_shader_create(sscreen, compiler, &program->shader, debug)) {
173 program->shader.compilation_failed = true;
174
175 if (program->ir_type == PIPE_SHADER_IR_TGSI)
176 FREE(program->ir.tgsi);
177 program->shader.selector = NULL;
178 return;
179 }
180
181 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
182 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
183 (sel.info.uses_grid_size ? 3 : 0) +
184 (program->reads_variable_block_size ? 3 : 0) +
185 program->num_cs_user_data_dwords;
186
187 shader->config.rsrc1 =
188 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
189 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
190 S_00B848_DX10_CLAMP(1) |
191 S_00B848_FLOAT_MODE(shader->config.float_mode);
192
193 shader->config.rsrc2 =
194 S_00B84C_USER_SGPR(user_sgprs) |
195 S_00B84C_SCRATCH_EN(scratch_enabled) |
196 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
197 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
198 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
199 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
200 sel.info.uses_thread_id[1] ? 1 : 0) |
201 S_00B84C_LDS_SIZE(shader->config.lds_size);
202
203 if (ir_binary) {
204 mtx_lock(&sscreen->shader_cache_mutex);
205 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
206 FREE(ir_binary);
207 mtx_unlock(&sscreen->shader_cache_mutex);
208 }
209 }
210
211 if (program->ir_type == PIPE_SHADER_IR_TGSI)
212 FREE(program->ir.tgsi);
213
214 program->shader.selector = NULL;
215 }
216
217 static void *si_create_compute_state(
218 struct pipe_context *ctx,
219 const struct pipe_compute_state *cso)
220 {
221 struct si_context *sctx = (struct si_context *)ctx;
222 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
223 struct si_compute *program = CALLOC_STRUCT(si_compute);
224
225 pipe_reference_init(&program->reference, 1);
226 program->screen = (struct si_screen *)ctx->screen;
227 program->ir_type = cso->ir_type;
228 program->local_size = cso->req_local_mem;
229 program->private_size = cso->req_private_mem;
230 program->input_size = cso->req_input_mem;
231 program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
232
233 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
234 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
235 program->ir.tgsi = tgsi_dup_tokens(cso->prog);
236 if (!program->ir.tgsi) {
237 FREE(program);
238 return NULL;
239 }
240 } else {
241 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
242 program->ir.nir = (struct nir_shader *) cso->prog;
243 }
244
245 program->compiler_ctx_state.debug = sctx->debug;
246 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
247 p_atomic_inc(&sscreen->num_shaders_created);
248
249 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
250 &program->ready,
251 &program->compiler_ctx_state,
252 program, si_create_compute_state_async);
253 } else {
254 const struct pipe_llvm_program_header *header;
255 const char *code;
256 header = cso->prog;
257 code = cso->prog + sizeof(struct pipe_llvm_program_header);
258
259 program->shader.binary.elf_size = header->num_bytes;
260 program->shader.binary.elf_buffer = malloc(header->num_bytes);
261 if (!program->shader.binary.elf_buffer) {
262 FREE(program);
263 return NULL;
264 }
265 memcpy((void *)program->shader.binary.elf_buffer, code, header->num_bytes);
266
267 const amd_kernel_code_t *code_object =
268 si_compute_get_code_object(program, 0);
269 code_object_to_config(code_object, &program->shader.config);
270
271 si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
272 PIPE_SHADER_COMPUTE, stderr, true);
273 if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
274 fprintf(stderr, "LLVM failed to upload shader\n");
275 free((void *)program->shader.binary.elf_buffer);
276 FREE(program);
277 return NULL;
278 }
279 }
280
281 return program;
282 }
283
284 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
285 {
286 struct si_context *sctx = (struct si_context*)ctx;
287 struct si_compute *program = (struct si_compute*)state;
288
289 sctx->cs_shader_state.program = program;
290 if (!program)
291 return;
292
293 /* Wait because we need active slot usage masks. */
294 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
295 util_queue_fence_wait(&program->ready);
296
297 si_set_active_descriptors(sctx,
298 SI_DESCS_FIRST_COMPUTE +
299 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
300 program->active_const_and_shader_buffers);
301 si_set_active_descriptors(sctx,
302 SI_DESCS_FIRST_COMPUTE +
303 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
304 program->active_samplers_and_images);
305 }
306
307 static void si_set_global_binding(
308 struct pipe_context *ctx, unsigned first, unsigned n,
309 struct pipe_resource **resources,
310 uint32_t **handles)
311 {
312 unsigned i;
313 struct si_context *sctx = (struct si_context*)ctx;
314 struct si_compute *program = sctx->cs_shader_state.program;
315
316 assert(first + n <= MAX_GLOBAL_BUFFERS);
317
318 if (!resources) {
319 for (i = 0; i < n; i++) {
320 pipe_resource_reference(&program->global_buffers[first + i], NULL);
321 }
322 return;
323 }
324
325 for (i = 0; i < n; i++) {
326 uint64_t va;
327 uint32_t offset;
328 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
329 va = si_resource(resources[i])->gpu_address;
330 offset = util_le32_to_cpu(*handles[i]);
331 va += offset;
332 va = util_cpu_to_le64(va);
333 memcpy(handles[i], &va, sizeof(va));
334 }
335 }
336
337 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
338 {
339 uint64_t bc_va;
340
341 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
342 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
343 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
344 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
345
346 if (sctx->chip_class >= GFX7) {
347 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
348 radeon_set_sh_reg_seq(cs,
349 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
350 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
351 S_00B858_SH1_CU_EN(0xffff));
352 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
353 S_00B858_SH1_CU_EN(0xffff));
354 }
355
356 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
357 * and is now per pipe, so it should be handled in the
358 * kernel if we want to use something other than the default value,
359 * which is now 0x22f.
360 */
361 if (sctx->chip_class <= GFX6) {
362 /* XXX: This should be:
363 * (number of compute units) * 4 * (waves per simd) - 1 */
364
365 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
366 0x190 /* Default value */);
367 }
368
369 /* Set the pointer to border colors. */
370 bc_va = sctx->border_color_buffer->gpu_address;
371
372 if (sctx->chip_class >= GFX7) {
373 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
374 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
375 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
376 } else {
377 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
378 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
379 bc_va >> 8);
380 }
381 }
382 }
383
384 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
385 struct si_shader *shader,
386 struct ac_shader_config *config)
387 {
388 uint64_t scratch_bo_size, scratch_needed;
389 scratch_bo_size = 0;
390 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
391 if (sctx->compute_scratch_buffer)
392 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
393
394 if (scratch_bo_size < scratch_needed) {
395 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
396
397 sctx->compute_scratch_buffer =
398 si_aligned_buffer_create(&sctx->screen->b,
399 SI_RESOURCE_FLAG_UNMAPPABLE,
400 PIPE_USAGE_DEFAULT,
401 scratch_needed, 256);
402
403 if (!sctx->compute_scratch_buffer)
404 return false;
405 }
406
407 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
408 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
409
410 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
411 return false;
412
413 si_resource_reference(&shader->scratch_bo,
414 sctx->compute_scratch_buffer);
415 }
416
417 return true;
418 }
419
420 static bool si_switch_compute_shader(struct si_context *sctx,
421 struct si_compute *program,
422 struct si_shader *shader,
423 const amd_kernel_code_t *code_object,
424 unsigned offset)
425 {
426 struct radeon_cmdbuf *cs = sctx->gfx_cs;
427 struct ac_shader_config inline_config = {0};
428 struct ac_shader_config *config;
429 uint64_t shader_va;
430
431 if (sctx->cs_shader_state.emitted_program == program &&
432 sctx->cs_shader_state.offset == offset)
433 return true;
434
435 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
436 config = &shader->config;
437 } else {
438 unsigned lds_blocks;
439
440 config = &inline_config;
441 code_object_to_config(code_object, config);
442
443 lds_blocks = config->lds_size;
444 /* XXX: We are over allocating LDS. For GFX6, the shader reports
445 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
446 * allocated in the shader and 4 bytes allocated by the state
447 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
448 */
449 if (sctx->chip_class <= GFX6) {
450 lds_blocks += align(program->local_size, 256) >> 8;
451 } else {
452 lds_blocks += align(program->local_size, 512) >> 9;
453 }
454
455 /* TODO: use si_multiwave_lds_size_workaround */
456 assert(lds_blocks <= 0xFF);
457
458 config->rsrc2 &= C_00B84C_LDS_SIZE;
459 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
460 }
461
462 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
463 return false;
464
465 if (shader->scratch_bo) {
466 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
467 "Total Scratch: %u bytes\n", sctx->scratch_waves,
468 config->scratch_bytes_per_wave,
469 config->scratch_bytes_per_wave *
470 sctx->scratch_waves);
471
472 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
473 shader->scratch_bo, RADEON_USAGE_READWRITE,
474 RADEON_PRIO_SCRATCH_BUFFER);
475 }
476
477 /* Prefetch the compute shader to TC L2.
478 *
479 * We should also prefetch graphics shaders if a compute dispatch was
480 * the last command, and the compute shader if a draw call was the last
481 * command. However, that would add more complexity and we're likely
482 * to get a shader state change in that case anyway.
483 */
484 if (sctx->chip_class >= GFX7) {
485 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
486 0, program->shader.bo->b.b.width0);
487 }
488
489 shader_va = shader->bo->gpu_address + offset;
490 if (program->use_code_object_v2) {
491 /* Shader code is placed after the amd_kernel_code_t
492 * struct. */
493 shader_va += sizeof(amd_kernel_code_t);
494 }
495
496 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
497 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
498
499 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
500 radeon_emit(cs, shader_va >> 8);
501 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
502
503 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
504 radeon_emit(cs, config->rsrc1);
505 radeon_emit(cs, config->rsrc2);
506
507 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
508 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
509
510 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
511 S_00B860_WAVES(sctx->scratch_waves)
512 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
513
514 sctx->cs_shader_state.emitted_program = program;
515 sctx->cs_shader_state.offset = offset;
516 sctx->cs_shader_state.uses_scratch =
517 config->scratch_bytes_per_wave != 0;
518
519 return true;
520 }
521
522 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
523 const amd_kernel_code_t *code_object,
524 unsigned user_sgpr)
525 {
526 struct radeon_cmdbuf *cs = sctx->gfx_cs;
527 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
528
529 unsigned max_private_element_size = AMD_HSA_BITS_GET(
530 code_object->code_properties,
531 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
532
533 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
534 uint32_t scratch_dword1 =
535 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
536 S_008F04_SWIZZLE_ENABLE(1);
537
538 /* Disable address clamping */
539 uint32_t scratch_dword2 = 0xffffffff;
540 uint32_t scratch_dword3 =
541 S_008F0C_INDEX_STRIDE(3) |
542 S_008F0C_ADD_TID_ENABLE(1);
543
544 if (sctx->chip_class >= GFX9) {
545 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
546 } else {
547 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
548
549 if (sctx->chip_class < GFX8) {
550 /* BUF_DATA_FORMAT is ignored, but it cannot be
551 * BUF_DATA_FORMAT_INVALID. */
552 scratch_dword3 |=
553 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
554 }
555 }
556
557 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
558 (user_sgpr * 4), 4);
559 radeon_emit(cs, scratch_dword0);
560 radeon_emit(cs, scratch_dword1);
561 radeon_emit(cs, scratch_dword2);
562 radeon_emit(cs, scratch_dword3);
563 }
564
565 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
566 const amd_kernel_code_t *code_object,
567 const struct pipe_grid_info *info,
568 uint64_t kernel_args_va)
569 {
570 struct si_compute *program = sctx->cs_shader_state.program;
571 struct radeon_cmdbuf *cs = sctx->gfx_cs;
572
573 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
574 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
575 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
576 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
577 };
578
579 unsigned i, user_sgpr = 0;
580 if (AMD_HSA_BITS_GET(code_object->code_properties,
581 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
582 if (code_object->workitem_private_segment_byte_size > 0) {
583 setup_scratch_rsrc_user_sgprs(sctx, code_object,
584 user_sgpr);
585 }
586 user_sgpr += 4;
587 }
588
589 if (AMD_HSA_BITS_GET(code_object->code_properties,
590 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
591 struct dispatch_packet dispatch;
592 unsigned dispatch_offset;
593 struct si_resource *dispatch_buf = NULL;
594 uint64_t dispatch_va;
595
596 /* Upload dispatch ptr */
597 memset(&dispatch, 0, sizeof(dispatch));
598
599 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
600 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
601 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
602
603 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
604 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
605 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
606
607 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
608 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
609
610 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
611
612 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
613 256, &dispatch, &dispatch_offset,
614 (struct pipe_resource**)&dispatch_buf);
615
616 if (!dispatch_buf) {
617 fprintf(stderr, "Error: Failed to allocate dispatch "
618 "packet.");
619 }
620 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
621 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
622
623 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
624
625 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
626 (user_sgpr * 4), 2);
627 radeon_emit(cs, dispatch_va);
628 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
629 S_008F04_STRIDE(0));
630
631 si_resource_reference(&dispatch_buf, NULL);
632 user_sgpr += 2;
633 }
634
635 if (AMD_HSA_BITS_GET(code_object->code_properties,
636 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
637 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
638 (user_sgpr * 4), 2);
639 radeon_emit(cs, kernel_args_va);
640 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
641 S_008F04_STRIDE(0));
642 user_sgpr += 2;
643 }
644
645 for (i = 0; i < 3 && user_sgpr < 16; i++) {
646 if (code_object->code_properties & workgroup_count_masks[i]) {
647 radeon_set_sh_reg_seq(cs,
648 R_00B900_COMPUTE_USER_DATA_0 +
649 (user_sgpr * 4), 1);
650 radeon_emit(cs, info->grid[i]);
651 user_sgpr += 1;
652 }
653 }
654 }
655
656 static bool si_upload_compute_input(struct si_context *sctx,
657 const amd_kernel_code_t *code_object,
658 const struct pipe_grid_info *info)
659 {
660 struct radeon_cmdbuf *cs = sctx->gfx_cs;
661 struct si_compute *program = sctx->cs_shader_state.program;
662 struct si_resource *input_buffer = NULL;
663 unsigned kernel_args_size;
664 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
665 uint32_t kernel_args_offset = 0;
666 uint32_t *kernel_args;
667 void *kernel_args_ptr;
668 uint64_t kernel_args_va;
669 unsigned i;
670
671 /* The extra num_work_size_bytes are for work group / work item size information */
672 kernel_args_size = program->input_size + num_work_size_bytes;
673
674 u_upload_alloc(sctx->b.const_uploader, 0, kernel_args_size,
675 sctx->screen->info.tcc_cache_line_size,
676 &kernel_args_offset,
677 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
678
679 if (unlikely(!kernel_args_ptr))
680 return false;
681
682 kernel_args = (uint32_t*)kernel_args_ptr;
683 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
684
685 if (!code_object) {
686 for (i = 0; i < 3; i++) {
687 kernel_args[i] = util_cpu_to_le32(info->grid[i]);
688 kernel_args[i + 3] = util_cpu_to_le32(info->grid[i] * info->block[i]);
689 kernel_args[i + 6] = util_cpu_to_le32(info->block[i]);
690 }
691 }
692
693 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
694 program->input_size);
695
696
697 for (i = 0; i < (kernel_args_size / 4); i++) {
698 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
699 kernel_args[i]);
700 }
701
702
703 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
704 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
705
706 if (code_object) {
707 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
708 } else {
709 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
710 radeon_emit(cs, kernel_args_va);
711 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
712 S_008F04_STRIDE(0));
713 }
714
715 si_resource_reference(&input_buffer, NULL);
716
717 return true;
718 }
719
720 static void si_setup_tgsi_user_data(struct si_context *sctx,
721 const struct pipe_grid_info *info)
722 {
723 struct si_compute *program = sctx->cs_shader_state.program;
724 struct radeon_cmdbuf *cs = sctx->gfx_cs;
725 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
726 4 * SI_NUM_RESOURCE_SGPRS;
727 unsigned block_size_reg = grid_size_reg +
728 /* 12 bytes = 3 dwords. */
729 12 * program->uses_grid_size;
730 unsigned cs_user_data_reg = block_size_reg +
731 12 * program->reads_variable_block_size;
732
733 if (info->indirect) {
734 if (program->uses_grid_size) {
735 for (unsigned i = 0; i < 3; ++i) {
736 si_cp_copy_data(sctx, sctx->gfx_cs,
737 COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
738 COPY_DATA_SRC_MEM, si_resource(info->indirect),
739 info->indirect_offset + 4 * i);
740 }
741 }
742 } else {
743 if (program->uses_grid_size) {
744 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
745 radeon_emit(cs, info->grid[0]);
746 radeon_emit(cs, info->grid[1]);
747 radeon_emit(cs, info->grid[2]);
748 }
749 if (program->reads_variable_block_size) {
750 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
751 radeon_emit(cs, info->block[0]);
752 radeon_emit(cs, info->block[1]);
753 radeon_emit(cs, info->block[2]);
754 }
755 }
756
757 if (program->num_cs_user_data_dwords) {
758 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
759 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
760 }
761 }
762
763 unsigned si_get_compute_resource_limits(struct si_screen *sscreen,
764 unsigned waves_per_threadgroup,
765 unsigned max_waves_per_sh,
766 unsigned threadgroups_per_cu)
767 {
768 unsigned compute_resource_limits =
769 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
770
771 if (sscreen->info.chip_class >= GFX7) {
772 unsigned num_cu_per_se = sscreen->info.num_good_compute_units /
773 sscreen->info.max_se;
774
775 /* Force even distribution on all SIMDs in CU if the workgroup
776 * size is 64. This has shown some good improvements if # of CUs
777 * per SE is not a multiple of 4.
778 */
779 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
780 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
781
782 assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
783 compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
784 S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
785 } else {
786 /* GFX6 */
787 if (max_waves_per_sh) {
788 unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
789 compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
790 }
791 }
792 return compute_resource_limits;
793 }
794
795 static void si_emit_dispatch_packets(struct si_context *sctx,
796 const struct pipe_grid_info *info)
797 {
798 struct si_screen *sscreen = sctx->screen;
799 struct radeon_cmdbuf *cs = sctx->gfx_cs;
800 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
801 unsigned waves_per_threadgroup =
802 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
803
804 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
805 si_get_compute_resource_limits(sscreen, waves_per_threadgroup,
806 sctx->cs_max_waves_per_sh, 1));
807
808 unsigned dispatch_initiator =
809 S_00B800_COMPUTE_SHADER_EN(1) |
810 S_00B800_FORCE_START_AT_000(1) |
811 /* If the KMD allows it (there is a KMD hw register for it),
812 * allow launching waves out-of-order. (same as Vulkan) */
813 S_00B800_ORDER_MODE(sctx->chip_class >= GFX7);
814
815 const uint *last_block = info->last_block;
816 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
817
818 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
819
820 if (partial_block_en) {
821 unsigned partial[3];
822
823 /* If no partial_block, these should be an entire block size, not 0. */
824 partial[0] = last_block[0] ? last_block[0] : info->block[0];
825 partial[1] = last_block[1] ? last_block[1] : info->block[1];
826 partial[2] = last_block[2] ? last_block[2] : info->block[2];
827
828 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
829 S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
830 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
831 S_00B820_NUM_THREAD_PARTIAL(partial[1]));
832 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
833 S_00B824_NUM_THREAD_PARTIAL(partial[2]));
834
835 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
836 } else {
837 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
838 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
839 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
840 }
841
842 if (info->indirect) {
843 uint64_t base_va = si_resource(info->indirect)->gpu_address;
844
845 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
846 si_resource(info->indirect),
847 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
848
849 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
850 PKT3_SHADER_TYPE_S(1));
851 radeon_emit(cs, 1);
852 radeon_emit(cs, base_va);
853 radeon_emit(cs, base_va >> 32);
854
855 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
856 PKT3_SHADER_TYPE_S(1));
857 radeon_emit(cs, info->indirect_offset);
858 radeon_emit(cs, dispatch_initiator);
859 } else {
860 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
861 PKT3_SHADER_TYPE_S(1));
862 radeon_emit(cs, info->grid[0]);
863 radeon_emit(cs, info->grid[1]);
864 radeon_emit(cs, info->grid[2]);
865 radeon_emit(cs, dispatch_initiator);
866 }
867 }
868
869
870 static void si_launch_grid(
871 struct pipe_context *ctx, const struct pipe_grid_info *info)
872 {
873 struct si_context *sctx = (struct si_context*)ctx;
874 struct si_compute *program = sctx->cs_shader_state.program;
875 const amd_kernel_code_t *code_object =
876 si_compute_get_code_object(program, info->pc);
877 int i;
878 /* HW bug workaround when CS threadgroups > 256 threads and async
879 * compute isn't used, i.e. only one compute job can run at a time.
880 * If async compute is possible, the threadgroup size must be limited
881 * to 256 threads on all queues to avoid the bug.
882 * Only GFX6 and certain GFX7 chips are affected.
883 */
884 bool cs_regalloc_hang =
885 (sctx->chip_class == GFX6 ||
886 sctx->family == CHIP_BONAIRE ||
887 sctx->family == CHIP_KABINI) &&
888 info->block[0] * info->block[1] * info->block[2] > 256;
889
890 if (cs_regalloc_hang)
891 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
892 SI_CONTEXT_CS_PARTIAL_FLUSH;
893
894 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
895 program->shader.compilation_failed)
896 return;
897
898 if (sctx->has_graphics) {
899 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
900 si_update_fb_dirtiness_after_rendering(sctx);
901 sctx->last_num_draw_calls = sctx->num_draw_calls;
902 }
903
904 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
905 }
906
907 /* Add buffer sizes for memory checking in need_cs_space. */
908 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
909 /* TODO: add the scratch buffer */
910
911 if (info->indirect) {
912 si_context_add_resource_size(sctx, info->indirect);
913
914 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
915 if (sctx->chip_class <= GFX8 &&
916 si_resource(info->indirect)->TC_L2_dirty) {
917 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
918 si_resource(info->indirect)->TC_L2_dirty = false;
919 }
920 }
921
922 si_need_gfx_cs_space(sctx);
923
924 if (sctx->bo_list_add_all_compute_resources)
925 si_compute_resources_add_all_to_bo_list(sctx);
926
927 if (!sctx->cs_shader_state.initialized) {
928 si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
929
930 sctx->cs_shader_state.emitted_program = NULL;
931 sctx->cs_shader_state.initialized = true;
932 }
933
934 if (sctx->flags)
935 si_emit_cache_flush(sctx);
936
937 if (!si_switch_compute_shader(sctx, program, &program->shader,
938 code_object, info->pc))
939 return;
940
941 si_upload_compute_shader_descriptors(sctx);
942 si_emit_compute_shader_pointers(sctx);
943
944 if (sctx->has_graphics &&
945 si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
946 sctx->atoms.s.render_cond.emit(sctx);
947 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
948 }
949
950 if ((program->input_size ||
951 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
952 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
953 return;
954 }
955
956 /* Global buffers */
957 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
958 struct si_resource *buffer =
959 si_resource(program->global_buffers[i]);
960 if (!buffer) {
961 continue;
962 }
963 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
964 RADEON_USAGE_READWRITE,
965 RADEON_PRIO_COMPUTE_GLOBAL);
966 }
967
968 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
969 si_setup_tgsi_user_data(sctx, info);
970
971 si_emit_dispatch_packets(sctx, info);
972
973 if (unlikely(sctx->current_saved_cs)) {
974 si_trace_emit(sctx);
975 si_log_compute_state(sctx, sctx->log);
976 }
977
978 sctx->compute_is_busy = true;
979 sctx->num_compute_calls++;
980 if (sctx->cs_shader_state.uses_scratch)
981 sctx->num_spill_compute_calls++;
982
983 if (cs_regalloc_hang)
984 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
985 }
986
987 void si_destroy_compute(struct si_compute *program)
988 {
989 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
990 util_queue_drop_job(&program->screen->shader_compiler_queue,
991 &program->ready);
992 util_queue_fence_destroy(&program->ready);
993 }
994
995 si_shader_destroy(&program->shader);
996 FREE(program);
997 }
998
999 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
1000 struct si_compute *program = (struct si_compute *)state;
1001 struct si_context *sctx = (struct si_context*)ctx;
1002
1003 if (!state)
1004 return;
1005
1006 if (program == sctx->cs_shader_state.program)
1007 sctx->cs_shader_state.program = NULL;
1008
1009 if (program == sctx->cs_shader_state.emitted_program)
1010 sctx->cs_shader_state.emitted_program = NULL;
1011
1012 si_compute_reference(&program, NULL);
1013 }
1014
1015 static void si_set_compute_resources(struct pipe_context * ctx_,
1016 unsigned start, unsigned count,
1017 struct pipe_surface ** surfaces) { }
1018
1019 void si_init_compute_functions(struct si_context *sctx)
1020 {
1021 sctx->b.create_compute_state = si_create_compute_state;
1022 sctx->b.delete_compute_state = si_delete_compute_state;
1023 sctx->b.bind_compute_state = si_bind_compute_state;
1024 sctx->b.set_compute_resources = si_set_compute_resources;
1025 sctx->b.set_global_binding = si_set_global_binding;
1026 sctx->b.launch_grid = si_launch_grid;
1027 }