2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
29 #include "amd_kernel_code_t.h"
30 #include "radeon/r600_cs.h"
32 #include "si_compute.h"
35 struct dispatch_packet
{
38 uint16_t workgroup_size_x
;
39 uint16_t workgroup_size_y
;
40 uint16_t workgroup_size_z
;
45 uint32_t private_segment_size
;
46 uint32_t group_segment_size
;
47 uint64_t kernel_object
;
48 uint64_t kernarg_address
;
52 static const amd_kernel_code_t
*si_compute_get_code_object(
53 const struct si_compute
*program
,
54 uint64_t symbol_offset
)
56 if (!program
->use_code_object_v2
) {
59 return (const amd_kernel_code_t
*)
60 (program
->shader
.binary
.code
+ symbol_offset
);
63 static void code_object_to_config(const amd_kernel_code_t
*code_object
,
64 struct si_shader_config
*out_config
) {
66 uint32_t rsrc1
= code_object
->compute_pgm_resource_registers
;
67 uint32_t rsrc2
= code_object
->compute_pgm_resource_registers
>> 32;
68 out_config
->num_sgprs
= code_object
->wavefront_sgpr_count
;
69 out_config
->num_vgprs
= code_object
->workitem_vgpr_count
;
70 out_config
->float_mode
= G_00B028_FLOAT_MODE(rsrc1
);
71 out_config
->rsrc1
= rsrc1
;
72 out_config
->lds_size
= MAX2(out_config
->lds_size
, G_00B84C_LDS_SIZE(rsrc2
));
73 out_config
->rsrc2
= rsrc2
;
74 out_config
->scratch_bytes_per_wave
=
75 align(code_object
->workitem_private_segment_byte_size
* 64, 1024);
78 /* Asynchronous compute shader compilation. */
79 static void si_create_compute_state_async(void *job
, int thread_index
)
81 struct si_compute
*program
= (struct si_compute
*)job
;
82 struct si_shader
*shader
= &program
->shader
;
83 struct si_shader_selector sel
;
84 LLVMTargetMachineRef tm
;
85 struct pipe_debug_callback
*debug
= &program
->compiler_ctx_state
.debug
;
87 if (thread_index
>= 0) {
88 assert(thread_index
< ARRAY_SIZE(program
->screen
->tm
));
89 tm
= program
->screen
->tm
[thread_index
];
93 tm
= program
->compiler_ctx_state
.tm
;
96 memset(&sel
, 0, sizeof(sel
));
98 sel
.screen
= program
->screen
;
99 tgsi_scan_shader(program
->tokens
, &sel
.info
);
100 sel
.tokens
= program
->tokens
;
101 sel
.type
= PIPE_SHADER_COMPUTE
;
102 sel
.local_size
= program
->local_size
;
103 si_get_active_slot_masks(&sel
.info
,
104 &program
->active_const_and_shader_buffers
,
105 &program
->active_samplers_and_images
);
107 program
->shader
.selector
= &sel
;
108 program
->shader
.is_monolithic
= true;
109 program
->uses_grid_size
= sel
.info
.uses_grid_size
;
110 program
->uses_block_size
= sel
.info
.uses_block_size
;
111 program
->uses_bindless_samplers
= sel
.info
.uses_bindless_samplers
;
112 program
->uses_bindless_images
= sel
.info
.uses_bindless_images
;
114 if (si_shader_create(program
->screen
, tm
, &program
->shader
, debug
)) {
115 program
->shader
.compilation_failed
= true;
117 bool scratch_enabled
= shader
->config
.scratch_bytes_per_wave
> 0;
118 unsigned user_sgprs
= SI_NUM_RESOURCE_SGPRS
+
119 (sel
.info
.uses_grid_size
? 3 : 0) +
120 (sel
.info
.uses_block_size
? 3 : 0);
122 shader
->config
.rsrc1
=
123 S_00B848_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
124 S_00B848_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
125 S_00B848_DX10_CLAMP(1) |
126 S_00B848_FLOAT_MODE(shader
->config
.float_mode
);
128 shader
->config
.rsrc2
=
129 S_00B84C_USER_SGPR(user_sgprs
) |
130 S_00B84C_SCRATCH_EN(scratch_enabled
) |
131 S_00B84C_TGID_X_EN(sel
.info
.uses_block_id
[0]) |
132 S_00B84C_TGID_Y_EN(sel
.info
.uses_block_id
[1]) |
133 S_00B84C_TGID_Z_EN(sel
.info
.uses_block_id
[2]) |
134 S_00B84C_TIDIG_COMP_CNT(sel
.info
.uses_thread_id
[2] ? 2 :
135 sel
.info
.uses_thread_id
[1] ? 1 : 0) |
136 S_00B84C_LDS_SIZE(shader
->config
.lds_size
);
138 program
->variable_group_size
=
139 sel
.info
.properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0;
142 FREE(program
->tokens
);
143 program
->shader
.selector
= NULL
;
146 static void *si_create_compute_state(
147 struct pipe_context
*ctx
,
148 const struct pipe_compute_state
*cso
)
150 struct si_context
*sctx
= (struct si_context
*)ctx
;
151 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
152 struct si_compute
*program
= CALLOC_STRUCT(si_compute
);
154 program
->screen
= (struct si_screen
*)ctx
->screen
;
155 program
->ir_type
= cso
->ir_type
;
156 program
->local_size
= cso
->req_local_mem
;
157 program
->private_size
= cso
->req_private_mem
;
158 program
->input_size
= cso
->req_input_mem
;
159 program
->use_code_object_v2
= HAVE_LLVM
>= 0x0400 &&
160 cso
->ir_type
== PIPE_SHADER_IR_NATIVE
;
162 if (cso
->ir_type
== PIPE_SHADER_IR_TGSI
) {
163 program
->tokens
= tgsi_dup_tokens(cso
->prog
);
164 if (!program
->tokens
) {
169 program
->compiler_ctx_state
.tm
= sctx
->tm
;
170 program
->compiler_ctx_state
.debug
= sctx
->b
.debug
;
171 program
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
172 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
173 util_queue_fence_init(&program
->ready
);
175 if ((sctx
->b
.debug
.debug_message
&& !sctx
->b
.debug
.async
) ||
177 r600_can_dump_shader(&sscreen
->b
, PIPE_SHADER_COMPUTE
))
178 si_create_compute_state_async(program
, -1);
180 util_queue_add_job(&sscreen
->shader_compiler_queue
,
181 program
, &program
->ready
,
182 si_create_compute_state_async
, NULL
);
184 const struct pipe_llvm_program_header
*header
;
187 code
= cso
->prog
+ sizeof(struct pipe_llvm_program_header
);
189 ac_elf_read(code
, header
->num_bytes
, &program
->shader
.binary
);
190 if (program
->use_code_object_v2
) {
191 const amd_kernel_code_t
*code_object
=
192 si_compute_get_code_object(program
, 0);
193 code_object_to_config(code_object
, &program
->shader
.config
);
195 si_shader_binary_read_config(&program
->shader
.binary
,
196 &program
->shader
.config
, 0);
198 si_shader_dump(sctx
->screen
, &program
->shader
, &sctx
->b
.debug
,
199 PIPE_SHADER_COMPUTE
, stderr
, true);
200 if (si_shader_binary_upload(sctx
->screen
, &program
->shader
) < 0) {
201 fprintf(stderr
, "LLVM failed to upload shader\n");
210 static void si_bind_compute_state(struct pipe_context
*ctx
, void *state
)
212 struct si_context
*sctx
= (struct si_context
*)ctx
;
213 struct si_compute
*program
= (struct si_compute
*)state
;
215 sctx
->cs_shader_state
.program
= program
;
219 /* Wait because we need active slot usage masks. */
220 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
)
221 util_queue_fence_wait(&program
->ready
);
223 si_set_active_descriptors(sctx
,
224 SI_DESCS_FIRST_COMPUTE
+
225 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
,
226 program
->active_const_and_shader_buffers
);
227 si_set_active_descriptors(sctx
,
228 SI_DESCS_FIRST_COMPUTE
+
229 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
,
230 program
->active_samplers_and_images
);
233 static void si_set_global_binding(
234 struct pipe_context
*ctx
, unsigned first
, unsigned n
,
235 struct pipe_resource
**resources
,
239 struct si_context
*sctx
= (struct si_context
*)ctx
;
240 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
242 assert(first
+ n
<= MAX_GLOBAL_BUFFERS
);
245 for (i
= 0; i
< n
; i
++) {
246 pipe_resource_reference(&program
->global_buffers
[first
+ i
], NULL
);
251 for (i
= 0; i
< n
; i
++) {
254 pipe_resource_reference(&program
->global_buffers
[first
+ i
], resources
[i
]);
255 va
= r600_resource(resources
[i
])->gpu_address
;
256 offset
= util_le32_to_cpu(*handles
[i
]);
258 va
= util_cpu_to_le64(va
);
259 memcpy(handles
[i
], &va
, sizeof(va
));
263 static void si_initialize_compute(struct si_context
*sctx
)
265 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
268 radeon_set_sh_reg_seq(cs
, R_00B810_COMPUTE_START_X
, 3);
273 radeon_set_sh_reg_seq(cs
, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0
, 2);
274 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
275 radeon_emit(cs
, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
276 radeon_emit(cs
, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
278 if (sctx
->b
.chip_class
>= CIK
) {
279 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
280 radeon_set_sh_reg_seq(cs
,
281 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2
, 2);
282 radeon_emit(cs
, S_00B864_SH0_CU_EN(0xffff) |
283 S_00B864_SH1_CU_EN(0xffff));
284 radeon_emit(cs
, S_00B868_SH0_CU_EN(0xffff) |
285 S_00B868_SH1_CU_EN(0xffff));
288 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
289 * and is now per pipe, so it should be handled in the
290 * kernel if we want to use something other than the default value,
291 * which is now 0x22f.
293 if (sctx
->b
.chip_class
<= SI
) {
294 /* XXX: This should be:
295 * (number of compute units) * 4 * (waves per simd) - 1 */
297 radeon_set_sh_reg(cs
, R_00B82C_COMPUTE_MAX_WAVE_ID
,
298 0x190 /* Default value */);
301 /* Set the pointer to border colors. */
302 bc_va
= sctx
->border_color_buffer
->gpu_address
;
304 if (sctx
->b
.chip_class
>= CIK
) {
305 radeon_set_uconfig_reg_seq(cs
, R_030E00_TA_CS_BC_BASE_ADDR
, 2);
306 radeon_emit(cs
, bc_va
>> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
307 radeon_emit(cs
, bc_va
>> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
309 if (sctx
->screen
->b
.info
.drm_major
== 3 ||
310 (sctx
->screen
->b
.info
.drm_major
== 2 &&
311 sctx
->screen
->b
.info
.drm_minor
>= 48)) {
312 radeon_set_config_reg(cs
, R_00950C_TA_CS_BC_BASE_ADDR
,
317 sctx
->cs_shader_state
.emitted_program
= NULL
;
318 sctx
->cs_shader_state
.initialized
= true;
321 static bool si_setup_compute_scratch_buffer(struct si_context
*sctx
,
322 struct si_shader
*shader
,
323 struct si_shader_config
*config
)
325 uint64_t scratch_bo_size
, scratch_needed
;
327 scratch_needed
= config
->scratch_bytes_per_wave
* sctx
->scratch_waves
;
328 if (sctx
->compute_scratch_buffer
)
329 scratch_bo_size
= sctx
->compute_scratch_buffer
->b
.b
.width0
;
331 if (scratch_bo_size
< scratch_needed
) {
332 r600_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
334 sctx
->compute_scratch_buffer
= (struct r600_resource
*)
335 r600_aligned_buffer_create(&sctx
->screen
->b
.b
,
336 R600_RESOURCE_FLAG_UNMAPPABLE
,
338 scratch_needed
, 256);
340 if (!sctx
->compute_scratch_buffer
)
344 if (sctx
->compute_scratch_buffer
!= shader
->scratch_bo
&& scratch_needed
) {
345 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
347 si_shader_apply_scratch_relocs(shader
, scratch_va
);
349 if (si_shader_binary_upload(sctx
->screen
, shader
))
352 r600_resource_reference(&shader
->scratch_bo
,
353 sctx
->compute_scratch_buffer
);
359 static bool si_switch_compute_shader(struct si_context
*sctx
,
360 struct si_compute
*program
,
361 struct si_shader
*shader
,
362 const amd_kernel_code_t
*code_object
,
365 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
366 struct si_shader_config inline_config
= {0};
367 struct si_shader_config
*config
;
370 if (sctx
->cs_shader_state
.emitted_program
== program
&&
371 sctx
->cs_shader_state
.offset
== offset
)
374 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
) {
375 config
= &shader
->config
;
379 config
= &inline_config
;
381 code_object_to_config(code_object
, config
);
383 si_shader_binary_read_config(&shader
->binary
, config
, offset
);
386 lds_blocks
= config
->lds_size
;
387 /* XXX: We are over allocating LDS. For SI, the shader reports
388 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
389 * allocated in the shader and 4 bytes allocated by the state
390 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
392 if (sctx
->b
.chip_class
<= SI
) {
393 lds_blocks
+= align(program
->local_size
, 256) >> 8;
395 lds_blocks
+= align(program
->local_size
, 512) >> 9;
398 /* TODO: use si_multiwave_lds_size_workaround */
399 assert(lds_blocks
<= 0xFF);
401 config
->rsrc2
&= C_00B84C_LDS_SIZE
;
402 config
->rsrc2
|= S_00B84C_LDS_SIZE(lds_blocks
);
405 if (!si_setup_compute_scratch_buffer(sctx
, shader
, config
))
408 if (shader
->scratch_bo
) {
409 COMPUTE_DBG(sctx
->screen
, "Waves: %u; Scratch per wave: %u bytes; "
410 "Total Scratch: %u bytes\n", sctx
->scratch_waves
,
411 config
->scratch_bytes_per_wave
,
412 config
->scratch_bytes_per_wave
*
413 sctx
->scratch_waves
);
415 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
416 shader
->scratch_bo
, RADEON_USAGE_READWRITE
,
417 RADEON_PRIO_SCRATCH_BUFFER
);
420 /* Prefetch the compute shader to TC L2.
422 * We should also prefetch graphics shaders if a compute dispatch was
423 * the last command, and the compute shader if a draw call was the last
424 * command. However, that would add more complexity and we're likely
425 * to get a shader state change in that case anyway.
427 if (sctx
->b
.chip_class
>= CIK
) {
428 cik_prefetch_TC_L2_async(sctx
, &program
->shader
.bo
->b
.b
,
429 0, program
->shader
.bo
->b
.b
.width0
);
432 shader_va
= shader
->bo
->gpu_address
+ offset
;
433 if (program
->use_code_object_v2
) {
434 /* Shader code is placed after the amd_kernel_code_t
436 shader_va
+= sizeof(amd_kernel_code_t
);
439 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, shader
->bo
,
440 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
442 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
443 radeon_emit(cs
, shader_va
>> 8);
444 radeon_emit(cs
, shader_va
>> 40);
446 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
447 radeon_emit(cs
, config
->rsrc1
);
448 radeon_emit(cs
, config
->rsrc2
);
450 COMPUTE_DBG(sctx
->screen
, "COMPUTE_PGM_RSRC1: 0x%08x "
451 "COMPUTE_PGM_RSRC2: 0x%08x\n", config
->rsrc1
, config
->rsrc2
);
453 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
454 S_00B860_WAVES(sctx
->scratch_waves
)
455 | S_00B860_WAVESIZE(config
->scratch_bytes_per_wave
>> 10));
457 sctx
->cs_shader_state
.emitted_program
= program
;
458 sctx
->cs_shader_state
.offset
= offset
;
459 sctx
->cs_shader_state
.uses_scratch
=
460 config
->scratch_bytes_per_wave
!= 0;
465 static void setup_scratch_rsrc_user_sgprs(struct si_context
*sctx
,
466 const amd_kernel_code_t
*code_object
,
469 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
470 uint64_t scratch_va
= sctx
->compute_scratch_buffer
->gpu_address
;
472 unsigned max_private_element_size
= AMD_HSA_BITS_GET(
473 code_object
->code_properties
,
474 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE
);
476 uint32_t scratch_dword0
= scratch_va
& 0xffffffff;
477 uint32_t scratch_dword1
=
478 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
479 S_008F04_SWIZZLE_ENABLE(1);
481 /* Disable address clamping */
482 uint32_t scratch_dword2
= 0xffffffff;
483 uint32_t scratch_dword3
=
484 S_008F0C_INDEX_STRIDE(3) |
485 S_008F0C_ADD_TID_ENABLE(1);
487 if (sctx
->b
.chip_class
>= GFX9
) {
488 assert(max_private_element_size
== 1); /* always 4 bytes on GFX9 */
490 scratch_dword3
|= S_008F0C_ELEMENT_SIZE(max_private_element_size
);
492 if (sctx
->b
.chip_class
< VI
) {
493 /* BUF_DATA_FORMAT is ignored, but it cannot be
494 * BUF_DATA_FORMAT_INVALID. */
496 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8
);
500 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
502 radeon_emit(cs
, scratch_dword0
);
503 radeon_emit(cs
, scratch_dword1
);
504 radeon_emit(cs
, scratch_dword2
);
505 radeon_emit(cs
, scratch_dword3
);
508 static void si_setup_user_sgprs_co_v2(struct si_context
*sctx
,
509 const amd_kernel_code_t
*code_object
,
510 const struct pipe_grid_info
*info
,
511 uint64_t kernel_args_va
)
513 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
514 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
516 static const enum amd_code_property_mask_t workgroup_count_masks
[] = {
517 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X
,
518 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y
,
519 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
522 unsigned i
, user_sgpr
= 0;
523 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
524 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER
)) {
525 if (code_object
->workitem_private_segment_byte_size
> 0) {
526 setup_scratch_rsrc_user_sgprs(sctx
, code_object
,
532 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
533 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR
)) {
534 struct dispatch_packet dispatch
;
535 unsigned dispatch_offset
;
536 struct r600_resource
*dispatch_buf
= NULL
;
537 uint64_t dispatch_va
;
539 /* Upload dispatch ptr */
540 memset(&dispatch
, 0, sizeof(dispatch
));
542 dispatch
.workgroup_size_x
= info
->block
[0];
543 dispatch
.workgroup_size_y
= info
->block
[1];
544 dispatch
.workgroup_size_z
= info
->block
[2];
546 dispatch
.grid_size_x
= info
->grid
[0] * info
->block
[0];
547 dispatch
.grid_size_y
= info
->grid
[1] * info
->block
[1];
548 dispatch
.grid_size_z
= info
->grid
[2] * info
->block
[2];
550 dispatch
.private_segment_size
= program
->private_size
;
551 dispatch
.group_segment_size
= program
->local_size
;
553 dispatch
.kernarg_address
= kernel_args_va
;
555 u_upload_data(sctx
->b
.b
.const_uploader
, 0, sizeof(dispatch
),
556 256, &dispatch
, &dispatch_offset
,
557 (struct pipe_resource
**)&dispatch_buf
);
560 fprintf(stderr
, "Error: Failed to allocate dispatch "
563 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, dispatch_buf
,
564 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
566 dispatch_va
= dispatch_buf
->gpu_address
+ dispatch_offset
;
568 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
570 radeon_emit(cs
, dispatch_va
);
571 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(dispatch_va
>> 32) |
574 r600_resource_reference(&dispatch_buf
, NULL
);
578 if (AMD_HSA_BITS_GET(code_object
->code_properties
,
579 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR
)) {
580 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
+
582 radeon_emit(cs
, kernel_args_va
);
583 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) |
588 for (i
= 0; i
< 3 && user_sgpr
< 16; i
++) {
589 if (code_object
->code_properties
& workgroup_count_masks
[i
]) {
590 radeon_set_sh_reg_seq(cs
,
591 R_00B900_COMPUTE_USER_DATA_0
+
593 radeon_emit(cs
, info
->grid
[i
]);
599 static bool si_upload_compute_input(struct si_context
*sctx
,
600 const amd_kernel_code_t
*code_object
,
601 const struct pipe_grid_info
*info
)
603 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
604 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
605 struct r600_resource
*input_buffer
= NULL
;
606 unsigned kernel_args_size
;
607 unsigned num_work_size_bytes
= program
->use_code_object_v2
? 0 : 36;
608 uint32_t kernel_args_offset
= 0;
609 uint32_t *kernel_args
;
610 void *kernel_args_ptr
;
611 uint64_t kernel_args_va
;
614 /* The extra num_work_size_bytes are for work group / work item size information */
615 kernel_args_size
= program
->input_size
+ num_work_size_bytes
;
617 u_upload_alloc(sctx
->b
.b
.const_uploader
, 0, kernel_args_size
,
618 sctx
->screen
->b
.info
.tcc_cache_line_size
,
620 (struct pipe_resource
**)&input_buffer
, &kernel_args_ptr
);
622 if (unlikely(!kernel_args_ptr
))
625 kernel_args
= (uint32_t*)kernel_args_ptr
;
626 kernel_args_va
= input_buffer
->gpu_address
+ kernel_args_offset
;
629 for (i
= 0; i
< 3; i
++) {
630 kernel_args
[i
] = info
->grid
[i
];
631 kernel_args
[i
+ 3] = info
->grid
[i
] * info
->block
[i
];
632 kernel_args
[i
+ 6] = info
->block
[i
];
636 memcpy(kernel_args
+ (num_work_size_bytes
/ 4), info
->input
,
637 program
->input_size
);
640 for (i
= 0; i
< (kernel_args_size
/ 4); i
++) {
641 COMPUTE_DBG(sctx
->screen
, "input %u : %u\n", i
,
646 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, input_buffer
,
647 RADEON_USAGE_READ
, RADEON_PRIO_CONST_BUFFER
);
650 si_setup_user_sgprs_co_v2(sctx
, code_object
, info
, kernel_args_va
);
652 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
653 radeon_emit(cs
, kernel_args_va
);
654 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI (kernel_args_va
>> 32) |
658 r600_resource_reference(&input_buffer
, NULL
);
663 static void si_setup_tgsi_grid(struct si_context
*sctx
,
664 const struct pipe_grid_info
*info
)
666 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
667 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
668 unsigned grid_size_reg
= R_00B900_COMPUTE_USER_DATA_0
+
669 4 * SI_NUM_RESOURCE_SGPRS
;
670 unsigned block_size_reg
= grid_size_reg
+
671 /* 12 bytes = 3 dwords. */
672 12 * program
->uses_grid_size
;
674 if (info
->indirect
) {
675 if (program
->uses_grid_size
) {
676 uint64_t base_va
= r600_resource(info
->indirect
)->gpu_address
;
677 uint64_t va
= base_va
+ info
->indirect_offset
;
680 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
681 (struct r600_resource
*)info
->indirect
,
682 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
684 for (i
= 0; i
< 3; ++i
) {
685 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
686 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
687 COPY_DATA_DST_SEL(COPY_DATA_REG
));
688 radeon_emit(cs
, (va
+ 4 * i
));
689 radeon_emit(cs
, (va
+ 4 * i
) >> 32);
690 radeon_emit(cs
, (grid_size_reg
>> 2) + i
);
695 if (program
->uses_grid_size
) {
696 radeon_set_sh_reg_seq(cs
, grid_size_reg
, 3);
697 radeon_emit(cs
, info
->grid
[0]);
698 radeon_emit(cs
, info
->grid
[1]);
699 radeon_emit(cs
, info
->grid
[2]);
701 if (program
->variable_group_size
&& program
->uses_block_size
) {
702 radeon_set_sh_reg_seq(cs
, block_size_reg
, 3);
703 radeon_emit(cs
, info
->block
[0]);
704 radeon_emit(cs
, info
->block
[1]);
705 radeon_emit(cs
, info
->block
[2]);
710 static void si_emit_dispatch_packets(struct si_context
*sctx
,
711 const struct pipe_grid_info
*info
)
713 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
714 bool render_cond_bit
= sctx
->b
.render_cond
&& !sctx
->b
.render_cond_force_off
;
715 unsigned waves_per_threadgroup
=
716 DIV_ROUND_UP(info
->block
[0] * info
->block
[1] * info
->block
[2], 64);
718 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
719 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0));
721 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
722 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(info
->block
[0]));
723 radeon_emit(cs
, S_00B820_NUM_THREAD_FULL(info
->block
[1]));
724 radeon_emit(cs
, S_00B824_NUM_THREAD_FULL(info
->block
[2]));
726 if (info
->indirect
) {
727 uint64_t base_va
= r600_resource(info
->indirect
)->gpu_address
;
729 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
730 (struct r600_resource
*)info
->indirect
,
731 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
733 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0) |
734 PKT3_SHADER_TYPE_S(1));
736 radeon_emit(cs
, base_va
);
737 radeon_emit(cs
, base_va
>> 32);
739 radeon_emit(cs
, PKT3(PKT3_DISPATCH_INDIRECT
, 1, render_cond_bit
) |
740 PKT3_SHADER_TYPE_S(1));
741 radeon_emit(cs
, info
->indirect_offset
);
744 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, render_cond_bit
) |
745 PKT3_SHADER_TYPE_S(1));
746 radeon_emit(cs
, info
->grid
[0]);
747 radeon_emit(cs
, info
->grid
[1]);
748 radeon_emit(cs
, info
->grid
[2]);
754 static void si_launch_grid(
755 struct pipe_context
*ctx
, const struct pipe_grid_info
*info
)
757 struct si_context
*sctx
= (struct si_context
*)ctx
;
758 struct si_compute
*program
= sctx
->cs_shader_state
.program
;
759 const amd_kernel_code_t
*code_object
=
760 si_compute_get_code_object(program
, info
->pc
);
762 /* HW bug workaround when CS threadgroups > 256 threads and async
763 * compute isn't used, i.e. only one compute job can run at a time.
764 * If async compute is possible, the threadgroup size must be limited
765 * to 256 threads on all queues to avoid the bug.
766 * Only SI and certain CIK chips are affected.
768 bool cs_regalloc_hang
=
769 (sctx
->b
.chip_class
== SI
||
770 sctx
->b
.family
== CHIP_BONAIRE
||
771 sctx
->b
.family
== CHIP_KABINI
) &&
772 info
->block
[0] * info
->block
[1] * info
->block
[2] > 256;
774 if (cs_regalloc_hang
)
775 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
776 SI_CONTEXT_CS_PARTIAL_FLUSH
;
778 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
&&
779 program
->shader
.compilation_failed
)
782 si_decompress_compute_textures(sctx
);
784 /* Add buffer sizes for memory checking in need_cs_space. */
785 r600_context_add_resource_size(ctx
, &program
->shader
.bo
->b
.b
);
786 /* TODO: add the scratch buffer */
788 if (info
->indirect
) {
789 r600_context_add_resource_size(ctx
, info
->indirect
);
791 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
792 if (sctx
->b
.chip_class
<= VI
&&
793 r600_resource(info
->indirect
)->TC_L2_dirty
) {
794 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
795 r600_resource(info
->indirect
)->TC_L2_dirty
= false;
799 si_need_cs_space(sctx
);
801 if (!sctx
->cs_shader_state
.initialized
)
802 si_initialize_compute(sctx
);
805 si_emit_cache_flush(sctx
);
807 if (!si_switch_compute_shader(sctx
, program
, &program
->shader
,
808 code_object
, info
->pc
))
811 si_upload_compute_shader_descriptors(sctx
);
812 si_emit_compute_shader_userdata(sctx
);
814 if (si_is_atom_dirty(sctx
, sctx
->atoms
.s
.render_cond
)) {
815 sctx
->atoms
.s
.render_cond
->emit(&sctx
->b
,
816 sctx
->atoms
.s
.render_cond
);
817 si_set_atom_dirty(sctx
, sctx
->atoms
.s
.render_cond
, false);
820 if ((program
->input_size
||
821 program
->ir_type
== PIPE_SHADER_IR_NATIVE
) &&
822 unlikely(!si_upload_compute_input(sctx
, code_object
, info
))) {
827 for (i
= 0; i
< MAX_GLOBAL_BUFFERS
; i
++) {
828 struct r600_resource
*buffer
=
829 (struct r600_resource
*)program
->global_buffers
[i
];
833 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, buffer
,
834 RADEON_USAGE_READWRITE
,
835 RADEON_PRIO_COMPUTE_GLOBAL
);
838 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
)
839 si_setup_tgsi_grid(sctx
, info
);
841 si_ce_pre_draw_synchronization(sctx
);
843 si_emit_dispatch_packets(sctx
, info
);
845 si_ce_post_draw_synchronization(sctx
);
847 sctx
->compute_is_busy
= true;
848 sctx
->b
.num_compute_calls
++;
849 if (sctx
->cs_shader_state
.uses_scratch
)
850 sctx
->b
.num_spill_compute_calls
++;
852 if (cs_regalloc_hang
)
853 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
857 static void si_delete_compute_state(struct pipe_context
*ctx
, void* state
){
858 struct si_compute
*program
= (struct si_compute
*)state
;
859 struct si_context
*sctx
= (struct si_context
*)ctx
;
865 if (program
->ir_type
== PIPE_SHADER_IR_TGSI
) {
866 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
,
868 util_queue_fence_destroy(&program
->ready
);
871 if (program
== sctx
->cs_shader_state
.program
)
872 sctx
->cs_shader_state
.program
= NULL
;
874 if (program
== sctx
->cs_shader_state
.emitted_program
)
875 sctx
->cs_shader_state
.emitted_program
= NULL
;
877 si_shader_destroy(&program
->shader
);
881 static void si_set_compute_resources(struct pipe_context
* ctx_
,
882 unsigned start
, unsigned count
,
883 struct pipe_surface
** surfaces
) { }
885 void si_init_compute_functions(struct si_context
*sctx
)
887 sctx
->b
.b
.create_compute_state
= si_create_compute_state
;
888 sctx
->b
.b
.delete_compute_state
= si_delete_compute_state
;
889 sctx
->b
.b
.bind_compute_state
= si_bind_compute_state
;
890 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
891 sctx
->b
.b
.set_compute_resources
= si_set_compute_resources
;
892 sctx
->b
.b
.set_global_binding
= si_set_global_binding
;
893 sctx
->b
.b
.launch_grid
= si_launch_grid
;