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radeonsi: move pipe debug callback to si_context
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_memory.h"
27 #include "util/u_upload_mgr.h"
28
29 #include "amd_kernel_code_t.h"
30 #include "radeon/r600_cs.h"
31 #include "si_pipe.h"
32 #include "si_compute.h"
33 #include "sid.h"
34
35 struct dispatch_packet {
36 uint16_t header;
37 uint16_t setup;
38 uint16_t workgroup_size_x;
39 uint16_t workgroup_size_y;
40 uint16_t workgroup_size_z;
41 uint16_t reserved0;
42 uint32_t grid_size_x;
43 uint32_t grid_size_y;
44 uint32_t grid_size_z;
45 uint32_t private_segment_size;
46 uint32_t group_segment_size;
47 uint64_t kernel_object;
48 uint64_t kernarg_address;
49 uint64_t reserved2;
50 };
51
52 static const amd_kernel_code_t *si_compute_get_code_object(
53 const struct si_compute *program,
54 uint64_t symbol_offset)
55 {
56 if (!program->use_code_object_v2) {
57 return NULL;
58 }
59 return (const amd_kernel_code_t*)
60 (program->shader.binary.code + symbol_offset);
61 }
62
63 static void code_object_to_config(const amd_kernel_code_t *code_object,
64 struct si_shader_config *out_config) {
65
66 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
67 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
68 out_config->num_sgprs = code_object->wavefront_sgpr_count;
69 out_config->num_vgprs = code_object->workitem_vgpr_count;
70 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
71 out_config->rsrc1 = rsrc1;
72 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
73 out_config->rsrc2 = rsrc2;
74 out_config->scratch_bytes_per_wave =
75 align(code_object->workitem_private_segment_byte_size * 64, 1024);
76 }
77
78 /* Asynchronous compute shader compilation. */
79 static void si_create_compute_state_async(void *job, int thread_index)
80 {
81 struct si_compute *program = (struct si_compute *)job;
82 struct si_shader *shader = &program->shader;
83 struct si_shader_selector sel;
84 LLVMTargetMachineRef tm;
85 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
86
87 if (thread_index >= 0) {
88 assert(thread_index < ARRAY_SIZE(program->screen->tm));
89 tm = program->screen->tm[thread_index];
90 if (!debug->async)
91 debug = NULL;
92 } else {
93 tm = program->compiler_ctx_state.tm;
94 }
95
96 memset(&sel, 0, sizeof(sel));
97
98 sel.screen = program->screen;
99 tgsi_scan_shader(program->tokens, &sel.info);
100 sel.tokens = program->tokens;
101 sel.type = PIPE_SHADER_COMPUTE;
102 sel.local_size = program->local_size;
103 si_get_active_slot_masks(&sel.info,
104 &program->active_const_and_shader_buffers,
105 &program->active_samplers_and_images);
106
107 program->shader.selector = &sel;
108 program->shader.is_monolithic = true;
109 program->uses_grid_size = sel.info.uses_grid_size;
110 program->uses_block_size = sel.info.uses_block_size;
111 program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
112 program->uses_bindless_images = sel.info.uses_bindless_images;
113
114 if (si_shader_create(program->screen, tm, &program->shader, debug)) {
115 program->shader.compilation_failed = true;
116 } else {
117 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
118 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
119 (sel.info.uses_grid_size ? 3 : 0) +
120 (sel.info.uses_block_size ? 3 : 0);
121
122 shader->config.rsrc1 =
123 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
124 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
125 S_00B848_DX10_CLAMP(1) |
126 S_00B848_FLOAT_MODE(shader->config.float_mode);
127
128 shader->config.rsrc2 =
129 S_00B84C_USER_SGPR(user_sgprs) |
130 S_00B84C_SCRATCH_EN(scratch_enabled) |
131 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
132 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
133 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
134 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
135 sel.info.uses_thread_id[1] ? 1 : 0) |
136 S_00B84C_LDS_SIZE(shader->config.lds_size);
137
138 program->variable_group_size =
139 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
140 }
141
142 FREE(program->tokens);
143 program->shader.selector = NULL;
144 }
145
146 static void *si_create_compute_state(
147 struct pipe_context *ctx,
148 const struct pipe_compute_state *cso)
149 {
150 struct si_context *sctx = (struct si_context *)ctx;
151 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
152 struct si_compute *program = CALLOC_STRUCT(si_compute);
153
154 pipe_reference_init(&program->reference, 1);
155 program->screen = (struct si_screen *)ctx->screen;
156 program->ir_type = cso->ir_type;
157 program->local_size = cso->req_local_mem;
158 program->private_size = cso->req_private_mem;
159 program->input_size = cso->req_input_mem;
160 program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
161 cso->ir_type == PIPE_SHADER_IR_NATIVE;
162
163 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
164 program->tokens = tgsi_dup_tokens(cso->prog);
165 if (!program->tokens) {
166 FREE(program);
167 return NULL;
168 }
169
170 program->compiler_ctx_state.tm = sctx->tm;
171 program->compiler_ctx_state.debug = sctx->debug;
172 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
173 p_atomic_inc(&sscreen->b.num_shaders_created);
174 util_queue_fence_init(&program->ready);
175
176 if ((sctx->debug.debug_message && !sctx->debug.async) ||
177 sctx->is_debug ||
178 si_can_dump_shader(&sscreen->b, PIPE_SHADER_COMPUTE))
179 si_create_compute_state_async(program, -1);
180 else
181 util_queue_add_job(&sscreen->shader_compiler_queue,
182 program, &program->ready,
183 si_create_compute_state_async, NULL);
184 } else {
185 const struct pipe_llvm_program_header *header;
186 const char *code;
187 header = cso->prog;
188 code = cso->prog + sizeof(struct pipe_llvm_program_header);
189
190 ac_elf_read(code, header->num_bytes, &program->shader.binary);
191 if (program->use_code_object_v2) {
192 const amd_kernel_code_t *code_object =
193 si_compute_get_code_object(program, 0);
194 code_object_to_config(code_object, &program->shader.config);
195 } else {
196 si_shader_binary_read_config(&program->shader.binary,
197 &program->shader.config, 0);
198 }
199 si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
200 PIPE_SHADER_COMPUTE, stderr, true);
201 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
202 fprintf(stderr, "LLVM failed to upload shader\n");
203 FREE(program);
204 return NULL;
205 }
206 }
207
208 return program;
209 }
210
211 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
212 {
213 struct si_context *sctx = (struct si_context*)ctx;
214 struct si_compute *program = (struct si_compute*)state;
215
216 sctx->cs_shader_state.program = program;
217 if (!program)
218 return;
219
220 /* Wait because we need active slot usage masks. */
221 if (program->ir_type == PIPE_SHADER_IR_TGSI)
222 util_queue_fence_wait(&program->ready);
223
224 si_set_active_descriptors(sctx,
225 SI_DESCS_FIRST_COMPUTE +
226 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
227 program->active_const_and_shader_buffers);
228 si_set_active_descriptors(sctx,
229 SI_DESCS_FIRST_COMPUTE +
230 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
231 program->active_samplers_and_images);
232 }
233
234 static void si_set_global_binding(
235 struct pipe_context *ctx, unsigned first, unsigned n,
236 struct pipe_resource **resources,
237 uint32_t **handles)
238 {
239 unsigned i;
240 struct si_context *sctx = (struct si_context*)ctx;
241 struct si_compute *program = sctx->cs_shader_state.program;
242
243 assert(first + n <= MAX_GLOBAL_BUFFERS);
244
245 if (!resources) {
246 for (i = 0; i < n; i++) {
247 pipe_resource_reference(&program->global_buffers[first + i], NULL);
248 }
249 return;
250 }
251
252 for (i = 0; i < n; i++) {
253 uint64_t va;
254 uint32_t offset;
255 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
256 va = r600_resource(resources[i])->gpu_address;
257 offset = util_le32_to_cpu(*handles[i]);
258 va += offset;
259 va = util_cpu_to_le64(va);
260 memcpy(handles[i], &va, sizeof(va));
261 }
262 }
263
264 static void si_initialize_compute(struct si_context *sctx)
265 {
266 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
267 uint64_t bc_va;
268
269 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
270 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
271 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
272 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
273
274 if (sctx->b.chip_class >= CIK) {
275 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
276 radeon_set_sh_reg_seq(cs,
277 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
278 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
279 S_00B864_SH1_CU_EN(0xffff));
280 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
281 S_00B868_SH1_CU_EN(0xffff));
282 }
283
284 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
285 * and is now per pipe, so it should be handled in the
286 * kernel if we want to use something other than the default value,
287 * which is now 0x22f.
288 */
289 if (sctx->b.chip_class <= SI) {
290 /* XXX: This should be:
291 * (number of compute units) * 4 * (waves per simd) - 1 */
292
293 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
294 0x190 /* Default value */);
295 }
296
297 /* Set the pointer to border colors. */
298 bc_va = sctx->border_color_buffer->gpu_address;
299
300 if (sctx->b.chip_class >= CIK) {
301 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
302 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
303 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
304 } else {
305 if (sctx->screen->b.info.drm_major == 3 ||
306 (sctx->screen->b.info.drm_major == 2 &&
307 sctx->screen->b.info.drm_minor >= 48)) {
308 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
309 bc_va >> 8);
310 }
311 }
312
313 sctx->cs_shader_state.emitted_program = NULL;
314 sctx->cs_shader_state.initialized = true;
315 }
316
317 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
318 struct si_shader *shader,
319 struct si_shader_config *config)
320 {
321 uint64_t scratch_bo_size, scratch_needed;
322 scratch_bo_size = 0;
323 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
324 if (sctx->compute_scratch_buffer)
325 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
326
327 if (scratch_bo_size < scratch_needed) {
328 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
329
330 sctx->compute_scratch_buffer = (struct r600_resource*)
331 si_aligned_buffer_create(&sctx->screen->b.b,
332 R600_RESOURCE_FLAG_UNMAPPABLE,
333 PIPE_USAGE_DEFAULT,
334 scratch_needed, 256);
335
336 if (!sctx->compute_scratch_buffer)
337 return false;
338 }
339
340 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
341 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
342
343 si_shader_apply_scratch_relocs(shader, scratch_va);
344
345 if (si_shader_binary_upload(sctx->screen, shader))
346 return false;
347
348 r600_resource_reference(&shader->scratch_bo,
349 sctx->compute_scratch_buffer);
350 }
351
352 return true;
353 }
354
355 static bool si_switch_compute_shader(struct si_context *sctx,
356 struct si_compute *program,
357 struct si_shader *shader,
358 const amd_kernel_code_t *code_object,
359 unsigned offset)
360 {
361 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
362 struct si_shader_config inline_config = {0};
363 struct si_shader_config *config;
364 uint64_t shader_va;
365
366 if (sctx->cs_shader_state.emitted_program == program &&
367 sctx->cs_shader_state.offset == offset)
368 return true;
369
370 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
371 config = &shader->config;
372 } else {
373 unsigned lds_blocks;
374
375 config = &inline_config;
376 if (code_object) {
377 code_object_to_config(code_object, config);
378 } else {
379 si_shader_binary_read_config(&shader->binary, config, offset);
380 }
381
382 lds_blocks = config->lds_size;
383 /* XXX: We are over allocating LDS. For SI, the shader reports
384 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
385 * allocated in the shader and 4 bytes allocated by the state
386 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
387 */
388 if (sctx->b.chip_class <= SI) {
389 lds_blocks += align(program->local_size, 256) >> 8;
390 } else {
391 lds_blocks += align(program->local_size, 512) >> 9;
392 }
393
394 /* TODO: use si_multiwave_lds_size_workaround */
395 assert(lds_blocks <= 0xFF);
396
397 config->rsrc2 &= C_00B84C_LDS_SIZE;
398 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
399 }
400
401 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
402 return false;
403
404 if (shader->scratch_bo) {
405 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
406 "Total Scratch: %u bytes\n", sctx->scratch_waves,
407 config->scratch_bytes_per_wave,
408 config->scratch_bytes_per_wave *
409 sctx->scratch_waves);
410
411 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
412 shader->scratch_bo, RADEON_USAGE_READWRITE,
413 RADEON_PRIO_SCRATCH_BUFFER);
414 }
415
416 /* Prefetch the compute shader to TC L2.
417 *
418 * We should also prefetch graphics shaders if a compute dispatch was
419 * the last command, and the compute shader if a draw call was the last
420 * command. However, that would add more complexity and we're likely
421 * to get a shader state change in that case anyway.
422 */
423 if (sctx->b.chip_class >= CIK) {
424 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
425 0, program->shader.bo->b.b.width0);
426 }
427
428 shader_va = shader->bo->gpu_address + offset;
429 if (program->use_code_object_v2) {
430 /* Shader code is placed after the amd_kernel_code_t
431 * struct. */
432 shader_va += sizeof(amd_kernel_code_t);
433 }
434
435 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
436 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
437
438 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
439 radeon_emit(cs, shader_va >> 8);
440 radeon_emit(cs, shader_va >> 40);
441
442 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
443 radeon_emit(cs, config->rsrc1);
444 radeon_emit(cs, config->rsrc2);
445
446 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
447 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
448
449 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
450 S_00B860_WAVES(sctx->scratch_waves)
451 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
452
453 sctx->cs_shader_state.emitted_program = program;
454 sctx->cs_shader_state.offset = offset;
455 sctx->cs_shader_state.uses_scratch =
456 config->scratch_bytes_per_wave != 0;
457
458 return true;
459 }
460
461 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
462 const amd_kernel_code_t *code_object,
463 unsigned user_sgpr)
464 {
465 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
466 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
467
468 unsigned max_private_element_size = AMD_HSA_BITS_GET(
469 code_object->code_properties,
470 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
471
472 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
473 uint32_t scratch_dword1 =
474 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
475 S_008F04_SWIZZLE_ENABLE(1);
476
477 /* Disable address clamping */
478 uint32_t scratch_dword2 = 0xffffffff;
479 uint32_t scratch_dword3 =
480 S_008F0C_INDEX_STRIDE(3) |
481 S_008F0C_ADD_TID_ENABLE(1);
482
483 if (sctx->b.chip_class >= GFX9) {
484 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
485 } else {
486 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
487
488 if (sctx->b.chip_class < VI) {
489 /* BUF_DATA_FORMAT is ignored, but it cannot be
490 * BUF_DATA_FORMAT_INVALID. */
491 scratch_dword3 |=
492 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
493 }
494 }
495
496 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
497 (user_sgpr * 4), 4);
498 radeon_emit(cs, scratch_dword0);
499 radeon_emit(cs, scratch_dword1);
500 radeon_emit(cs, scratch_dword2);
501 radeon_emit(cs, scratch_dword3);
502 }
503
504 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
505 const amd_kernel_code_t *code_object,
506 const struct pipe_grid_info *info,
507 uint64_t kernel_args_va)
508 {
509 struct si_compute *program = sctx->cs_shader_state.program;
510 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
511
512 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
513 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
514 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
515 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
516 };
517
518 unsigned i, user_sgpr = 0;
519 if (AMD_HSA_BITS_GET(code_object->code_properties,
520 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
521 if (code_object->workitem_private_segment_byte_size > 0) {
522 setup_scratch_rsrc_user_sgprs(sctx, code_object,
523 user_sgpr);
524 }
525 user_sgpr += 4;
526 }
527
528 if (AMD_HSA_BITS_GET(code_object->code_properties,
529 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
530 struct dispatch_packet dispatch;
531 unsigned dispatch_offset;
532 struct r600_resource *dispatch_buf = NULL;
533 uint64_t dispatch_va;
534
535 /* Upload dispatch ptr */
536 memset(&dispatch, 0, sizeof(dispatch));
537
538 dispatch.workgroup_size_x = info->block[0];
539 dispatch.workgroup_size_y = info->block[1];
540 dispatch.workgroup_size_z = info->block[2];
541
542 dispatch.grid_size_x = info->grid[0] * info->block[0];
543 dispatch.grid_size_y = info->grid[1] * info->block[1];
544 dispatch.grid_size_z = info->grid[2] * info->block[2];
545
546 dispatch.private_segment_size = program->private_size;
547 dispatch.group_segment_size = program->local_size;
548
549 dispatch.kernarg_address = kernel_args_va;
550
551 u_upload_data(sctx->b.b.const_uploader, 0, sizeof(dispatch),
552 256, &dispatch, &dispatch_offset,
553 (struct pipe_resource**)&dispatch_buf);
554
555 if (!dispatch_buf) {
556 fprintf(stderr, "Error: Failed to allocate dispatch "
557 "packet.");
558 }
559 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
560 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
561
562 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
563
564 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
565 (user_sgpr * 4), 2);
566 radeon_emit(cs, dispatch_va);
567 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
568 S_008F04_STRIDE(0));
569
570 r600_resource_reference(&dispatch_buf, NULL);
571 user_sgpr += 2;
572 }
573
574 if (AMD_HSA_BITS_GET(code_object->code_properties,
575 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
576 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
577 (user_sgpr * 4), 2);
578 radeon_emit(cs, kernel_args_va);
579 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
580 S_008F04_STRIDE(0));
581 user_sgpr += 2;
582 }
583
584 for (i = 0; i < 3 && user_sgpr < 16; i++) {
585 if (code_object->code_properties & workgroup_count_masks[i]) {
586 radeon_set_sh_reg_seq(cs,
587 R_00B900_COMPUTE_USER_DATA_0 +
588 (user_sgpr * 4), 1);
589 radeon_emit(cs, info->grid[i]);
590 user_sgpr += 1;
591 }
592 }
593 }
594
595 static bool si_upload_compute_input(struct si_context *sctx,
596 const amd_kernel_code_t *code_object,
597 const struct pipe_grid_info *info)
598 {
599 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
600 struct si_compute *program = sctx->cs_shader_state.program;
601 struct r600_resource *input_buffer = NULL;
602 unsigned kernel_args_size;
603 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
604 uint32_t kernel_args_offset = 0;
605 uint32_t *kernel_args;
606 void *kernel_args_ptr;
607 uint64_t kernel_args_va;
608 unsigned i;
609
610 /* The extra num_work_size_bytes are for work group / work item size information */
611 kernel_args_size = program->input_size + num_work_size_bytes;
612
613 u_upload_alloc(sctx->b.b.const_uploader, 0, kernel_args_size,
614 sctx->screen->b.info.tcc_cache_line_size,
615 &kernel_args_offset,
616 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
617
618 if (unlikely(!kernel_args_ptr))
619 return false;
620
621 kernel_args = (uint32_t*)kernel_args_ptr;
622 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
623
624 if (!code_object) {
625 for (i = 0; i < 3; i++) {
626 kernel_args[i] = info->grid[i];
627 kernel_args[i + 3] = info->grid[i] * info->block[i];
628 kernel_args[i + 6] = info->block[i];
629 }
630 }
631
632 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
633 program->input_size);
634
635
636 for (i = 0; i < (kernel_args_size / 4); i++) {
637 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
638 kernel_args[i]);
639 }
640
641
642 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
643 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
644
645 if (code_object) {
646 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
647 } else {
648 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
649 radeon_emit(cs, kernel_args_va);
650 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
651 S_008F04_STRIDE(0));
652 }
653
654 r600_resource_reference(&input_buffer, NULL);
655
656 return true;
657 }
658
659 static void si_setup_tgsi_grid(struct si_context *sctx,
660 const struct pipe_grid_info *info)
661 {
662 struct si_compute *program = sctx->cs_shader_state.program;
663 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
664 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
665 4 * SI_NUM_RESOURCE_SGPRS;
666 unsigned block_size_reg = grid_size_reg +
667 /* 12 bytes = 3 dwords. */
668 12 * program->uses_grid_size;
669
670 if (info->indirect) {
671 if (program->uses_grid_size) {
672 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
673 uint64_t va = base_va + info->indirect_offset;
674 int i;
675
676 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
677 (struct r600_resource *)info->indirect,
678 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
679
680 for (i = 0; i < 3; ++i) {
681 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
682 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
683 COPY_DATA_DST_SEL(COPY_DATA_REG));
684 radeon_emit(cs, (va + 4 * i));
685 radeon_emit(cs, (va + 4 * i) >> 32);
686 radeon_emit(cs, (grid_size_reg >> 2) + i);
687 radeon_emit(cs, 0);
688 }
689 }
690 } else {
691 if (program->uses_grid_size) {
692 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
693 radeon_emit(cs, info->grid[0]);
694 radeon_emit(cs, info->grid[1]);
695 radeon_emit(cs, info->grid[2]);
696 }
697 if (program->variable_group_size && program->uses_block_size) {
698 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
699 radeon_emit(cs, info->block[0]);
700 radeon_emit(cs, info->block[1]);
701 radeon_emit(cs, info->block[2]);
702 }
703 }
704 }
705
706 static void si_emit_dispatch_packets(struct si_context *sctx,
707 const struct pipe_grid_info *info)
708 {
709 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
710 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
711 unsigned waves_per_threadgroup =
712 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
713
714 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
715 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
716
717 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
718 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
719 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
720 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
721
722 unsigned dispatch_initiator =
723 S_00B800_COMPUTE_SHADER_EN(1) |
724 S_00B800_FORCE_START_AT_000(1) |
725 /* If the KMD allows it (there is a KMD hw register for it),
726 * allow launching waves out-of-order. (same as Vulkan) */
727 S_00B800_ORDER_MODE(sctx->b.chip_class >= CIK);
728
729 if (info->indirect) {
730 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
731
732 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
733 (struct r600_resource *)info->indirect,
734 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
735
736 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
737 PKT3_SHADER_TYPE_S(1));
738 radeon_emit(cs, 1);
739 radeon_emit(cs, base_va);
740 radeon_emit(cs, base_va >> 32);
741
742 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
743 PKT3_SHADER_TYPE_S(1));
744 radeon_emit(cs, info->indirect_offset);
745 radeon_emit(cs, dispatch_initiator);
746 } else {
747 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
748 PKT3_SHADER_TYPE_S(1));
749 radeon_emit(cs, info->grid[0]);
750 radeon_emit(cs, info->grid[1]);
751 radeon_emit(cs, info->grid[2]);
752 radeon_emit(cs, dispatch_initiator);
753 }
754 }
755
756
757 static void si_launch_grid(
758 struct pipe_context *ctx, const struct pipe_grid_info *info)
759 {
760 struct si_context *sctx = (struct si_context*)ctx;
761 struct si_compute *program = sctx->cs_shader_state.program;
762 const amd_kernel_code_t *code_object =
763 si_compute_get_code_object(program, info->pc);
764 int i;
765 /* HW bug workaround when CS threadgroups > 256 threads and async
766 * compute isn't used, i.e. only one compute job can run at a time.
767 * If async compute is possible, the threadgroup size must be limited
768 * to 256 threads on all queues to avoid the bug.
769 * Only SI and certain CIK chips are affected.
770 */
771 bool cs_regalloc_hang =
772 (sctx->b.chip_class == SI ||
773 sctx->b.family == CHIP_BONAIRE ||
774 sctx->b.family == CHIP_KABINI) &&
775 info->block[0] * info->block[1] * info->block[2] > 256;
776
777 if (cs_regalloc_hang)
778 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
779 SI_CONTEXT_CS_PARTIAL_FLUSH;
780
781 if (program->ir_type == PIPE_SHADER_IR_TGSI &&
782 program->shader.compilation_failed)
783 return;
784
785 if (sctx->b.last_num_draw_calls != sctx->b.num_draw_calls) {
786 si_update_fb_dirtiness_after_rendering(sctx);
787 sctx->b.last_num_draw_calls = sctx->b.num_draw_calls;
788 }
789
790 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
791
792 /* Add buffer sizes for memory checking in need_cs_space. */
793 r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
794 /* TODO: add the scratch buffer */
795
796 if (info->indirect) {
797 r600_context_add_resource_size(ctx, info->indirect);
798
799 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
800 if (sctx->b.chip_class <= VI &&
801 r600_resource(info->indirect)->TC_L2_dirty) {
802 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
803 r600_resource(info->indirect)->TC_L2_dirty = false;
804 }
805 }
806
807 si_need_cs_space(sctx);
808
809 if (!sctx->cs_shader_state.initialized)
810 si_initialize_compute(sctx);
811
812 if (sctx->b.flags)
813 si_emit_cache_flush(sctx);
814
815 if (!si_switch_compute_shader(sctx, program, &program->shader,
816 code_object, info->pc))
817 return;
818
819 si_upload_compute_shader_descriptors(sctx);
820 si_emit_compute_shader_pointers(sctx);
821
822 if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
823 sctx->atoms.s.render_cond->emit(&sctx->b,
824 sctx->atoms.s.render_cond);
825 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
826 }
827
828 if ((program->input_size ||
829 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
830 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
831 return;
832 }
833
834 /* Global buffers */
835 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
836 struct r600_resource *buffer =
837 (struct r600_resource*)program->global_buffers[i];
838 if (!buffer) {
839 continue;
840 }
841 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
842 RADEON_USAGE_READWRITE,
843 RADEON_PRIO_COMPUTE_GLOBAL);
844 }
845
846 if (program->ir_type == PIPE_SHADER_IR_TGSI)
847 si_setup_tgsi_grid(sctx, info);
848
849 si_emit_dispatch_packets(sctx, info);
850
851 if (unlikely(sctx->current_saved_cs)) {
852 si_trace_emit(sctx);
853 si_log_compute_state(sctx, sctx->b.log);
854 }
855
856 sctx->compute_is_busy = true;
857 sctx->b.num_compute_calls++;
858 if (sctx->cs_shader_state.uses_scratch)
859 sctx->b.num_spill_compute_calls++;
860
861 if (cs_regalloc_hang)
862 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
863 }
864
865 void si_destroy_compute(struct si_compute *program)
866 {
867 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
868 util_queue_drop_job(&program->screen->shader_compiler_queue,
869 &program->ready);
870 util_queue_fence_destroy(&program->ready);
871 }
872
873 si_shader_destroy(&program->shader);
874 FREE(program);
875 }
876
877 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
878 struct si_compute *program = (struct si_compute *)state;
879 struct si_context *sctx = (struct si_context*)ctx;
880
881 if (!state)
882 return;
883
884 if (program == sctx->cs_shader_state.program)
885 sctx->cs_shader_state.program = NULL;
886
887 if (program == sctx->cs_shader_state.emitted_program)
888 sctx->cs_shader_state.emitted_program = NULL;
889
890 si_compute_reference(&program, NULL);
891 }
892
893 static void si_set_compute_resources(struct pipe_context * ctx_,
894 unsigned start, unsigned count,
895 struct pipe_surface ** surfaces) { }
896
897 void si_init_compute_functions(struct si_context *sctx)
898 {
899 sctx->b.b.create_compute_state = si_create_compute_state;
900 sctx->b.b.delete_compute_state = si_delete_compute_state;
901 sctx->b.b.bind_compute_state = si_bind_compute_state;
902 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
903 sctx->b.b.set_compute_resources = si_set_compute_resources;
904 sctx->b.b.set_global_binding = si_set_global_binding;
905 sctx->b.b.launch_grid = si_launch_grid;
906 }