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radeonsi: always use async compiles when creating shader/compute states
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include "tgsi/tgsi_parse.h"
26 #include "util/u_async_debug.h"
27 #include "util/u_memory.h"
28 #include "util/u_upload_mgr.h"
29
30 #include "amd_kernel_code_t.h"
31 #include "radeon/r600_cs.h"
32 #include "si_pipe.h"
33 #include "si_compute.h"
34 #include "sid.h"
35
36 struct dispatch_packet {
37 uint16_t header;
38 uint16_t setup;
39 uint16_t workgroup_size_x;
40 uint16_t workgroup_size_y;
41 uint16_t workgroup_size_z;
42 uint16_t reserved0;
43 uint32_t grid_size_x;
44 uint32_t grid_size_y;
45 uint32_t grid_size_z;
46 uint32_t private_segment_size;
47 uint32_t group_segment_size;
48 uint64_t kernel_object;
49 uint64_t kernarg_address;
50 uint64_t reserved2;
51 };
52
53 static const amd_kernel_code_t *si_compute_get_code_object(
54 const struct si_compute *program,
55 uint64_t symbol_offset)
56 {
57 if (!program->use_code_object_v2) {
58 return NULL;
59 }
60 return (const amd_kernel_code_t*)
61 (program->shader.binary.code + symbol_offset);
62 }
63
64 static void code_object_to_config(const amd_kernel_code_t *code_object,
65 struct si_shader_config *out_config) {
66
67 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
68 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
69 out_config->num_sgprs = code_object->wavefront_sgpr_count;
70 out_config->num_vgprs = code_object->workitem_vgpr_count;
71 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
72 out_config->rsrc1 = rsrc1;
73 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
74 out_config->rsrc2 = rsrc2;
75 out_config->scratch_bytes_per_wave =
76 align(code_object->workitem_private_segment_byte_size * 64, 1024);
77 }
78
79 /* Asynchronous compute shader compilation. */
80 static void si_create_compute_state_async(void *job, int thread_index)
81 {
82 struct si_compute *program = (struct si_compute *)job;
83 struct si_shader *shader = &program->shader;
84 struct si_shader_selector sel;
85 LLVMTargetMachineRef tm;
86 struct pipe_debug_callback *debug = &program->compiler_ctx_state.debug;
87
88 assert(!debug->debug_message || debug->async);
89 assert(thread_index >= 0);
90 assert(thread_index < ARRAY_SIZE(program->screen->tm));
91 tm = program->screen->tm[thread_index];
92
93 memset(&sel, 0, sizeof(sel));
94
95 sel.screen = program->screen;
96 tgsi_scan_shader(program->tokens, &sel.info);
97 sel.tokens = program->tokens;
98 sel.type = PIPE_SHADER_COMPUTE;
99 sel.local_size = program->local_size;
100 si_get_active_slot_masks(&sel.info,
101 &program->active_const_and_shader_buffers,
102 &program->active_samplers_and_images);
103
104 program->shader.selector = &sel;
105 program->shader.is_monolithic = true;
106 program->uses_grid_size = sel.info.uses_grid_size;
107 program->uses_block_size = sel.info.uses_block_size;
108 program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
109 program->uses_bindless_images = sel.info.uses_bindless_images;
110
111 if (si_shader_create(program->screen, tm, &program->shader, debug)) {
112 program->shader.compilation_failed = true;
113 } else {
114 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
115 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
116 (sel.info.uses_grid_size ? 3 : 0) +
117 (sel.info.uses_block_size ? 3 : 0);
118
119 shader->config.rsrc1 =
120 S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
121 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
122 S_00B848_DX10_CLAMP(1) |
123 S_00B848_FLOAT_MODE(shader->config.float_mode);
124
125 shader->config.rsrc2 =
126 S_00B84C_USER_SGPR(user_sgprs) |
127 S_00B84C_SCRATCH_EN(scratch_enabled) |
128 S_00B84C_TGID_X_EN(sel.info.uses_block_id[0]) |
129 S_00B84C_TGID_Y_EN(sel.info.uses_block_id[1]) |
130 S_00B84C_TGID_Z_EN(sel.info.uses_block_id[2]) |
131 S_00B84C_TIDIG_COMP_CNT(sel.info.uses_thread_id[2] ? 2 :
132 sel.info.uses_thread_id[1] ? 1 : 0) |
133 S_00B84C_LDS_SIZE(shader->config.lds_size);
134
135 program->variable_group_size =
136 sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
137 }
138
139 FREE(program->tokens);
140 program->shader.selector = NULL;
141 }
142
143 static void *si_create_compute_state(
144 struct pipe_context *ctx,
145 const struct pipe_compute_state *cso)
146 {
147 struct si_context *sctx = (struct si_context *)ctx;
148 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
149 struct si_compute *program = CALLOC_STRUCT(si_compute);
150
151 pipe_reference_init(&program->reference, 1);
152 program->screen = (struct si_screen *)ctx->screen;
153 program->ir_type = cso->ir_type;
154 program->local_size = cso->req_local_mem;
155 program->private_size = cso->req_private_mem;
156 program->input_size = cso->req_input_mem;
157 program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
158 cso->ir_type == PIPE_SHADER_IR_NATIVE;
159
160 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
161 program->tokens = tgsi_dup_tokens(cso->prog);
162 if (!program->tokens) {
163 FREE(program);
164 return NULL;
165 }
166
167 program->compiler_ctx_state.debug = sctx->debug;
168 program->compiler_ctx_state.is_debug_context = sctx->is_debug;
169 p_atomic_inc(&sscreen->b.num_shaders_created);
170 util_queue_fence_init(&program->ready);
171
172 struct util_async_debug_callback async_debug;
173 bool wait =
174 (sctx->debug.debug_message && !sctx->debug.async) ||
175 sctx->is_debug ||
176 si_can_dump_shader(&sscreen->b, PIPE_SHADER_COMPUTE);
177
178 if (wait) {
179 u_async_debug_init(&async_debug);
180 program->compiler_ctx_state.debug = async_debug.base;
181 }
182
183 util_queue_add_job(&sscreen->shader_compiler_queue,
184 program, &program->ready,
185 si_create_compute_state_async, NULL);
186
187 if (wait) {
188 util_queue_fence_wait(&program->ready);
189 u_async_debug_drain(&async_debug, &sctx->debug);
190 u_async_debug_cleanup(&async_debug);
191 }
192 } else {
193 const struct pipe_llvm_program_header *header;
194 const char *code;
195 header = cso->prog;
196 code = cso->prog + sizeof(struct pipe_llvm_program_header);
197
198 ac_elf_read(code, header->num_bytes, &program->shader.binary);
199 if (program->use_code_object_v2) {
200 const amd_kernel_code_t *code_object =
201 si_compute_get_code_object(program, 0);
202 code_object_to_config(code_object, &program->shader.config);
203 } else {
204 si_shader_binary_read_config(&program->shader.binary,
205 &program->shader.config, 0);
206 }
207 si_shader_dump(sctx->screen, &program->shader, &sctx->debug,
208 PIPE_SHADER_COMPUTE, stderr, true);
209 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
210 fprintf(stderr, "LLVM failed to upload shader\n");
211 FREE(program);
212 return NULL;
213 }
214 }
215
216 return program;
217 }
218
219 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
220 {
221 struct si_context *sctx = (struct si_context*)ctx;
222 struct si_compute *program = (struct si_compute*)state;
223
224 sctx->cs_shader_state.program = program;
225 if (!program)
226 return;
227
228 /* Wait because we need active slot usage masks. */
229 if (program->ir_type == PIPE_SHADER_IR_TGSI)
230 util_queue_fence_wait(&program->ready);
231
232 si_set_active_descriptors(sctx,
233 SI_DESCS_FIRST_COMPUTE +
234 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
235 program->active_const_and_shader_buffers);
236 si_set_active_descriptors(sctx,
237 SI_DESCS_FIRST_COMPUTE +
238 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
239 program->active_samplers_and_images);
240 }
241
242 static void si_set_global_binding(
243 struct pipe_context *ctx, unsigned first, unsigned n,
244 struct pipe_resource **resources,
245 uint32_t **handles)
246 {
247 unsigned i;
248 struct si_context *sctx = (struct si_context*)ctx;
249 struct si_compute *program = sctx->cs_shader_state.program;
250
251 assert(first + n <= MAX_GLOBAL_BUFFERS);
252
253 if (!resources) {
254 for (i = 0; i < n; i++) {
255 pipe_resource_reference(&program->global_buffers[first + i], NULL);
256 }
257 return;
258 }
259
260 for (i = 0; i < n; i++) {
261 uint64_t va;
262 uint32_t offset;
263 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
264 va = r600_resource(resources[i])->gpu_address;
265 offset = util_le32_to_cpu(*handles[i]);
266 va += offset;
267 va = util_cpu_to_le64(va);
268 memcpy(handles[i], &va, sizeof(va));
269 }
270 }
271
272 static void si_initialize_compute(struct si_context *sctx)
273 {
274 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
275 uint64_t bc_va;
276
277 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
278 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
279 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
280 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
281
282 if (sctx->b.chip_class >= CIK) {
283 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
284 radeon_set_sh_reg_seq(cs,
285 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
286 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
287 S_00B864_SH1_CU_EN(0xffff));
288 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
289 S_00B868_SH1_CU_EN(0xffff));
290 }
291
292 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
293 * and is now per pipe, so it should be handled in the
294 * kernel if we want to use something other than the default value,
295 * which is now 0x22f.
296 */
297 if (sctx->b.chip_class <= SI) {
298 /* XXX: This should be:
299 * (number of compute units) * 4 * (waves per simd) - 1 */
300
301 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
302 0x190 /* Default value */);
303 }
304
305 /* Set the pointer to border colors. */
306 bc_va = sctx->border_color_buffer->gpu_address;
307
308 if (sctx->b.chip_class >= CIK) {
309 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
310 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
311 radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
312 } else {
313 if (sctx->screen->b.info.drm_major == 3 ||
314 (sctx->screen->b.info.drm_major == 2 &&
315 sctx->screen->b.info.drm_minor >= 48)) {
316 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
317 bc_va >> 8);
318 }
319 }
320
321 sctx->cs_shader_state.emitted_program = NULL;
322 sctx->cs_shader_state.initialized = true;
323 }
324
325 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
326 struct si_shader *shader,
327 struct si_shader_config *config)
328 {
329 uint64_t scratch_bo_size, scratch_needed;
330 scratch_bo_size = 0;
331 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
332 if (sctx->compute_scratch_buffer)
333 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
334
335 if (scratch_bo_size < scratch_needed) {
336 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
337
338 sctx->compute_scratch_buffer = (struct r600_resource*)
339 si_aligned_buffer_create(&sctx->screen->b.b,
340 R600_RESOURCE_FLAG_UNMAPPABLE,
341 PIPE_USAGE_DEFAULT,
342 scratch_needed, 256);
343
344 if (!sctx->compute_scratch_buffer)
345 return false;
346 }
347
348 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
349 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
350
351 si_shader_apply_scratch_relocs(shader, scratch_va);
352
353 if (si_shader_binary_upload(sctx->screen, shader))
354 return false;
355
356 r600_resource_reference(&shader->scratch_bo,
357 sctx->compute_scratch_buffer);
358 }
359
360 return true;
361 }
362
363 static bool si_switch_compute_shader(struct si_context *sctx,
364 struct si_compute *program,
365 struct si_shader *shader,
366 const amd_kernel_code_t *code_object,
367 unsigned offset)
368 {
369 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
370 struct si_shader_config inline_config = {0};
371 struct si_shader_config *config;
372 uint64_t shader_va;
373
374 if (sctx->cs_shader_state.emitted_program == program &&
375 sctx->cs_shader_state.offset == offset)
376 return true;
377
378 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
379 config = &shader->config;
380 } else {
381 unsigned lds_blocks;
382
383 config = &inline_config;
384 if (code_object) {
385 code_object_to_config(code_object, config);
386 } else {
387 si_shader_binary_read_config(&shader->binary, config, offset);
388 }
389
390 lds_blocks = config->lds_size;
391 /* XXX: We are over allocating LDS. For SI, the shader reports
392 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
393 * allocated in the shader and 4 bytes allocated by the state
394 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
395 */
396 if (sctx->b.chip_class <= SI) {
397 lds_blocks += align(program->local_size, 256) >> 8;
398 } else {
399 lds_blocks += align(program->local_size, 512) >> 9;
400 }
401
402 /* TODO: use si_multiwave_lds_size_workaround */
403 assert(lds_blocks <= 0xFF);
404
405 config->rsrc2 &= C_00B84C_LDS_SIZE;
406 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
407 }
408
409 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
410 return false;
411
412 if (shader->scratch_bo) {
413 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
414 "Total Scratch: %u bytes\n", sctx->scratch_waves,
415 config->scratch_bytes_per_wave,
416 config->scratch_bytes_per_wave *
417 sctx->scratch_waves);
418
419 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
420 shader->scratch_bo, RADEON_USAGE_READWRITE,
421 RADEON_PRIO_SCRATCH_BUFFER);
422 }
423
424 /* Prefetch the compute shader to TC L2.
425 *
426 * We should also prefetch graphics shaders if a compute dispatch was
427 * the last command, and the compute shader if a draw call was the last
428 * command. However, that would add more complexity and we're likely
429 * to get a shader state change in that case anyway.
430 */
431 if (sctx->b.chip_class >= CIK) {
432 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
433 0, program->shader.bo->b.b.width0);
434 }
435
436 shader_va = shader->bo->gpu_address + offset;
437 if (program->use_code_object_v2) {
438 /* Shader code is placed after the amd_kernel_code_t
439 * struct. */
440 shader_va += sizeof(amd_kernel_code_t);
441 }
442
443 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
444 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
445
446 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
447 radeon_emit(cs, shader_va >> 8);
448 radeon_emit(cs, shader_va >> 40);
449
450 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
451 radeon_emit(cs, config->rsrc1);
452 radeon_emit(cs, config->rsrc2);
453
454 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
455 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
456
457 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
458 S_00B860_WAVES(sctx->scratch_waves)
459 | S_00B860_WAVESIZE(config->scratch_bytes_per_wave >> 10));
460
461 sctx->cs_shader_state.emitted_program = program;
462 sctx->cs_shader_state.offset = offset;
463 sctx->cs_shader_state.uses_scratch =
464 config->scratch_bytes_per_wave != 0;
465
466 return true;
467 }
468
469 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
470 const amd_kernel_code_t *code_object,
471 unsigned user_sgpr)
472 {
473 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
474 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
475
476 unsigned max_private_element_size = AMD_HSA_BITS_GET(
477 code_object->code_properties,
478 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
479
480 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
481 uint32_t scratch_dword1 =
482 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
483 S_008F04_SWIZZLE_ENABLE(1);
484
485 /* Disable address clamping */
486 uint32_t scratch_dword2 = 0xffffffff;
487 uint32_t scratch_dword3 =
488 S_008F0C_INDEX_STRIDE(3) |
489 S_008F0C_ADD_TID_ENABLE(1);
490
491 if (sctx->b.chip_class >= GFX9) {
492 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
493 } else {
494 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
495
496 if (sctx->b.chip_class < VI) {
497 /* BUF_DATA_FORMAT is ignored, but it cannot be
498 * BUF_DATA_FORMAT_INVALID. */
499 scratch_dword3 |=
500 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
501 }
502 }
503
504 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
505 (user_sgpr * 4), 4);
506 radeon_emit(cs, scratch_dword0);
507 radeon_emit(cs, scratch_dword1);
508 radeon_emit(cs, scratch_dword2);
509 radeon_emit(cs, scratch_dword3);
510 }
511
512 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
513 const amd_kernel_code_t *code_object,
514 const struct pipe_grid_info *info,
515 uint64_t kernel_args_va)
516 {
517 struct si_compute *program = sctx->cs_shader_state.program;
518 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
519
520 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
521 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
522 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
523 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
524 };
525
526 unsigned i, user_sgpr = 0;
527 if (AMD_HSA_BITS_GET(code_object->code_properties,
528 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
529 if (code_object->workitem_private_segment_byte_size > 0) {
530 setup_scratch_rsrc_user_sgprs(sctx, code_object,
531 user_sgpr);
532 }
533 user_sgpr += 4;
534 }
535
536 if (AMD_HSA_BITS_GET(code_object->code_properties,
537 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
538 struct dispatch_packet dispatch;
539 unsigned dispatch_offset;
540 struct r600_resource *dispatch_buf = NULL;
541 uint64_t dispatch_va;
542
543 /* Upload dispatch ptr */
544 memset(&dispatch, 0, sizeof(dispatch));
545
546 dispatch.workgroup_size_x = info->block[0];
547 dispatch.workgroup_size_y = info->block[1];
548 dispatch.workgroup_size_z = info->block[2];
549
550 dispatch.grid_size_x = info->grid[0] * info->block[0];
551 dispatch.grid_size_y = info->grid[1] * info->block[1];
552 dispatch.grid_size_z = info->grid[2] * info->block[2];
553
554 dispatch.private_segment_size = program->private_size;
555 dispatch.group_segment_size = program->local_size;
556
557 dispatch.kernarg_address = kernel_args_va;
558
559 u_upload_data(sctx->b.b.const_uploader, 0, sizeof(dispatch),
560 256, &dispatch, &dispatch_offset,
561 (struct pipe_resource**)&dispatch_buf);
562
563 if (!dispatch_buf) {
564 fprintf(stderr, "Error: Failed to allocate dispatch "
565 "packet.");
566 }
567 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
568 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
569
570 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
571
572 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
573 (user_sgpr * 4), 2);
574 radeon_emit(cs, dispatch_va);
575 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
576 S_008F04_STRIDE(0));
577
578 r600_resource_reference(&dispatch_buf, NULL);
579 user_sgpr += 2;
580 }
581
582 if (AMD_HSA_BITS_GET(code_object->code_properties,
583 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
584 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
585 (user_sgpr * 4), 2);
586 radeon_emit(cs, kernel_args_va);
587 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
588 S_008F04_STRIDE(0));
589 user_sgpr += 2;
590 }
591
592 for (i = 0; i < 3 && user_sgpr < 16; i++) {
593 if (code_object->code_properties & workgroup_count_masks[i]) {
594 radeon_set_sh_reg_seq(cs,
595 R_00B900_COMPUTE_USER_DATA_0 +
596 (user_sgpr * 4), 1);
597 radeon_emit(cs, info->grid[i]);
598 user_sgpr += 1;
599 }
600 }
601 }
602
603 static bool si_upload_compute_input(struct si_context *sctx,
604 const amd_kernel_code_t *code_object,
605 const struct pipe_grid_info *info)
606 {
607 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
608 struct si_compute *program = sctx->cs_shader_state.program;
609 struct r600_resource *input_buffer = NULL;
610 unsigned kernel_args_size;
611 unsigned num_work_size_bytes = program->use_code_object_v2 ? 0 : 36;
612 uint32_t kernel_args_offset = 0;
613 uint32_t *kernel_args;
614 void *kernel_args_ptr;
615 uint64_t kernel_args_va;
616 unsigned i;
617
618 /* The extra num_work_size_bytes are for work group / work item size information */
619 kernel_args_size = program->input_size + num_work_size_bytes;
620
621 u_upload_alloc(sctx->b.b.const_uploader, 0, kernel_args_size,
622 sctx->screen->b.info.tcc_cache_line_size,
623 &kernel_args_offset,
624 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
625
626 if (unlikely(!kernel_args_ptr))
627 return false;
628
629 kernel_args = (uint32_t*)kernel_args_ptr;
630 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
631
632 if (!code_object) {
633 for (i = 0; i < 3; i++) {
634 kernel_args[i] = info->grid[i];
635 kernel_args[i + 3] = info->grid[i] * info->block[i];
636 kernel_args[i + 6] = info->block[i];
637 }
638 }
639
640 memcpy(kernel_args + (num_work_size_bytes / 4), info->input,
641 program->input_size);
642
643
644 for (i = 0; i < (kernel_args_size / 4); i++) {
645 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
646 kernel_args[i]);
647 }
648
649
650 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
651 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
652
653 if (code_object) {
654 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
655 } else {
656 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
657 radeon_emit(cs, kernel_args_va);
658 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
659 S_008F04_STRIDE(0));
660 }
661
662 r600_resource_reference(&input_buffer, NULL);
663
664 return true;
665 }
666
667 static void si_setup_tgsi_grid(struct si_context *sctx,
668 const struct pipe_grid_info *info)
669 {
670 struct si_compute *program = sctx->cs_shader_state.program;
671 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
672 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
673 4 * SI_NUM_RESOURCE_SGPRS;
674 unsigned block_size_reg = grid_size_reg +
675 /* 12 bytes = 3 dwords. */
676 12 * program->uses_grid_size;
677
678 if (info->indirect) {
679 if (program->uses_grid_size) {
680 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
681 uint64_t va = base_va + info->indirect_offset;
682 int i;
683
684 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
685 (struct r600_resource *)info->indirect,
686 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
687
688 for (i = 0; i < 3; ++i) {
689 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
690 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
691 COPY_DATA_DST_SEL(COPY_DATA_REG));
692 radeon_emit(cs, (va + 4 * i));
693 radeon_emit(cs, (va + 4 * i) >> 32);
694 radeon_emit(cs, (grid_size_reg >> 2) + i);
695 radeon_emit(cs, 0);
696 }
697 }
698 } else {
699 if (program->uses_grid_size) {
700 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
701 radeon_emit(cs, info->grid[0]);
702 radeon_emit(cs, info->grid[1]);
703 radeon_emit(cs, info->grid[2]);
704 }
705 if (program->variable_group_size && program->uses_block_size) {
706 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
707 radeon_emit(cs, info->block[0]);
708 radeon_emit(cs, info->block[1]);
709 radeon_emit(cs, info->block[2]);
710 }
711 }
712 }
713
714 static void si_emit_dispatch_packets(struct si_context *sctx,
715 const struct pipe_grid_info *info)
716 {
717 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
718 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
719 unsigned waves_per_threadgroup =
720 DIV_ROUND_UP(info->block[0] * info->block[1] * info->block[2], 64);
721
722 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
723 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0));
724
725 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
726 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
727 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
728 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
729
730 unsigned dispatch_initiator =
731 S_00B800_COMPUTE_SHADER_EN(1) |
732 S_00B800_FORCE_START_AT_000(1) |
733 /* If the KMD allows it (there is a KMD hw register for it),
734 * allow launching waves out-of-order. (same as Vulkan) */
735 S_00B800_ORDER_MODE(sctx->b.chip_class >= CIK);
736
737 if (info->indirect) {
738 uint64_t base_va = r600_resource(info->indirect)->gpu_address;
739
740 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
741 (struct r600_resource *)info->indirect,
742 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
743
744 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
745 PKT3_SHADER_TYPE_S(1));
746 radeon_emit(cs, 1);
747 radeon_emit(cs, base_va);
748 radeon_emit(cs, base_va >> 32);
749
750 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
751 PKT3_SHADER_TYPE_S(1));
752 radeon_emit(cs, info->indirect_offset);
753 radeon_emit(cs, dispatch_initiator);
754 } else {
755 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
756 PKT3_SHADER_TYPE_S(1));
757 radeon_emit(cs, info->grid[0]);
758 radeon_emit(cs, info->grid[1]);
759 radeon_emit(cs, info->grid[2]);
760 radeon_emit(cs, dispatch_initiator);
761 }
762 }
763
764
765 static void si_launch_grid(
766 struct pipe_context *ctx, const struct pipe_grid_info *info)
767 {
768 struct si_context *sctx = (struct si_context*)ctx;
769 struct si_compute *program = sctx->cs_shader_state.program;
770 const amd_kernel_code_t *code_object =
771 si_compute_get_code_object(program, info->pc);
772 int i;
773 /* HW bug workaround when CS threadgroups > 256 threads and async
774 * compute isn't used, i.e. only one compute job can run at a time.
775 * If async compute is possible, the threadgroup size must be limited
776 * to 256 threads on all queues to avoid the bug.
777 * Only SI and certain CIK chips are affected.
778 */
779 bool cs_regalloc_hang =
780 (sctx->b.chip_class == SI ||
781 sctx->b.family == CHIP_BONAIRE ||
782 sctx->b.family == CHIP_KABINI) &&
783 info->block[0] * info->block[1] * info->block[2] > 256;
784
785 if (cs_regalloc_hang)
786 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
787 SI_CONTEXT_CS_PARTIAL_FLUSH;
788
789 if (program->ir_type == PIPE_SHADER_IR_TGSI &&
790 program->shader.compilation_failed)
791 return;
792
793 if (sctx->b.last_num_draw_calls != sctx->b.num_draw_calls) {
794 si_update_fb_dirtiness_after_rendering(sctx);
795 sctx->b.last_num_draw_calls = sctx->b.num_draw_calls;
796 }
797
798 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
799
800 /* Add buffer sizes for memory checking in need_cs_space. */
801 r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
802 /* TODO: add the scratch buffer */
803
804 if (info->indirect) {
805 r600_context_add_resource_size(ctx, info->indirect);
806
807 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
808 if (sctx->b.chip_class <= VI &&
809 r600_resource(info->indirect)->TC_L2_dirty) {
810 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
811 r600_resource(info->indirect)->TC_L2_dirty = false;
812 }
813 }
814
815 si_need_cs_space(sctx);
816
817 if (!sctx->cs_shader_state.initialized)
818 si_initialize_compute(sctx);
819
820 if (sctx->b.flags)
821 si_emit_cache_flush(sctx);
822
823 if (!si_switch_compute_shader(sctx, program, &program->shader,
824 code_object, info->pc))
825 return;
826
827 si_upload_compute_shader_descriptors(sctx);
828 si_emit_compute_shader_pointers(sctx);
829
830 if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
831 sctx->atoms.s.render_cond->emit(&sctx->b,
832 sctx->atoms.s.render_cond);
833 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
834 }
835
836 if ((program->input_size ||
837 program->ir_type == PIPE_SHADER_IR_NATIVE) &&
838 unlikely(!si_upload_compute_input(sctx, code_object, info))) {
839 return;
840 }
841
842 /* Global buffers */
843 for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
844 struct r600_resource *buffer =
845 (struct r600_resource*)program->global_buffers[i];
846 if (!buffer) {
847 continue;
848 }
849 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
850 RADEON_USAGE_READWRITE,
851 RADEON_PRIO_COMPUTE_GLOBAL);
852 }
853
854 if (program->ir_type == PIPE_SHADER_IR_TGSI)
855 si_setup_tgsi_grid(sctx, info);
856
857 si_emit_dispatch_packets(sctx, info);
858
859 if (unlikely(sctx->current_saved_cs)) {
860 si_trace_emit(sctx);
861 si_log_compute_state(sctx, sctx->b.log);
862 }
863
864 sctx->compute_is_busy = true;
865 sctx->b.num_compute_calls++;
866 if (sctx->cs_shader_state.uses_scratch)
867 sctx->b.num_spill_compute_calls++;
868
869 if (cs_regalloc_hang)
870 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
871 }
872
873 void si_destroy_compute(struct si_compute *program)
874 {
875 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
876 util_queue_drop_job(&program->screen->shader_compiler_queue,
877 &program->ready);
878 util_queue_fence_destroy(&program->ready);
879 }
880
881 si_shader_destroy(&program->shader);
882 FREE(program);
883 }
884
885 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
886 struct si_compute *program = (struct si_compute *)state;
887 struct si_context *sctx = (struct si_context*)ctx;
888
889 if (!state)
890 return;
891
892 if (program == sctx->cs_shader_state.program)
893 sctx->cs_shader_state.program = NULL;
894
895 if (program == sctx->cs_shader_state.emitted_program)
896 sctx->cs_shader_state.emitted_program = NULL;
897
898 si_compute_reference(&program, NULL);
899 }
900
901 static void si_set_compute_resources(struct pipe_context * ctx_,
902 unsigned start, unsigned count,
903 struct pipe_surface ** surfaces) { }
904
905 void si_init_compute_functions(struct si_context *sctx)
906 {
907 sctx->b.b.create_compute_state = si_create_compute_state;
908 sctx->b.b.delete_compute_state = si_delete_compute_state;
909 sctx->b.b.bind_compute_state = si_bind_compute_state;
910 /* ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
911 sctx->b.b.set_compute_resources = si_set_compute_resources;
912 sctx->b.b.set_global_binding = si_set_global_binding;
913 sctx->b.b.launch_grid = si_launch_grid;
914 }