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radeonsi/nir: implement pipe_screen::finalize_nir
[mesa.git] / src / gallium / drivers / radeonsi / si_compute.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "nir/tgsi_to_nir.h"
27 #include "tgsi/tgsi_parse.h"
28 #include "util/u_async_debug.h"
29 #include "util/u_memory.h"
30 #include "util/u_upload_mgr.h"
31
32 #include "ac_rtld.h"
33 #include "amd_kernel_code_t.h"
34 #include "si_build_pm4.h"
35 #include "si_compute.h"
36
37 #define COMPUTE_DBG(sscreen, fmt, args...) \
38 do { \
39 if ((sscreen->debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
40 } while (0);
41
42 struct dispatch_packet {
43 uint16_t header;
44 uint16_t setup;
45 uint16_t workgroup_size_x;
46 uint16_t workgroup_size_y;
47 uint16_t workgroup_size_z;
48 uint16_t reserved0;
49 uint32_t grid_size_x;
50 uint32_t grid_size_y;
51 uint32_t grid_size_z;
52 uint32_t private_segment_size;
53 uint32_t group_segment_size;
54 uint64_t kernel_object;
55 uint64_t kernarg_address;
56 uint64_t reserved2;
57 };
58
59 static const amd_kernel_code_t *si_compute_get_code_object(
60 const struct si_compute *program,
61 uint64_t symbol_offset)
62 {
63 const struct si_shader_selector *sel = &program->sel;
64
65 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
66 return NULL;
67
68 struct ac_rtld_binary rtld;
69 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
70 .info = &sel->screen->info,
71 .shader_type = MESA_SHADER_COMPUTE,
72 .wave_size = sel->screen->compute_wave_size,
73 .num_parts = 1,
74 .elf_ptrs = &program->shader.binary.elf_buffer,
75 .elf_sizes = &program->shader.binary.elf_size }))
76 return NULL;
77
78 const amd_kernel_code_t *result = NULL;
79 const char *text;
80 size_t size;
81 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
82 goto out;
83
84 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
85 goto out;
86
87 result = (const amd_kernel_code_t*)(text + symbol_offset);
88
89 out:
90 ac_rtld_close(&rtld);
91 return result;
92 }
93
94 static void code_object_to_config(const amd_kernel_code_t *code_object,
95 struct ac_shader_config *out_config) {
96
97 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
98 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
99 out_config->num_sgprs = code_object->wavefront_sgpr_count;
100 out_config->num_vgprs = code_object->workitem_vgpr_count;
101 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
102 out_config->rsrc1 = rsrc1;
103 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
104 out_config->rsrc2 = rsrc2;
105 out_config->scratch_bytes_per_wave =
106 align(code_object->workitem_private_segment_byte_size * 64, 1024);
107 }
108
109 /* Asynchronous compute shader compilation. */
110 static void si_create_compute_state_async(void *job, int thread_index)
111 {
112 struct si_compute *program = (struct si_compute *)job;
113 struct si_shader_selector *sel = &program->sel;
114 struct si_shader *shader = &program->shader;
115 struct ac_llvm_compiler *compiler;
116 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
117 struct si_screen *sscreen = sel->screen;
118
119 assert(!debug->debug_message || debug->async);
120 assert(thread_index >= 0);
121 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
122 compiler = &sscreen->compiler[thread_index];
123
124 if (program->ir_type == PIPE_SHADER_IR_TGSI) {
125 tgsi_scan_shader(sel->tokens, &sel->info);
126 } else {
127 assert(program->ir_type == PIPE_SHADER_IR_NIR);
128
129 si_nir_scan_shader(sel->nir, &sel->info);
130 }
131
132 /* Store the declared LDS size into tgsi_shader_info for the shader
133 * cache to include it.
134 */
135 sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;
136
137 si_get_active_slot_masks(&sel->info,
138 &sel->active_const_and_shader_buffers,
139 &sel->active_samplers_and_images);
140
141 program->shader.is_monolithic = true;
142 program->reads_variable_block_size =
143 sel->info.uses_block_size &&
144 sel->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
145 program->num_cs_user_data_dwords =
146 sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
147
148 void *ir_binary = si_get_ir_binary(sel, false, false);
149
150 /* Try to load the shader from the shader cache. */
151 simple_mtx_lock(&sscreen->shader_cache_mutex);
152
153 if (ir_binary &&
154 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
155 simple_mtx_unlock(&sscreen->shader_cache_mutex);
156
157 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
158 si_shader_dump(sscreen, shader, debug, stderr, true);
159
160 if (!si_shader_binary_upload(sscreen, shader, 0))
161 program->shader.compilation_failed = true;
162 } else {
163 simple_mtx_unlock(&sscreen->shader_cache_mutex);
164
165 if (!si_shader_create(sscreen, compiler, &program->shader, debug)) {
166 program->shader.compilation_failed = true;
167
168 if (program->ir_type == PIPE_SHADER_IR_TGSI)
169 FREE(sel->tokens);
170 return;
171 }
172
173 bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
174 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
175 (sel->info.uses_grid_size ? 3 : 0) +
176 (program->reads_variable_block_size ? 3 : 0) +
177 program->num_cs_user_data_dwords;
178
179 shader->config.rsrc1 =
180 S_00B848_VGPRS((shader->config.num_vgprs - 1) /
181 (sscreen->compute_wave_size == 32 ? 8 : 4)) |
182 S_00B848_DX10_CLAMP(1) |
183 S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
184 S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) |
185 S_00B848_FLOAT_MODE(shader->config.float_mode);
186
187 if (sscreen->info.chip_class < GFX10) {
188 shader->config.rsrc1 |=
189 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
190 }
191
192 shader->config.rsrc2 =
193 S_00B84C_USER_SGPR(user_sgprs) |
194 S_00B84C_SCRATCH_EN(scratch_enabled) |
195 S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
196 S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
197 S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
198 S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2] ? 2 :
199 sel->info.uses_thread_id[1] ? 1 : 0) |
200 S_00B84C_LDS_SIZE(shader->config.lds_size);
201
202 if (ir_binary) {
203 simple_mtx_lock(&sscreen->shader_cache_mutex);
204 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
205 FREE(ir_binary);
206 simple_mtx_unlock(&sscreen->shader_cache_mutex);
207 }
208 }
209
210 if (program->ir_type == PIPE_SHADER_IR_TGSI)
211 FREE(sel->tokens);
212 }
213
214 static void *si_create_compute_state(
215 struct pipe_context *ctx,
216 const struct pipe_compute_state *cso)
217 {
218 struct si_context *sctx = (struct si_context *)ctx;
219 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
220 struct si_compute *program = CALLOC_STRUCT(si_compute);
221 struct si_shader_selector *sel = &program->sel;
222
223 pipe_reference_init(&sel->reference, 1);
224 sel->type = PIPE_SHADER_COMPUTE;
225 sel->screen = sscreen;
226 program->shader.selector = &program->sel;
227 program->ir_type = cso->ir_type;
228 program->local_size = cso->req_local_mem;
229 program->private_size = cso->req_private_mem;
230 program->input_size = cso->req_input_mem;
231
232 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
233 if (sscreen->options.enable_nir &&
234 cso->ir_type == PIPE_SHADER_IR_TGSI) {
235 program->ir_type = PIPE_SHADER_IR_NIR;
236 sel->nir = tgsi_to_nir(cso->prog, ctx->screen);
237 } else if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
238 sel->tokens = tgsi_dup_tokens(cso->prog);
239 if (!sel->tokens) {
240 FREE(program);
241 return NULL;
242 }
243 } else {
244 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
245 sel->nir = (struct nir_shader *) cso->prog;
246 }
247
248 sel->compiler_ctx_state.debug = sctx->debug;
249 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
250 p_atomic_inc(&sscreen->num_shaders_created);
251
252 si_schedule_initial_compile(sctx, PIPE_SHADER_COMPUTE,
253 &sel->ready,
254 &sel->compiler_ctx_state,
255 program, si_create_compute_state_async);
256 } else {
257 const struct pipe_binary_program_header *header;
258 header = cso->prog;
259
260 program->shader.binary.elf_size = header->num_bytes;
261 program->shader.binary.elf_buffer = malloc(header->num_bytes);
262 if (!program->shader.binary.elf_buffer) {
263 FREE(program);
264 return NULL;
265 }
266 memcpy((void *)program->shader.binary.elf_buffer, header->blob, header->num_bytes);
267
268 const amd_kernel_code_t *code_object =
269 si_compute_get_code_object(program, 0);
270 code_object_to_config(code_object, &program->shader.config);
271
272 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
273 if (!si_shader_binary_upload(sctx->screen, &program->shader, 0)) {
274 fprintf(stderr, "LLVM failed to upload shader\n");
275 free((void *)program->shader.binary.elf_buffer);
276 FREE(program);
277 return NULL;
278 }
279 }
280
281 return program;
282 }
283
284 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
285 {
286 struct si_context *sctx = (struct si_context*)ctx;
287 struct si_compute *program = (struct si_compute*)state;
288 struct si_shader_selector *sel = &program->sel;
289
290 sctx->cs_shader_state.program = program;
291 if (!program)
292 return;
293
294 /* Wait because we need active slot usage masks. */
295 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
296 util_queue_fence_wait(&sel->ready);
297
298 si_set_active_descriptors(sctx,
299 SI_DESCS_FIRST_COMPUTE +
300 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
301 sel->active_const_and_shader_buffers);
302 si_set_active_descriptors(sctx,
303 SI_DESCS_FIRST_COMPUTE +
304 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
305 sel->active_samplers_and_images);
306 }
307
308 static void si_set_global_binding(
309 struct pipe_context *ctx, unsigned first, unsigned n,
310 struct pipe_resource **resources,
311 uint32_t **handles)
312 {
313 unsigned i;
314 struct si_context *sctx = (struct si_context*)ctx;
315 struct si_compute *program = sctx->cs_shader_state.program;
316
317 if (first + n > program->max_global_buffers) {
318 unsigned old_max = program->max_global_buffers;
319 program->max_global_buffers = first + n;
320 program->global_buffers =
321 realloc(program->global_buffers,
322 program->max_global_buffers *
323 sizeof(program->global_buffers[0]));
324 if (!program->global_buffers) {
325 fprintf(stderr, "radeonsi: failed to allocate compute global_buffers\n");
326 return;
327 }
328
329 memset(&program->global_buffers[old_max], 0,
330 (program->max_global_buffers - old_max) *
331 sizeof(program->global_buffers[0]));
332 }
333
334 if (!resources) {
335 for (i = 0; i < n; i++) {
336 pipe_resource_reference(&program->global_buffers[first + i], NULL);
337 }
338 return;
339 }
340
341 for (i = 0; i < n; i++) {
342 uint64_t va;
343 uint32_t offset;
344 pipe_resource_reference(&program->global_buffers[first + i], resources[i]);
345 va = si_resource(resources[i])->gpu_address;
346 offset = util_le32_to_cpu(*handles[i]);
347 va += offset;
348 va = util_cpu_to_le64(va);
349 memcpy(handles[i], &va, sizeof(va));
350 }
351 }
352
353 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
354 {
355 uint64_t bc_va;
356
357 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
358 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
359 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
360 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
361 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
362
363 if (sctx->chip_class >= GFX7) {
364 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
365 radeon_set_sh_reg_seq(cs,
366 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
367 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
368 S_00B858_SH1_CU_EN(0xffff));
369 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
370 S_00B858_SH1_CU_EN(0xffff));
371 }
372
373 if (sctx->chip_class >= GFX10)
374 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
375
376 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
377 * and is now per pipe, so it should be handled in the
378 * kernel if we want to use something other than the default value,
379 * which is now 0x22f.
380 */
381 if (sctx->chip_class <= GFX6) {
382 /* XXX: This should be:
383 * (number of compute units) * 4 * (waves per simd) - 1 */
384
385 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
386 0x190 /* Default value */);
387 }
388
389 /* Set the pointer to border colors. */
390 bc_va = sctx->border_color_buffer->gpu_address;
391
392 if (sctx->chip_class >= GFX7) {
393 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
394 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
395 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
396 } else {
397 if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
398 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR,
399 bc_va >> 8);
400 }
401 }
402 }
403
404 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
405 struct si_shader *shader,
406 struct ac_shader_config *config)
407 {
408 uint64_t scratch_bo_size, scratch_needed;
409 scratch_bo_size = 0;
410 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
411 if (sctx->compute_scratch_buffer)
412 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
413
414 if (scratch_bo_size < scratch_needed) {
415 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
416
417 sctx->compute_scratch_buffer =
418 si_aligned_buffer_create(&sctx->screen->b,
419 SI_RESOURCE_FLAG_UNMAPPABLE,
420 PIPE_USAGE_DEFAULT,
421 scratch_needed,
422 sctx->screen->info.pte_fragment_size);
423
424 if (!sctx->compute_scratch_buffer)
425 return false;
426 }
427
428 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
429 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
430
431 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
432 return false;
433
434 si_resource_reference(&shader->scratch_bo,
435 sctx->compute_scratch_buffer);
436 }
437
438 return true;
439 }
440
441 static bool si_switch_compute_shader(struct si_context *sctx,
442 struct si_compute *program,
443 struct si_shader *shader,
444 const amd_kernel_code_t *code_object,
445 unsigned offset)
446 {
447 struct radeon_cmdbuf *cs = sctx->gfx_cs;
448 struct ac_shader_config inline_config = {0};
449 struct ac_shader_config *config;
450 uint64_t shader_va;
451
452 if (sctx->cs_shader_state.emitted_program == program &&
453 sctx->cs_shader_state.offset == offset)
454 return true;
455
456 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
457 config = &shader->config;
458 } else {
459 unsigned lds_blocks;
460
461 config = &inline_config;
462 code_object_to_config(code_object, config);
463
464 lds_blocks = config->lds_size;
465 /* XXX: We are over allocating LDS. For GFX6, the shader reports
466 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
467 * allocated in the shader and 4 bytes allocated by the state
468 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
469 */
470 if (sctx->chip_class <= GFX6) {
471 lds_blocks += align(program->local_size, 256) >> 8;
472 } else {
473 lds_blocks += align(program->local_size, 512) >> 9;
474 }
475
476 /* TODO: use si_multiwave_lds_size_workaround */
477 assert(lds_blocks <= 0xFF);
478
479 config->rsrc2 &= C_00B84C_LDS_SIZE;
480 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
481 }
482
483 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
484 return false;
485
486 if (shader->scratch_bo) {
487 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
488 "Total Scratch: %u bytes\n", sctx->scratch_waves,
489 config->scratch_bytes_per_wave,
490 config->scratch_bytes_per_wave *
491 sctx->scratch_waves);
492
493 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
494 shader->scratch_bo, RADEON_USAGE_READWRITE,
495 RADEON_PRIO_SCRATCH_BUFFER);
496 }
497
498 /* Prefetch the compute shader to TC L2.
499 *
500 * We should also prefetch graphics shaders if a compute dispatch was
501 * the last command, and the compute shader if a draw call was the last
502 * command. However, that would add more complexity and we're likely
503 * to get a shader state change in that case anyway.
504 */
505 if (sctx->chip_class >= GFX7) {
506 cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
507 0, program->shader.bo->b.b.width0);
508 }
509
510 shader_va = shader->bo->gpu_address + offset;
511 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
512 /* Shader code is placed after the amd_kernel_code_t
513 * struct. */
514 shader_va += sizeof(amd_kernel_code_t);
515 }
516
517 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, shader->bo,
518 RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
519
520 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
521 radeon_emit(cs, shader_va >> 8);
522 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
523
524 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
525 radeon_emit(cs, config->rsrc1);
526 radeon_emit(cs, config->rsrc2);
527
528 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
529 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
530
531 sctx->max_seen_compute_scratch_bytes_per_wave =
532 MAX2(sctx->max_seen_compute_scratch_bytes_per_wave,
533 config->scratch_bytes_per_wave);
534
535 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
536 S_00B860_WAVES(sctx->scratch_waves)
537 | S_00B860_WAVESIZE(sctx->max_seen_compute_scratch_bytes_per_wave >> 10));
538
539 sctx->cs_shader_state.emitted_program = program;
540 sctx->cs_shader_state.offset = offset;
541 sctx->cs_shader_state.uses_scratch =
542 config->scratch_bytes_per_wave != 0;
543
544 return true;
545 }
546
547 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
548 const amd_kernel_code_t *code_object,
549 unsigned user_sgpr)
550 {
551 struct radeon_cmdbuf *cs = sctx->gfx_cs;
552 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
553
554 unsigned max_private_element_size = AMD_HSA_BITS_GET(
555 code_object->code_properties,
556 AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
557
558 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
559 uint32_t scratch_dword1 =
560 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
561 S_008F04_SWIZZLE_ENABLE(1);
562
563 /* Disable address clamping */
564 uint32_t scratch_dword2 = 0xffffffff;
565 uint32_t scratch_dword3 =
566 S_008F0C_INDEX_STRIDE(3) |
567 S_008F0C_ADD_TID_ENABLE(1);
568
569 if (sctx->chip_class >= GFX9) {
570 assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
571 } else {
572 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
573
574 if (sctx->chip_class < GFX8) {
575 /* BUF_DATA_FORMAT is ignored, but it cannot be
576 * BUF_DATA_FORMAT_INVALID. */
577 scratch_dword3 |=
578 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
579 }
580 }
581
582 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
583 (user_sgpr * 4), 4);
584 radeon_emit(cs, scratch_dword0);
585 radeon_emit(cs, scratch_dword1);
586 radeon_emit(cs, scratch_dword2);
587 radeon_emit(cs, scratch_dword3);
588 }
589
590 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
591 const amd_kernel_code_t *code_object,
592 const struct pipe_grid_info *info,
593 uint64_t kernel_args_va)
594 {
595 struct si_compute *program = sctx->cs_shader_state.program;
596 struct radeon_cmdbuf *cs = sctx->gfx_cs;
597
598 static const enum amd_code_property_mask_t workgroup_count_masks [] = {
599 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
600 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
601 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z
602 };
603
604 unsigned i, user_sgpr = 0;
605 if (AMD_HSA_BITS_GET(code_object->code_properties,
606 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
607 if (code_object->workitem_private_segment_byte_size > 0) {
608 setup_scratch_rsrc_user_sgprs(sctx, code_object,
609 user_sgpr);
610 }
611 user_sgpr += 4;
612 }
613
614 if (AMD_HSA_BITS_GET(code_object->code_properties,
615 AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
616 struct dispatch_packet dispatch;
617 unsigned dispatch_offset;
618 struct si_resource *dispatch_buf = NULL;
619 uint64_t dispatch_va;
620
621 /* Upload dispatch ptr */
622 memset(&dispatch, 0, sizeof(dispatch));
623
624 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
625 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
626 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
627
628 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
629 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
630 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
631
632 dispatch.private_segment_size = util_cpu_to_le32(program->private_size);
633 dispatch.group_segment_size = util_cpu_to_le32(program->local_size);
634
635 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
636
637 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch),
638 256, &dispatch, &dispatch_offset,
639 (struct pipe_resource**)&dispatch_buf);
640
641 if (!dispatch_buf) {
642 fprintf(stderr, "Error: Failed to allocate dispatch "
643 "packet.");
644 }
645 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, dispatch_buf,
646 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
647
648 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
649
650 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
651 (user_sgpr * 4), 2);
652 radeon_emit(cs, dispatch_va);
653 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) |
654 S_008F04_STRIDE(0));
655
656 si_resource_reference(&dispatch_buf, NULL);
657 user_sgpr += 2;
658 }
659
660 if (AMD_HSA_BITS_GET(code_object->code_properties,
661 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
662 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
663 (user_sgpr * 4), 2);
664 radeon_emit(cs, kernel_args_va);
665 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) |
666 S_008F04_STRIDE(0));
667 user_sgpr += 2;
668 }
669
670 for (i = 0; i < 3 && user_sgpr < 16; i++) {
671 if (code_object->code_properties & workgroup_count_masks[i]) {
672 radeon_set_sh_reg_seq(cs,
673 R_00B900_COMPUTE_USER_DATA_0 +
674 (user_sgpr * 4), 1);
675 radeon_emit(cs, info->grid[i]);
676 user_sgpr += 1;
677 }
678 }
679 }
680
681 static bool si_upload_compute_input(struct si_context *sctx,
682 const amd_kernel_code_t *code_object,
683 const struct pipe_grid_info *info)
684 {
685 struct si_compute *program = sctx->cs_shader_state.program;
686 struct si_resource *input_buffer = NULL;
687 uint32_t kernel_args_offset = 0;
688 uint32_t *kernel_args;
689 void *kernel_args_ptr;
690 uint64_t kernel_args_va;
691
692 u_upload_alloc(sctx->b.const_uploader, 0, program->input_size,
693 sctx->screen->info.tcc_cache_line_size,
694 &kernel_args_offset,
695 (struct pipe_resource**)&input_buffer, &kernel_args_ptr);
696
697 if (unlikely(!kernel_args_ptr))
698 return false;
699
700 kernel_args = (uint32_t*)kernel_args_ptr;
701 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
702
703 memcpy(kernel_args, info->input, program->input_size);
704
705 for (unsigned i = 0; i < program->input_size / 4; i++) {
706 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
707 kernel_args[i]);
708 }
709
710 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, input_buffer,
711 RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER);
712
713 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
714 si_resource_reference(&input_buffer, NULL);
715 return true;
716 }
717
718 static void si_setup_tgsi_user_data(struct si_context *sctx,
719 const struct pipe_grid_info *info)
720 {
721 struct si_compute *program = sctx->cs_shader_state.program;
722 struct si_shader_selector *sel = &program->sel;
723 struct radeon_cmdbuf *cs = sctx->gfx_cs;
724 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 +
725 4 * SI_NUM_RESOURCE_SGPRS;
726 unsigned block_size_reg = grid_size_reg +
727 /* 12 bytes = 3 dwords. */
728 12 * sel->info.uses_grid_size;
729 unsigned cs_user_data_reg = block_size_reg +
730 12 * program->reads_variable_block_size;
731
732 if (info->indirect) {
733 if (sel->info.uses_grid_size) {
734 for (unsigned i = 0; i < 3; ++i) {
735 si_cp_copy_data(sctx, sctx->gfx_cs,
736 COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
737 COPY_DATA_SRC_MEM, si_resource(info->indirect),
738 info->indirect_offset + 4 * i);
739 }
740 }
741 } else {
742 if (sel->info.uses_grid_size) {
743 radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
744 radeon_emit(cs, info->grid[0]);
745 radeon_emit(cs, info->grid[1]);
746 radeon_emit(cs, info->grid[2]);
747 }
748 if (program->reads_variable_block_size) {
749 radeon_set_sh_reg_seq(cs, block_size_reg, 3);
750 radeon_emit(cs, info->block[0]);
751 radeon_emit(cs, info->block[1]);
752 radeon_emit(cs, info->block[2]);
753 }
754 }
755
756 if (program->num_cs_user_data_dwords) {
757 radeon_set_sh_reg_seq(cs, cs_user_data_reg, program->num_cs_user_data_dwords);
758 radeon_emit_array(cs, sctx->cs_user_data, program->num_cs_user_data_dwords);
759 }
760 }
761
762 static void si_emit_dispatch_packets(struct si_context *sctx,
763 const struct pipe_grid_info *info)
764 {
765 struct si_screen *sscreen = sctx->screen;
766 struct radeon_cmdbuf *cs = sctx->gfx_cs;
767 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
768 unsigned threads_per_threadgroup =
769 info->block[0] * info->block[1] * info->block[2];
770 unsigned waves_per_threadgroup =
771 DIV_ROUND_UP(threads_per_threadgroup, sscreen->compute_wave_size);
772 unsigned threadgroups_per_cu = 1;
773
774 if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1)
775 threadgroups_per_cu = 2;
776
777 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
778 ac_get_compute_resource_limits(&sscreen->info,
779 waves_per_threadgroup,
780 sctx->cs_max_waves_per_sh,
781 threadgroups_per_cu));
782
783 unsigned dispatch_initiator =
784 S_00B800_COMPUTE_SHADER_EN(1) |
785 S_00B800_FORCE_START_AT_000(1) |
786 /* If the KMD allows it (there is a KMD hw register for it),
787 * allow launching waves out-of-order. (same as Vulkan) */
788 S_00B800_ORDER_MODE(sctx->chip_class >= GFX7) |
789 S_00B800_CS_W32_EN(sscreen->compute_wave_size == 32);
790
791 const uint *last_block = info->last_block;
792 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
793
794 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
795
796 if (partial_block_en) {
797 unsigned partial[3];
798
799 /* If no partial_block, these should be an entire block size, not 0. */
800 partial[0] = last_block[0] ? last_block[0] : info->block[0];
801 partial[1] = last_block[1] ? last_block[1] : info->block[1];
802 partial[2] = last_block[2] ? last_block[2] : info->block[2];
803
804 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
805 S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
806 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
807 S_00B820_NUM_THREAD_PARTIAL(partial[1]));
808 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
809 S_00B824_NUM_THREAD_PARTIAL(partial[2]));
810
811 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
812 } else {
813 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
814 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
815 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
816 }
817
818 if (info->indirect) {
819 uint64_t base_va = si_resource(info->indirect)->gpu_address;
820
821 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
822 si_resource(info->indirect),
823 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
824
825 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
826 PKT3_SHADER_TYPE_S(1));
827 radeon_emit(cs, 1);
828 radeon_emit(cs, base_va);
829 radeon_emit(cs, base_va >> 32);
830
831 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, render_cond_bit) |
832 PKT3_SHADER_TYPE_S(1));
833 radeon_emit(cs, info->indirect_offset);
834 radeon_emit(cs, dispatch_initiator);
835 } else {
836 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, render_cond_bit) |
837 PKT3_SHADER_TYPE_S(1));
838 radeon_emit(cs, info->grid[0]);
839 radeon_emit(cs, info->grid[1]);
840 radeon_emit(cs, info->grid[2]);
841 radeon_emit(cs, dispatch_initiator);
842 }
843 }
844
845
846 static void si_launch_grid(
847 struct pipe_context *ctx, const struct pipe_grid_info *info)
848 {
849 struct si_context *sctx = (struct si_context*)ctx;
850 struct si_compute *program = sctx->cs_shader_state.program;
851 const amd_kernel_code_t *code_object =
852 si_compute_get_code_object(program, info->pc);
853 int i;
854 /* HW bug workaround when CS threadgroups > 256 threads and async
855 * compute isn't used, i.e. only one compute job can run at a time.
856 * If async compute is possible, the threadgroup size must be limited
857 * to 256 threads on all queues to avoid the bug.
858 * Only GFX6 and certain GFX7 chips are affected.
859 */
860 bool cs_regalloc_hang =
861 (sctx->chip_class == GFX6 ||
862 sctx->family == CHIP_BONAIRE ||
863 sctx->family == CHIP_KABINI) &&
864 info->block[0] * info->block[1] * info->block[2] > 256;
865
866 if (cs_regalloc_hang)
867 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
868 SI_CONTEXT_CS_PARTIAL_FLUSH;
869
870 if (program->ir_type != PIPE_SHADER_IR_NATIVE &&
871 program->shader.compilation_failed)
872 return;
873
874 if (sctx->has_graphics) {
875 if (sctx->last_num_draw_calls != sctx->num_draw_calls) {
876 si_update_fb_dirtiness_after_rendering(sctx);
877 sctx->last_num_draw_calls = sctx->num_draw_calls;
878 }
879
880 si_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
881 }
882
883 /* Add buffer sizes for memory checking in need_cs_space. */
884 si_context_add_resource_size(sctx, &program->shader.bo->b.b);
885 /* TODO: add the scratch buffer */
886
887 if (info->indirect) {
888 si_context_add_resource_size(sctx, info->indirect);
889
890 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
891 if (sctx->chip_class <= GFX8 &&
892 si_resource(info->indirect)->TC_L2_dirty) {
893 sctx->flags |= SI_CONTEXT_WB_L2;
894 si_resource(info->indirect)->TC_L2_dirty = false;
895 }
896 }
897
898 si_need_gfx_cs_space(sctx);
899
900 if (sctx->bo_list_add_all_compute_resources)
901 si_compute_resources_add_all_to_bo_list(sctx);
902
903 if (!sctx->cs_shader_state.initialized) {
904 si_emit_initial_compute_regs(sctx, sctx->gfx_cs);
905
906 sctx->cs_shader_state.emitted_program = NULL;
907 sctx->cs_shader_state.initialized = true;
908 }
909
910 if (sctx->flags)
911 sctx->emit_cache_flush(sctx);
912
913 if (!si_switch_compute_shader(sctx, program, &program->shader,
914 code_object, info->pc))
915 return;
916
917 si_upload_compute_shader_descriptors(sctx);
918 si_emit_compute_shader_pointers(sctx);
919
920 if (sctx->has_graphics &&
921 si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
922 sctx->atoms.s.render_cond.emit(sctx);
923 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
924 }
925
926 if (program->ir_type == PIPE_SHADER_IR_NATIVE &&
927 unlikely(!si_upload_compute_input(sctx, code_object, info)))
928 return;
929
930 /* Global buffers */
931 for (i = 0; i < program->max_global_buffers; i++) {
932 struct si_resource *buffer =
933 si_resource(program->global_buffers[i]);
934 if (!buffer) {
935 continue;
936 }
937 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, buffer,
938 RADEON_USAGE_READWRITE,
939 RADEON_PRIO_COMPUTE_GLOBAL);
940 }
941
942 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
943 si_setup_tgsi_user_data(sctx, info);
944
945 si_emit_dispatch_packets(sctx, info);
946
947 if (unlikely(sctx->current_saved_cs)) {
948 si_trace_emit(sctx);
949 si_log_compute_state(sctx, sctx->log);
950 }
951
952 sctx->compute_is_busy = true;
953 sctx->num_compute_calls++;
954 if (sctx->cs_shader_state.uses_scratch)
955 sctx->num_spill_compute_calls++;
956
957 if (cs_regalloc_hang)
958 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
959 }
960
961 void si_destroy_compute(struct si_compute *program)
962 {
963 struct si_shader_selector *sel = &program->sel;
964
965 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
966 util_queue_drop_job(&sel->screen->shader_compiler_queue,
967 &sel->ready);
968 util_queue_fence_destroy(&sel->ready);
969 }
970
971 for (unsigned i = 0; i < program->max_global_buffers; i++)
972 pipe_resource_reference(&program->global_buffers[i], NULL);
973 FREE(program->global_buffers);
974
975 si_shader_destroy(&program->shader);
976 ralloc_free(program->sel.nir);
977 FREE(program);
978 }
979
980 static void si_delete_compute_state(struct pipe_context *ctx, void* state){
981 struct si_compute *program = (struct si_compute *)state;
982 struct si_context *sctx = (struct si_context*)ctx;
983
984 if (!state)
985 return;
986
987 if (program == sctx->cs_shader_state.program)
988 sctx->cs_shader_state.program = NULL;
989
990 if (program == sctx->cs_shader_state.emitted_program)
991 sctx->cs_shader_state.emitted_program = NULL;
992
993 si_compute_reference(&program, NULL);
994 }
995
996 static void si_set_compute_resources(struct pipe_context * ctx_,
997 unsigned start, unsigned count,
998 struct pipe_surface ** surfaces) { }
999
1000 void si_init_compute_functions(struct si_context *sctx)
1001 {
1002 sctx->b.create_compute_state = si_create_compute_state;
1003 sctx->b.delete_compute_state = si_delete_compute_state;
1004 sctx->b.bind_compute_state = si_bind_compute_state;
1005 sctx->b.set_compute_resources = si_set_compute_resources;
1006 sctx->b.set_global_binding = si_set_global_binding;
1007 sctx->b.launch_grid = si_launch_grid;
1008 }