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radeonsi: use ctx->ac. for types and integer constants
[mesa.git] / src / gallium / drivers / radeonsi / si_compute_prim_discard.c
1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include "si_pipe.h"
27 #include "si_shader_internal.h"
28 #include "sid.h"
29 #include "si_build_pm4.h"
30 #include "ac_llvm_cull.h"
31
32 #include "util/u_prim.h"
33 #include "util/u_suballoc.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 /* Based on:
38 * https://frostbite-wp-prd.s3.amazonaws.com/wp-content/uploads/2016/03/29204330/GDC_2016_Compute.pdf
39 */
40
41 /* This file implements primitive culling using asynchronous compute.
42 * It's written to be GL conformant.
43 *
44 * It takes a monolithic VS in LLVM IR returning gl_Position and invokes it
45 * in a compute shader. The shader processes 1 primitive/thread by invoking
46 * the VS for each vertex to get the positions, decomposes strips and fans
47 * into triangles (if needed), eliminates primitive restart (if needed),
48 * does (W<0) culling, face culling, view XY culling, zero-area and
49 * small-primitive culling, and generates a new index buffer that doesn't
50 * contain culled primitives.
51 *
52 * The index buffer is generated using the Ordered Count feature of GDS,
53 * which is an atomic counter that is incremented in the wavefront launch
54 * order, so that the original primitive order is preserved.
55 *
56 * Another GDS ordered counter is used to eliminate primitive restart indices.
57 * If a restart index lands on an even thread ID, the compute shader has to flip
58 * the primitive orientation of the whole following triangle strip. The primitive
59 * orientation has to be correct after strip and fan decomposition for two-sided
60 * shading to behave correctly. The decomposition also needs to be aware of
61 * which vertex is the provoking vertex for flat shading to behave correctly.
62 *
63 * IB = a GPU command buffer
64 *
65 * Both the compute and gfx IBs run in parallel sort of like CE and DE.
66 * The gfx IB has a CP barrier (REWIND packet) before a draw packet. REWIND
67 * doesn't continue if its word isn't 0x80000000. Once compute shaders are
68 * finished culling, the last wave will write the final primitive count from
69 * GDS directly into the count word of the draw packet in the gfx IB, and
70 * a CS_DONE event will signal the REWIND packet to continue. It's really
71 * a direct draw with command buffer patching from the compute queue.
72 *
73 * The compute IB doesn't have to start when its corresponding gfx IB starts,
74 * but can start sooner. The compute IB is signaled to start after the last
75 * execution barrier in the *previous* gfx IB. This is handled as follows.
76 * The kernel GPU scheduler starts the compute IB after the previous gfx IB has
77 * started. The compute IB then waits (WAIT_REG_MEM) for a mid-IB fence that
78 * represents the barrier in the previous gfx IB.
79 *
80 * Features:
81 * - Triangle strips and fans are decomposed into an indexed triangle list.
82 * The decomposition differs based on the provoking vertex state.
83 * - Instanced draws are converted into non-instanced draws for 16-bit indices.
84 * (InstanceID is stored in the high bits of VertexID and unpacked by VS)
85 * - Primitive restart is fully supported with triangle strips, including
86 * correct primitive orientation across multiple waves. (restart indices
87 * reset primitive orientation)
88 * - W<0 culling (W<0 is behind the viewer, sort of like near Z culling).
89 * - Back face culling, incl. culling zero-area / degenerate primitives.
90 * - View XY culling.
91 * - View Z culling (disabled due to limited impact with perspective projection).
92 * - Small primitive culling for all MSAA modes and all quant modes.
93 *
94 * The following are not implemented:
95 * - ClipVertex/ClipDistance/CullDistance-based culling.
96 * - Scissor culling.
97 * - HiZ culling.
98 *
99 * Limitations (and unimplemented features that may be possible to implement):
100 * - Only triangles, triangle strips, and triangle fans are supported.
101 * - Primitive restart is only supported with triangle strips.
102 * - Instancing and primitive restart can't be used together.
103 * - Instancing is only supported with 16-bit indices and instance count <= 2^16.
104 * - The instance divisor buffer is unavailable, so all divisors must be
105 * either 0 or 1.
106 * - Multidraws where the vertex shader reads gl_DrawID are unsupported.
107 * - No support for tessellation and geometry shaders.
108 * (patch elimination where tess factors are 0 would be possible to implement)
109 * - The vertex shader must not contain memory stores.
110 * - All VS resources must not have a write usage in the command buffer.
111 * (TODO: all shader buffers currently set the write usage)
112 * - Bindless textures and images must not occur in the vertex shader.
113 *
114 * User data SGPR layout:
115 * INDEX_BUFFERS: pointer to constants
116 * 0..3: input index buffer - typed buffer view
117 * 4..7: output index buffer - typed buffer view
118 * 8..11: viewport state - scale.xy, translate.xy
119 * VERTEX_COUNTER: counter address or first primitive ID
120 * - If unordered memory counter: address of "count" in the draw packet
121 * and is incremented atomically by the shader.
122 * - If unordered GDS counter: address of "count" in GDS starting from 0,
123 * must be initialized to 0 before the dispatch.
124 * - If ordered GDS counter: the primitive ID that should reset the vertex
125 * counter to 0 in GDS
126 * LAST_WAVE_PRIM_ID: the primitive ID that should write the final vertex
127 * count to memory if using GDS ordered append
128 * VERTEX_COUNT_ADDR: where the last wave should write the vertex count if
129 * using GDS ordered append
130 * VS.VERTEX_BUFFERS: same value as VS
131 * VS.CONST_AND_SHADER_BUFFERS: same value as VS
132 * VS.SAMPLERS_AND_IMAGES: same value as VS
133 * VS.BASE_VERTEX: same value as VS
134 * VS.START_INSTANCE: same value as VS
135 * NUM_PRIMS_UDIV_MULTIPLIER: For fast 31-bit division by the number of primitives
136 * per instance for instancing.
137 * NUM_PRIMS_UDIV_TERMS:
138 * - Bits [0:4]: "post_shift" for fast 31-bit division for instancing.
139 * - Bits [5:31]: The number of primitives per instance for computing the remainder.
140 * PRIMITIVE_RESTART_INDEX
141 * SMALL_PRIM_CULLING_PRECISION: Scale the primitive bounding box by this number.
142 *
143 *
144 * The code contains 3 codepaths:
145 * - Unordered memory counter (for debugging, random primitive order, no primitive restart)
146 * - Unordered GDS counter (for debugging, random primitive order, no primitive restart)
147 * - Ordered GDS counter (it preserves the primitive order)
148 *
149 * How to test primitive restart (the most complicated part because it needs
150 * to get the primitive orientation right):
151 * Set THREADGROUP_SIZE to 2 to exercise both intra-wave and inter-wave
152 * primitive orientation flips with small draw calls, which is what most tests use.
153 * You can also enable draw call splitting into draw calls with just 2 primitives.
154 */
155
156 /* At least 256 is needed for the fastest wave launch rate from compute queues
157 * due to hw constraints. Nothing in the code needs more than 1 wave/threadgroup. */
158 #define THREADGROUP_SIZE 256 /* high numbers limit available VGPRs */
159 #define THREADGROUPS_PER_CU 1 /* TGs to launch on 1 CU before going onto the next, max 8 */
160 #define MAX_WAVES_PER_SH 0 /* no limit */
161 #define INDEX_STORES_USE_SLC 1 /* don't cache indices if L2 is full */
162 /* Don't cull Z. We already do (W < 0) culling for primitives behind the viewer. */
163 #define CULL_Z 0
164 /* 0 = unordered memory counter, 1 = unordered GDS counter, 2 = ordered GDS counter */
165 #define VERTEX_COUNTER_GDS_MODE 2
166 #define GDS_SIZE_UNORDERED (4 * 1024) /* only for the unordered GDS counter */
167
168 /* Grouping compute dispatches for small draw calls: How many primitives from multiple
169 * draw calls to process by compute before signaling the gfx IB. This reduces the number
170 * of EOP events + REWIND packets, because they decrease performance. */
171 #define PRIMS_PER_BATCH (512 * 1024)
172 /* Draw call splitting at the packet level. This allows signaling the gfx IB
173 * for big draw calls sooner, but doesn't allow context flushes between packets.
174 * Primitive restart is supported. Only implemented for ordered append. */
175 #define SPLIT_PRIMS_PACKET_LEVEL_VALUE PRIMS_PER_BATCH
176 /* If there is not enough ring buffer space for the current IB, split draw calls into
177 * this number of primitives, so that we can flush the context and get free ring space. */
178 #define SPLIT_PRIMS_DRAW_LEVEL PRIMS_PER_BATCH
179
180 /* Derived values. */
181 #define WAVES_PER_TG DIV_ROUND_UP(THREADGROUP_SIZE, 64)
182 #define SPLIT_PRIMS_PACKET_LEVEL (VERTEX_COUNTER_GDS_MODE == 2 ? \
183 SPLIT_PRIMS_PACKET_LEVEL_VALUE : \
184 UINT_MAX & ~(THREADGROUP_SIZE - 1))
185
186 #define REWIND_SIGNAL_BIT 0x80000000
187 /* For emulating the rewind packet on CI. */
188 #define FORCE_REWIND_EMULATION 0
189
190 void si_initialize_prim_discard_tunables(struct si_screen *sscreen,
191 bool is_aux_context,
192 unsigned *prim_discard_vertex_count_threshold,
193 unsigned *index_ring_size_per_ib)
194 {
195 *prim_discard_vertex_count_threshold = UINT_MAX; /* disable */
196
197 if (sscreen->info.chip_class == GFX6 || /* SI support is not implemented */
198 !sscreen->info.has_gds_ordered_append ||
199 sscreen->debug_flags & DBG(NO_PD) ||
200 is_aux_context)
201 return;
202
203 /* TODO: enable this after the GDS kernel memory management is fixed */
204 bool enable_on_pro_graphics_by_default = false;
205
206 if (sscreen->debug_flags & DBG(ALWAYS_PD) ||
207 sscreen->debug_flags & DBG(PD) ||
208 (enable_on_pro_graphics_by_default &&
209 sscreen->info.is_pro_graphics &&
210 (sscreen->info.family == CHIP_BONAIRE ||
211 sscreen->info.family == CHIP_HAWAII ||
212 sscreen->info.family == CHIP_TONGA ||
213 sscreen->info.family == CHIP_FIJI ||
214 sscreen->info.family == CHIP_POLARIS10 ||
215 sscreen->info.family == CHIP_POLARIS11 ||
216 sscreen->info.family == CHIP_VEGA10 ||
217 sscreen->info.family == CHIP_VEGA20))) {
218 *prim_discard_vertex_count_threshold = 6000 * 3; /* 6K triangles */
219
220 if (sscreen->debug_flags & DBG(ALWAYS_PD))
221 *prim_discard_vertex_count_threshold = 0; /* always enable */
222
223 const uint32_t MB = 1024 * 1024;
224 const uint64_t GB = 1024 * 1024 * 1024;
225
226 /* The total size is double this per context.
227 * Greater numbers allow bigger gfx IBs.
228 */
229 if (sscreen->info.vram_size <= 2 * GB)
230 *index_ring_size_per_ib = 64 * MB;
231 else if (sscreen->info.vram_size <= 4 * GB)
232 *index_ring_size_per_ib = 128 * MB;
233 else
234 *index_ring_size_per_ib = 256 * MB;
235 }
236 }
237
238 /* Opcode can be "add" or "swap". */
239 static LLVMValueRef
240 si_build_ds_ordered_op(struct si_shader_context *ctx, const char *opcode,
241 LLVMValueRef m0, LLVMValueRef value, unsigned ordered_count_index,
242 bool release, bool done)
243 {
244 LLVMValueRef args[] = {
245 LLVMBuildIntToPtr(ctx->ac.builder, m0,
246 LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS), ""),
247 value,
248 LLVMConstInt(ctx->ac.i32, LLVMAtomicOrderingMonotonic, 0), /* ordering */
249 ctx->ac.i32_0, /* scope */
250 ctx->ac.i1false, /* volatile */
251 LLVMConstInt(ctx->ac.i32, ordered_count_index, 0),
252 LLVMConstInt(ctx->ac.i1, release, 0),
253 LLVMConstInt(ctx->ac.i1, done, 0),
254 };
255
256 char intrinsic[64];
257 snprintf(intrinsic, sizeof(intrinsic), "llvm.amdgcn.ds.ordered.%s", opcode);
258 return ac_build_intrinsic(&ctx->ac, intrinsic, ctx->ac.i32, args, ARRAY_SIZE(args), 0);
259 }
260
261 static LLVMValueRef si_expand_32bit_pointer(struct si_shader_context *ctx, LLVMValueRef ptr)
262 {
263 uint64_t hi = (uint64_t)ctx->screen->info.address32_hi << 32;
264 ptr = LLVMBuildZExt(ctx->ac.builder, ptr, ctx->ac.i64, "");
265 ptr = LLVMBuildOr(ctx->ac.builder, ptr, LLVMConstInt(ctx->ac.i64, hi, 0), "");
266 return LLVMBuildIntToPtr(ctx->ac.builder, ptr,
267 LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GLOBAL), "");
268 }
269
270 struct si_thread0_section {
271 struct si_shader_context *ctx;
272 LLVMValueRef vgpr_result; /* a VGPR for the value on thread 0. */
273 LLVMValueRef saved_exec;
274 };
275
276 /* Enter a section that only executes on thread 0. */
277 static void si_enter_thread0_section(struct si_shader_context *ctx,
278 struct si_thread0_section *section,
279 LLVMValueRef thread_id)
280 {
281 section->ctx = ctx;
282 section->vgpr_result = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "result0");
283
284 /* This IF has 4 instructions:
285 * v_and_b32_e32 v, 63, v ; get the thread ID
286 * v_cmp_eq_u32_e32 vcc, 0, v ; thread ID == 0
287 * s_and_saveexec_b64 s, vcc
288 * s_cbranch_execz BB0_4
289 *
290 * It could just be s_and_saveexec_b64 s, 1.
291 */
292 ac_build_ifcc(&ctx->ac,
293 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, thread_id,
294 ctx->ac.i32_0, ""), 12601);
295 }
296
297 /* Exit a section that only executes on thread 0 and broadcast the result
298 * to all threads. */
299 static void si_exit_thread0_section(struct si_thread0_section *section,
300 LLVMValueRef *result)
301 {
302 struct si_shader_context *ctx = section->ctx;
303
304 LLVMBuildStore(ctx->ac.builder, *result, section->vgpr_result);
305
306 ac_build_endif(&ctx->ac, 12601);
307
308 /* Broadcast the result from thread 0 to all threads. */
309 *result = ac_build_readlane(&ctx->ac,
310 LLVMBuildLoad(ctx->ac.builder, section->vgpr_result, ""), NULL);
311 }
312
313 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx)
314 {
315 struct si_shader_key *key = &ctx->shader->key;
316 LLVMBuilderRef builder = ctx->ac.builder;
317 LLVMValueRef vs = ctx->main_fn;
318
319 /* Always inline the VS function. */
320 ac_add_function_attr(ctx->ac.context, vs, -1, AC_FUNC_ATTR_ALWAYSINLINE);
321 LLVMSetLinkage(vs, LLVMPrivateLinkage);
322
323 enum ac_arg_type const_desc_type;
324 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
325 ctx->shader->selector->info.shader_buffers_declared == 0)
326 const_desc_type = AC_ARG_CONST_FLOAT_PTR;
327 else
328 const_desc_type = AC_ARG_CONST_DESC_PTR;
329
330 memset(&ctx->args, 0, sizeof(ctx->args));
331
332 struct ac_arg param_index_buffers_and_constants, param_vertex_counter;
333 struct ac_arg param_vb_desc, param_const_desc;
334 struct ac_arg param_base_vertex, param_start_instance;
335 struct ac_arg param_block_id, param_local_id, param_ordered_wave_id;
336 struct ac_arg param_restart_index, param_smallprim_precision;
337 struct ac_arg param_num_prims_udiv_multiplier, param_num_prims_udiv_terms;
338 struct ac_arg param_sampler_desc, param_last_wave_prim_id, param_vertex_count_addr;
339
340 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR,
341 &param_index_buffers_and_constants);
342 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &param_vertex_counter);
343 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &param_last_wave_prim_id);
344 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &param_vertex_count_addr);
345 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR,
346 &param_vb_desc);
347 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, const_desc_type,
348 &param_const_desc);
349 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_IMAGE_PTR,
350 &param_sampler_desc);
351 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &param_base_vertex);
352 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &param_start_instance);
353 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &param_num_prims_udiv_multiplier);
354 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &param_num_prims_udiv_terms);
355 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &param_restart_index);
356 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_FLOAT, &param_smallprim_precision);
357
358 /* Block ID and thread ID inputs. */
359 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &param_block_id);
360 if (VERTEX_COUNTER_GDS_MODE == 2)
361 ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &param_ordered_wave_id);
362 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &param_local_id);
363
364 /* Create the compute shader function. */
365 unsigned old_type = ctx->type;
366 ctx->type = PIPE_SHADER_COMPUTE;
367 si_llvm_create_func(ctx, "prim_discard_cs", NULL, 0, THREADGROUP_SIZE);
368 ctx->type = old_type;
369
370 if (VERTEX_COUNTER_GDS_MODE == 1) {
371 ac_llvm_add_target_dep_function_attr(ctx->main_fn, "amdgpu-gds-size",
372 GDS_SIZE_UNORDERED);
373 }
374
375 /* Assemble parameters for VS. */
376 LLVMValueRef vs_params[16];
377 unsigned num_vs_params = 0;
378 unsigned param_vertex_id, param_instance_id;
379
380 vs_params[num_vs_params++] = LLVMGetUndef(LLVMTypeOf(LLVMGetParam(vs, 0))); /* RW_BUFFERS */
381 vs_params[num_vs_params++] = LLVMGetUndef(LLVMTypeOf(LLVMGetParam(vs, 1))); /* BINDLESS */
382 vs_params[num_vs_params++] = ac_get_arg(&ctx->ac, param_const_desc);
383 vs_params[num_vs_params++] = ac_get_arg(&ctx->ac, param_sampler_desc);
384 vs_params[num_vs_params++] = LLVMConstInt(ctx->ac.i32,
385 S_VS_STATE_INDEXED(key->opt.cs_indexed), 0);
386 vs_params[num_vs_params++] = ac_get_arg(&ctx->ac, param_base_vertex);
387 vs_params[num_vs_params++] = ac_get_arg(&ctx->ac, param_start_instance);
388 vs_params[num_vs_params++] = ctx->ac.i32_0; /* DrawID */
389 vs_params[num_vs_params++] = ac_get_arg(&ctx->ac, param_vb_desc);
390
391 vs_params[(param_vertex_id = num_vs_params++)] = NULL; /* VertexID */
392 vs_params[(param_instance_id = num_vs_params++)] = NULL; /* InstanceID */
393 vs_params[num_vs_params++] = ctx->ac.i32_0; /* unused (PrimID) */
394 vs_params[num_vs_params++] = ctx->ac.i32_0; /* unused */
395
396 assert(num_vs_params <= ARRAY_SIZE(vs_params));
397 assert(num_vs_params == LLVMCountParamTypes(LLVMGetElementType(LLVMTypeOf(vs))));
398
399 /* Load descriptors. (load 8 dwords at once) */
400 LLVMValueRef input_indexbuf, output_indexbuf, tmp, desc[8];
401
402 LLVMValueRef index_buffers_and_constants = ac_get_arg(&ctx->ac, param_index_buffers_and_constants);
403 tmp = LLVMBuildPointerCast(builder, index_buffers_and_constants,
404 ac_array_in_const32_addr_space(ctx->ac.v8i32), "");
405 tmp = ac_build_load_to_sgpr(&ctx->ac, tmp, ctx->ac.i32_0);
406
407 for (unsigned i = 0; i < 8; i++)
408 desc[i] = ac_llvm_extract_elem(&ctx->ac, tmp, i);
409
410 input_indexbuf = ac_build_gather_values(&ctx->ac, desc, 4);
411 output_indexbuf = ac_build_gather_values(&ctx->ac, desc + 4, 4);
412
413 /* Compute PrimID and InstanceID. */
414 LLVMValueRef global_thread_id =
415 ac_build_imad(&ctx->ac, ac_get_arg(&ctx->ac, param_block_id),
416 LLVMConstInt(ctx->ac.i32, THREADGROUP_SIZE, 0),
417 ac_get_arg(&ctx->ac, param_local_id));
418 LLVMValueRef prim_id = global_thread_id; /* PrimID within an instance */
419 LLVMValueRef instance_id = ctx->ac.i32_0;
420
421 if (key->opt.cs_instancing) {
422 LLVMValueRef num_prims_udiv_terms =
423 ac_get_arg(&ctx->ac, param_num_prims_udiv_terms);
424 LLVMValueRef num_prims_udiv_multiplier =
425 ac_get_arg(&ctx->ac, param_num_prims_udiv_multiplier);
426 /* Unpack num_prims_udiv_terms. */
427 LLVMValueRef post_shift = LLVMBuildAnd(builder, num_prims_udiv_terms,
428 LLVMConstInt(ctx->ac.i32, 0x1f, 0), "");
429 LLVMValueRef prims_per_instance = LLVMBuildLShr(builder, num_prims_udiv_terms,
430 LLVMConstInt(ctx->ac.i32, 5, 0), "");
431 /* Divide the total prim_id by the number of prims per instance. */
432 instance_id = ac_build_fast_udiv_u31_d_not_one(&ctx->ac, prim_id,
433 num_prims_udiv_multiplier,
434 post_shift);
435 /* Compute the remainder. */
436 prim_id = LLVMBuildSub(builder, prim_id,
437 LLVMBuildMul(builder, instance_id,
438 prims_per_instance, ""), "");
439 }
440
441 /* Generate indices (like a non-indexed draw call). */
442 LLVMValueRef index[4] = {NULL, NULL, NULL, LLVMGetUndef(ctx->ac.i32)};
443 unsigned vertices_per_prim = 3;
444
445 switch (key->opt.cs_prim_type) {
446 case PIPE_PRIM_TRIANGLES:
447 for (unsigned i = 0; i < 3; i++) {
448 index[i] = ac_build_imad(&ctx->ac, prim_id,
449 LLVMConstInt(ctx->ac.i32, 3, 0),
450 LLVMConstInt(ctx->ac.i32, i, 0));
451 }
452 break;
453 case PIPE_PRIM_TRIANGLE_STRIP:
454 for (unsigned i = 0; i < 3; i++) {
455 index[i] = LLVMBuildAdd(builder, prim_id,
456 LLVMConstInt(ctx->ac.i32, i, 0), "");
457 }
458 break;
459 case PIPE_PRIM_TRIANGLE_FAN:
460 /* Vertex 1 is first and vertex 2 is last. This will go to the hw clipper
461 * and rasterizer as a normal triangle, so we need to put the provoking
462 * vertex into the correct index variable and preserve orientation at the same time.
463 * gl_VertexID is preserved, because it's equal to the index.
464 */
465 if (key->opt.cs_provoking_vertex_first) {
466 index[0] = LLVMBuildAdd(builder, prim_id, LLVMConstInt(ctx->ac.i32, 1, 0), "");
467 index[1] = LLVMBuildAdd(builder, prim_id, LLVMConstInt(ctx->ac.i32, 2, 0), "");
468 index[2] = ctx->ac.i32_0;
469 } else {
470 index[0] = ctx->ac.i32_0;
471 index[1] = LLVMBuildAdd(builder, prim_id, LLVMConstInt(ctx->ac.i32, 1, 0), "");
472 index[2] = LLVMBuildAdd(builder, prim_id, LLVMConstInt(ctx->ac.i32, 2, 0), "");
473 }
474 break;
475 default:
476 unreachable("unexpected primitive type");
477 }
478
479 /* Fetch indices. */
480 if (key->opt.cs_indexed) {
481 for (unsigned i = 0; i < 3; i++) {
482 index[i] = ac_build_buffer_load_format(&ctx->ac, input_indexbuf,
483 index[i], ctx->ac.i32_0, 1,
484 0, true);
485 index[i] = ac_to_integer(&ctx->ac, index[i]);
486 }
487 }
488
489 LLVMValueRef ordered_wave_id = ac_get_arg(&ctx->ac, param_ordered_wave_id);
490
491 /* Extract the ordered wave ID. */
492 if (VERTEX_COUNTER_GDS_MODE == 2) {
493 ordered_wave_id = LLVMBuildLShr(builder, ordered_wave_id,
494 LLVMConstInt(ctx->ac.i32, 6, 0), "");
495 ordered_wave_id = LLVMBuildAnd(builder, ordered_wave_id,
496 LLVMConstInt(ctx->ac.i32, 0xfff, 0), "");
497 }
498 LLVMValueRef thread_id =
499 LLVMBuildAnd(builder, ac_get_arg(&ctx->ac, param_local_id),
500 LLVMConstInt(ctx->ac.i32, 63, 0), "");
501
502 /* Every other triangle in a strip has a reversed vertex order, so we
503 * need to swap vertices of odd primitives to get the correct primitive
504 * orientation when converting triangle strips to triangles. Primitive
505 * restart complicates it, because a strip can start anywhere.
506 */
507 LLVMValueRef prim_restart_accepted = ctx->ac.i1true;
508 LLVMValueRef vertex_counter = ac_get_arg(&ctx->ac, param_vertex_counter);
509
510 if (key->opt.cs_prim_type == PIPE_PRIM_TRIANGLE_STRIP) {
511 /* Without primitive restart, odd primitives have reversed orientation.
512 * Only primitive restart can flip it with respect to the first vertex
513 * of the draw call.
514 */
515 LLVMValueRef first_is_odd = ctx->ac.i1false;
516
517 /* Handle primitive restart. */
518 if (key->opt.cs_primitive_restart) {
519 /* Get the GDS primitive restart continue flag and clear
520 * the flag in vertex_counter. This flag is used when the draw
521 * call was split and we need to load the primitive orientation
522 * flag from GDS for the first wave too.
523 */
524 LLVMValueRef gds_prim_restart_continue =
525 LLVMBuildLShr(builder, vertex_counter,
526 LLVMConstInt(ctx->ac.i32, 31, 0), "");
527 gds_prim_restart_continue =
528 LLVMBuildTrunc(builder, gds_prim_restart_continue, ctx->ac.i1, "");
529 vertex_counter = LLVMBuildAnd(builder, vertex_counter,
530 LLVMConstInt(ctx->ac.i32, 0x7fffffff, 0), "");
531
532 LLVMValueRef index0_is_reset;
533
534 for (unsigned i = 0; i < 3; i++) {
535 LLVMValueRef not_reset = LLVMBuildICmp(builder, LLVMIntNE, index[i],
536 ac_get_arg(&ctx->ac, param_restart_index),
537 "");
538 if (i == 0)
539 index0_is_reset = LLVMBuildNot(builder, not_reset, "");
540 prim_restart_accepted = LLVMBuildAnd(builder, prim_restart_accepted,
541 not_reset, "");
542 }
543
544 /* If the previous waves flip the primitive orientation
545 * of the current triangle strip, it will be stored in GDS.
546 *
547 * Sometimes the correct orientation is not needed, in which case
548 * we don't need to execute this.
549 */
550 if (key->opt.cs_need_correct_orientation && VERTEX_COUNTER_GDS_MODE == 2) {
551 /* If there are reset indices in this wave, get the thread index
552 * where the most recent strip starts relative to each thread.
553 */
554 LLVMValueRef preceding_threads_mask =
555 LLVMBuildSub(builder,
556 LLVMBuildShl(builder, ctx->ac.i64_1,
557 LLVMBuildZExt(builder, thread_id, ctx->ac.i64, ""), ""),
558 ctx->ac.i64_1, "");
559
560 LLVMValueRef reset_threadmask = ac_get_i1_sgpr_mask(&ctx->ac, index0_is_reset);
561 LLVMValueRef preceding_reset_threadmask =
562 LLVMBuildAnd(builder, reset_threadmask, preceding_threads_mask, "");
563 LLVMValueRef strip_start =
564 ac_build_umsb(&ctx->ac, preceding_reset_threadmask, NULL);
565 strip_start = LLVMBuildAdd(builder, strip_start, ctx->ac.i32_1, "");
566
567 /* This flips the orientatino based on reset indices within this wave only. */
568 first_is_odd = LLVMBuildTrunc(builder, strip_start, ctx->ac.i1, "");
569
570 LLVMValueRef last_strip_start, prev_wave_state, ret, tmp;
571 LLVMValueRef is_first_wave, current_wave_resets_index;
572
573 /* Get the thread index where the last strip starts in this wave.
574 *
575 * If the last strip doesn't start in this wave, the thread index
576 * will be 0.
577 *
578 * If the last strip starts in the next wave, the thread index will
579 * be 64.
580 */
581 last_strip_start = ac_build_umsb(&ctx->ac, reset_threadmask, NULL);
582 last_strip_start = LLVMBuildAdd(builder, last_strip_start, ctx->ac.i32_1, "");
583
584 struct si_thread0_section section;
585 si_enter_thread0_section(ctx, &section, thread_id);
586
587 /* This must be done in the thread 0 section, because
588 * we expect PrimID to be 0 for the whole first wave
589 * in this expression.
590 *
591 * NOTE: This will need to be different if we wanna support
592 * instancing with primitive restart.
593 */
594 is_first_wave = LLVMBuildICmp(builder, LLVMIntEQ, prim_id, ctx->ac.i32_0, "");
595 is_first_wave = LLVMBuildAnd(builder, is_first_wave,
596 LLVMBuildNot(builder,
597 gds_prim_restart_continue, ""), "");
598 current_wave_resets_index = LLVMBuildICmp(builder, LLVMIntNE,
599 last_strip_start, ctx->ac.i32_0, "");
600
601 ret = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "prev_state");
602
603 /* Save the last strip start primitive index in GDS and read
604 * the value that previous waves stored.
605 *
606 * if (is_first_wave || current_wave_resets_strip)
607 * // Read the value that previous waves stored and store a new one.
608 * first_is_odd = ds.ordered.swap(last_strip_start);
609 * else
610 * // Just read the value that previous waves stored.
611 * first_is_odd = ds.ordered.add(0);
612 */
613 ac_build_ifcc(&ctx->ac,
614 LLVMBuildOr(builder, is_first_wave,
615 current_wave_resets_index, ""), 12602);
616 {
617 /* The GDS address is always 0 with ordered append. */
618 tmp = si_build_ds_ordered_op(ctx, "swap",
619 ordered_wave_id, last_strip_start,
620 1, true, false);
621 LLVMBuildStore(builder, tmp, ret);
622 }
623 ac_build_else(&ctx->ac, 12603);
624 {
625 /* Just read the value from GDS. */
626 tmp = si_build_ds_ordered_op(ctx, "add",
627 ordered_wave_id, ctx->ac.i32_0,
628 1, true, false);
629 LLVMBuildStore(builder, tmp, ret);
630 }
631 ac_build_endif(&ctx->ac, 12602);
632
633 prev_wave_state = LLVMBuildLoad(builder, ret, "");
634 /* Ignore the return value if this is the first wave. */
635 prev_wave_state = LLVMBuildSelect(builder, is_first_wave,
636 ctx->ac.i32_0, prev_wave_state, "");
637 si_exit_thread0_section(&section, &prev_wave_state);
638 prev_wave_state = LLVMBuildTrunc(builder, prev_wave_state, ctx->ac.i1, "");
639
640 /* If the strip start appears to be on thread 0 for the current primitive
641 * (meaning the reset index is not present in this wave and might have
642 * appeared in previous waves), use the value from GDS to determine
643 * primitive orientation.
644 *
645 * If the strip start is in this wave for the current primitive, use
646 * the value from the current wave to determine primitive orientation.
647 */
648 LLVMValueRef strip_start_is0 = LLVMBuildICmp(builder, LLVMIntEQ,
649 strip_start, ctx->ac.i32_0, "");
650 first_is_odd = LLVMBuildSelect(builder, strip_start_is0, prev_wave_state,
651 first_is_odd, "");
652 }
653 }
654 /* prim_is_odd = (first_is_odd + current_is_odd) % 2. */
655 LLVMValueRef prim_is_odd =
656 LLVMBuildXor(builder, first_is_odd,
657 LLVMBuildTrunc(builder, thread_id, ctx->ac.i1, ""), "");
658
659 /* Convert triangle strip indices to triangle indices. */
660 ac_build_triangle_strip_indices_to_triangle(&ctx->ac, prim_is_odd,
661 LLVMConstInt(ctx->ac.i1, key->opt.cs_provoking_vertex_first, 0),
662 index);
663 }
664
665 /* Execute the vertex shader for each vertex to get vertex positions. */
666 LLVMValueRef pos[3][4];
667 for (unsigned i = 0; i < vertices_per_prim; i++) {
668 vs_params[param_vertex_id] = index[i];
669 vs_params[param_instance_id] = instance_id;
670
671 LLVMValueRef ret = ac_build_call(&ctx->ac, vs, vs_params, num_vs_params);
672 for (unsigned chan = 0; chan < 4; chan++)
673 pos[i][chan] = LLVMBuildExtractValue(builder, ret, chan, "");
674 }
675
676 /* Divide XYZ by W. */
677 for (unsigned i = 0; i < vertices_per_prim; i++) {
678 for (unsigned chan = 0; chan < 3; chan++)
679 pos[i][chan] = ac_build_fdiv(&ctx->ac, pos[i][chan], pos[i][3]);
680 }
681
682 /* Load the viewport state. */
683 LLVMValueRef vp = ac_build_load_invariant(&ctx->ac, index_buffers_and_constants,
684 LLVMConstInt(ctx->ac.i32, 2, 0));
685 vp = LLVMBuildBitCast(builder, vp, ctx->ac.v4f32, "");
686 LLVMValueRef vp_scale[2], vp_translate[2];
687 vp_scale[0] = ac_llvm_extract_elem(&ctx->ac, vp, 0);
688 vp_scale[1] = ac_llvm_extract_elem(&ctx->ac, vp, 1);
689 vp_translate[0] = ac_llvm_extract_elem(&ctx->ac, vp, 2);
690 vp_translate[1] = ac_llvm_extract_elem(&ctx->ac, vp, 3);
691
692 /* Do culling. */
693 struct ac_cull_options options = {};
694 options.cull_front = key->opt.cs_cull_front;
695 options.cull_back = key->opt.cs_cull_back;
696 options.cull_view_xy = true;
697 options.cull_view_near_z = CULL_Z && key->opt.cs_cull_z;
698 options.cull_view_far_z = CULL_Z && key->opt.cs_cull_z;
699 options.cull_small_prims = true;
700 options.cull_zero_area = true;
701 options.cull_w = true;
702 options.use_halfz_clip_space = key->opt.cs_halfz_clip_space;
703
704 LLVMValueRef accepted =
705 ac_cull_triangle(&ctx->ac, pos, prim_restart_accepted,
706 vp_scale, vp_translate,
707 ac_get_arg(&ctx->ac, param_smallprim_precision),
708 &options);
709
710 ac_build_optimization_barrier(&ctx->ac, &accepted);
711 LLVMValueRef accepted_threadmask = ac_get_i1_sgpr_mask(&ctx->ac, accepted);
712
713 /* Count the number of active threads by doing bitcount(accepted). */
714 LLVMValueRef num_prims_accepted =
715 ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64,
716 &accepted_threadmask, 1, AC_FUNC_ATTR_READNONE);
717 num_prims_accepted = LLVMBuildTrunc(builder, num_prims_accepted, ctx->ac.i32, "");
718
719 LLVMValueRef start;
720
721 /* Execute atomic_add on the vertex count. */
722 struct si_thread0_section section;
723 si_enter_thread0_section(ctx, &section, thread_id);
724 {
725 if (VERTEX_COUNTER_GDS_MODE == 0) {
726 LLVMValueRef num_indices = LLVMBuildMul(builder, num_prims_accepted,
727 LLVMConstInt(ctx->ac.i32, vertices_per_prim, 0), "");
728 vertex_counter = si_expand_32bit_pointer(ctx, vertex_counter);
729 start = LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
730 vertex_counter, num_indices,
731 LLVMAtomicOrderingMonotonic, false);
732 } else if (VERTEX_COUNTER_GDS_MODE == 1) {
733 LLVMValueRef num_indices = LLVMBuildMul(builder, num_prims_accepted,
734 LLVMConstInt(ctx->ac.i32, vertices_per_prim, 0), "");
735 vertex_counter = LLVMBuildIntToPtr(builder, vertex_counter,
736 LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS), "");
737 start = LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
738 vertex_counter, num_indices,
739 LLVMAtomicOrderingMonotonic, false);
740 } else if (VERTEX_COUNTER_GDS_MODE == 2) {
741 LLVMValueRef tmp_store = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
742
743 /* If the draw call was split into multiple subdraws, each using
744 * a separate draw packet, we need to start counting from 0 for
745 * the first compute wave of the subdraw.
746 *
747 * vertex_counter contains the primitive ID of the first thread
748 * in the first wave.
749 *
750 * This is only correct with VERTEX_COUNTER_GDS_MODE == 2:
751 */
752 LLVMValueRef is_first_wave =
753 LLVMBuildICmp(builder, LLVMIntEQ, global_thread_id,
754 vertex_counter, "");
755
756 /* Store the primitive count for ordered append, not vertex count.
757 * The idea is to avoid GDS initialization via CP DMA. The shader
758 * effectively stores the first count using "swap".
759 *
760 * if (first_wave) {
761 * ds.ordered.swap(num_prims_accepted); // store the first primitive count
762 * previous = 0;
763 * } else {
764 * previous = ds.ordered.add(num_prims_accepted) // add the primitive count
765 * }
766 */
767 ac_build_ifcc(&ctx->ac, is_first_wave, 12604);
768 {
769 /* The GDS address is always 0 with ordered append. */
770 si_build_ds_ordered_op(ctx, "swap", ordered_wave_id,
771 num_prims_accepted, 0, true, true);
772 LLVMBuildStore(builder, ctx->ac.i32_0, tmp_store);
773 }
774 ac_build_else(&ctx->ac, 12605);
775 {
776 LLVMBuildStore(builder,
777 si_build_ds_ordered_op(ctx, "add", ordered_wave_id,
778 num_prims_accepted, 0,
779 true, true),
780 tmp_store);
781 }
782 ac_build_endif(&ctx->ac, 12604);
783
784 start = LLVMBuildLoad(builder, tmp_store, "");
785 }
786 }
787 si_exit_thread0_section(&section, &start);
788
789 /* Write the final vertex count to memory. An EOS/EOP event could do this,
790 * but those events are super slow and should be avoided if performance
791 * is a concern. Thanks to GDS ordered append, we can emulate a CS_DONE
792 * event like this.
793 */
794 if (VERTEX_COUNTER_GDS_MODE == 2) {
795 ac_build_ifcc(&ctx->ac,
796 LLVMBuildICmp(builder, LLVMIntEQ, global_thread_id,
797 ac_get_arg(&ctx->ac, param_last_wave_prim_id), ""),
798 12606);
799 LLVMValueRef count = LLVMBuildAdd(builder, start, num_prims_accepted, "");
800 count = LLVMBuildMul(builder, count,
801 LLVMConstInt(ctx->ac.i32, vertices_per_prim, 0), "");
802
803 /* GFX8 needs to disable caching, so that the CP can see the stored value.
804 * MTYPE=3 bypasses TC L2.
805 */
806 if (ctx->screen->info.chip_class <= GFX8) {
807 LLVMValueRef desc[] = {
808 ac_get_arg(&ctx->ac, param_vertex_count_addr),
809 LLVMConstInt(ctx->ac.i32,
810 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0),
811 LLVMConstInt(ctx->ac.i32, 4, 0),
812 LLVMConstInt(ctx->ac.i32, S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
813 S_008F0C_MTYPE(3 /* uncached */), 0),
814 };
815 LLVMValueRef rsrc = ac_build_gather_values(&ctx->ac, desc, 4);
816 ac_build_buffer_store_dword(&ctx->ac, rsrc, count, 1, ctx->ac.i32_0,
817 ctx->ac.i32_0, 0, ac_glc | ac_slc);
818 } else {
819 LLVMBuildStore(builder, count,
820 si_expand_32bit_pointer(ctx,
821 ac_get_arg(&ctx->ac,
822 param_vertex_count_addr)));
823 }
824 ac_build_endif(&ctx->ac, 12606);
825 } else {
826 /* For unordered modes that increment a vertex count instead of
827 * primitive count, convert it into the primitive index.
828 */
829 start = LLVMBuildUDiv(builder, start,
830 LLVMConstInt(ctx->ac.i32, vertices_per_prim, 0), "");
831 }
832
833 /* Now we need to store the indices of accepted primitives into
834 * the output index buffer.
835 */
836 ac_build_ifcc(&ctx->ac, accepted, 16607);
837 {
838 /* Get the number of bits set before the index of this thread. */
839 LLVMValueRef prim_index = ac_build_mbcnt(&ctx->ac, accepted_threadmask);
840
841 /* We have lowered instancing. Pack the instance ID into vertex ID. */
842 if (key->opt.cs_instancing) {
843 instance_id = LLVMBuildShl(builder, instance_id,
844 LLVMConstInt(ctx->ac.i32, 16, 0), "");
845
846 for (unsigned i = 0; i < vertices_per_prim; i++)
847 index[i] = LLVMBuildOr(builder, index[i], instance_id, "");
848 }
849
850 if (VERTEX_COUNTER_GDS_MODE == 2) {
851 /* vertex_counter contains the first primitive ID
852 * for this dispatch. If the draw call was split into
853 * multiple subdraws, the first primitive ID is > 0
854 * for subsequent subdraws. Each subdraw uses a different
855 * portion of the output index buffer. Offset the store
856 * vindex by the first primitive ID to get the correct
857 * store address for the subdraw.
858 */
859 start = LLVMBuildAdd(builder, start, vertex_counter, "");
860 }
861
862 /* Write indices for accepted primitives. */
863 LLVMValueRef vindex = LLVMBuildAdd(builder, start, prim_index, "");
864 LLVMValueRef vdata = ac_build_gather_values(&ctx->ac, index, 3);
865
866 if (!ac_has_vec3_support(ctx->ac.chip_class, true))
867 vdata = ac_build_expand_to_vec4(&ctx->ac, vdata, 3);
868
869 ac_build_buffer_store_format(&ctx->ac, output_indexbuf, vdata,
870 vindex, ctx->ac.i32_0, 3,
871 ac_glc | (INDEX_STORES_USE_SLC ? ac_slc : 0));
872 }
873 ac_build_endif(&ctx->ac, 16607);
874
875 LLVMBuildRetVoid(builder);
876 }
877
878 /* Return false if the shader isn't ready. */
879 static bool si_shader_select_prim_discard_cs(struct si_context *sctx,
880 const struct pipe_draw_info *info,
881 bool primitive_restart)
882 {
883 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
884 struct si_shader_key key;
885
886 /* Primitive restart needs ordered counters. */
887 assert(!primitive_restart || VERTEX_COUNTER_GDS_MODE == 2);
888 assert(!primitive_restart || info->instance_count == 1);
889
890 memset(&key, 0, sizeof(key));
891 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, &key, &key.part.vs.prolog);
892 assert(!key.part.vs.prolog.instance_divisor_is_fetched);
893
894 key.part.vs.prolog.unpack_instance_id_from_vertex_id = 0;
895 key.opt.vs_as_prim_discard_cs = 1;
896 key.opt.cs_prim_type = info->mode;
897 key.opt.cs_indexed = info->index_size != 0;
898 key.opt.cs_instancing = info->instance_count > 1;
899 key.opt.cs_primitive_restart = primitive_restart;
900 key.opt.cs_provoking_vertex_first = rs->provoking_vertex_first;
901
902 /* Primitive restart with triangle strips needs to preserve primitive
903 * orientation for cases where front and back primitive orientation matters.
904 */
905 if (primitive_restart) {
906 struct si_shader_selector *ps = sctx->ps_shader.cso;
907
908 key.opt.cs_need_correct_orientation =
909 rs->cull_front != rs->cull_back ||
910 ps->info.uses_frontface ||
911 (rs->two_side && ps->info.colors_read);
912 }
913
914 if (rs->rasterizer_discard) {
915 /* Just for performance testing and analysis of trivial bottlenecks.
916 * This should result in a very short compute shader. */
917 key.opt.cs_cull_front = 1;
918 key.opt.cs_cull_back = 1;
919 } else {
920 key.opt.cs_cull_front =
921 sctx->viewports.y_inverted ? rs->cull_back : rs->cull_front;
922 key.opt.cs_cull_back =
923 sctx->viewports.y_inverted ? rs->cull_front : rs->cull_back;
924 }
925
926 if (!rs->depth_clamp_any && CULL_Z) {
927 key.opt.cs_cull_z = 1;
928 key.opt.cs_halfz_clip_space = rs->clip_halfz;
929 }
930
931 sctx->cs_prim_discard_state.cso = sctx->vs_shader.cso;
932 sctx->cs_prim_discard_state.current = NULL;
933
934 if (!sctx->compiler.passes)
935 si_init_compiler(sctx->screen, &sctx->compiler);
936
937 struct si_compiler_ctx_state compiler_state;
938 compiler_state.compiler = &sctx->compiler;
939 compiler_state.debug = sctx->debug;
940 compiler_state.is_debug_context = sctx->is_debug;
941
942 return si_shader_select_with_key(sctx->screen, &sctx->cs_prim_discard_state,
943 &compiler_state, &key, -1, true) == 0 &&
944 /* Disallow compute shaders using the scratch buffer. */
945 sctx->cs_prim_discard_state.current->config.scratch_bytes_per_wave == 0;
946 }
947
948 static bool si_initialize_prim_discard_cmdbuf(struct si_context *sctx)
949 {
950 if (sctx->index_ring)
951 return true;
952
953 if (!sctx->prim_discard_compute_cs) {
954 struct radeon_winsys *ws = sctx->ws;
955 unsigned gds_size = VERTEX_COUNTER_GDS_MODE == 1 ? GDS_SIZE_UNORDERED :
956 VERTEX_COUNTER_GDS_MODE == 2 ? 8 : 0;
957 unsigned num_oa_counters = VERTEX_COUNTER_GDS_MODE == 2 ? 2 : 0;
958
959 if (gds_size) {
960 sctx->gds = ws->buffer_create(ws, gds_size, 4,
961 RADEON_DOMAIN_GDS, 0);
962 if (!sctx->gds)
963 return false;
964
965 ws->cs_add_buffer(sctx->gfx_cs, sctx->gds,
966 RADEON_USAGE_READWRITE, 0, 0);
967 }
968 if (num_oa_counters) {
969 assert(gds_size);
970 sctx->gds_oa = ws->buffer_create(ws, num_oa_counters,
971 1, RADEON_DOMAIN_OA, 0);
972 if (!sctx->gds_oa)
973 return false;
974
975 ws->cs_add_buffer(sctx->gfx_cs, sctx->gds_oa,
976 RADEON_USAGE_READWRITE, 0, 0);
977 }
978
979 sctx->prim_discard_compute_cs =
980 ws->cs_add_parallel_compute_ib(sctx->gfx_cs,
981 num_oa_counters > 0);
982 if (!sctx->prim_discard_compute_cs)
983 return false;
984 }
985
986 if (!sctx->index_ring) {
987 sctx->index_ring =
988 si_aligned_buffer_create(sctx->b.screen,
989 SI_RESOURCE_FLAG_UNMAPPABLE,
990 PIPE_USAGE_DEFAULT,
991 sctx->index_ring_size_per_ib * 2,
992 sctx->screen->info.pte_fragment_size);
993 if (!sctx->index_ring)
994 return false;
995 }
996 return true;
997 }
998
999 static bool si_check_ring_space(struct si_context *sctx, unsigned out_indexbuf_size)
1000 {
1001 return sctx->index_ring_offset +
1002 align(out_indexbuf_size, sctx->screen->info.tcc_cache_line_size) <=
1003 sctx->index_ring_size_per_ib;
1004 }
1005
1006 enum si_prim_discard_outcome
1007 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1008 const struct pipe_draw_info *info,
1009 bool primitive_restart)
1010 {
1011 /* If the compute shader compilation isn't finished, this returns false. */
1012 if (!si_shader_select_prim_discard_cs(sctx, info, primitive_restart))
1013 return SI_PRIM_DISCARD_DISABLED;
1014
1015 if (!si_initialize_prim_discard_cmdbuf(sctx))
1016 return SI_PRIM_DISCARD_DISABLED;
1017
1018 struct radeon_cmdbuf *gfx_cs = sctx->gfx_cs;
1019 unsigned prim = info->mode;
1020 unsigned count = info->count;
1021 unsigned instance_count = info->instance_count;
1022 unsigned num_prims_per_instance = u_decomposed_prims_for_vertices(prim, count);
1023 unsigned num_prims = num_prims_per_instance * instance_count;
1024 unsigned out_indexbuf_size = num_prims * 12;
1025 bool ring_full = !si_check_ring_space(sctx, out_indexbuf_size);
1026 const unsigned split_prims_draw_level = SPLIT_PRIMS_DRAW_LEVEL;
1027
1028 /* Split draws at the draw call level if the ring is full. This makes
1029 * better use of the ring space.
1030 */
1031 if (ring_full &&
1032 num_prims > split_prims_draw_level &&
1033 instance_count == 1 && /* TODO: support splitting instanced draws */
1034 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1035 (1 << PIPE_PRIM_TRIANGLE_STRIP))) {
1036 /* Split draws. */
1037 struct pipe_draw_info split_draw = *info;
1038 split_draw.primitive_restart = primitive_restart;
1039
1040 unsigned base_start = split_draw.start;
1041
1042 if (prim == PIPE_PRIM_TRIANGLES) {
1043 unsigned vert_count_per_subdraw = split_prims_draw_level * 3;
1044 assert(vert_count_per_subdraw < count);
1045
1046 for (unsigned start = 0; start < count; start += vert_count_per_subdraw) {
1047 split_draw.start = base_start + start;
1048 split_draw.count = MIN2(count - start, vert_count_per_subdraw);
1049
1050 sctx->b.draw_vbo(&sctx->b, &split_draw);
1051 }
1052 } else if (prim == PIPE_PRIM_TRIANGLE_STRIP) {
1053 /* No primitive pair can be split, because strips reverse orientation
1054 * for odd primitives. */
1055 STATIC_ASSERT(split_prims_draw_level % 2 == 0);
1056
1057 unsigned vert_count_per_subdraw = split_prims_draw_level;
1058
1059 for (unsigned start = 0; start < count - 2; start += vert_count_per_subdraw) {
1060 split_draw.start = base_start + start;
1061 split_draw.count = MIN2(count - start, vert_count_per_subdraw + 2);
1062
1063 sctx->b.draw_vbo(&sctx->b, &split_draw);
1064
1065 if (start == 0 &&
1066 primitive_restart &&
1067 sctx->cs_prim_discard_state.current->key.opt.cs_need_correct_orientation)
1068 sctx->preserve_prim_restart_gds_at_flush = true;
1069 }
1070 sctx->preserve_prim_restart_gds_at_flush = false;
1071 } else {
1072 assert(0);
1073 }
1074
1075 return SI_PRIM_DISCARD_DRAW_SPLIT;
1076 }
1077
1078 /* Just quit if the draw call doesn't fit into the ring and can't be split. */
1079 if (out_indexbuf_size > sctx->index_ring_size_per_ib) {
1080 if (SI_PRIM_DISCARD_DEBUG)
1081 puts("PD failed: draw call too big, can't be split");
1082 return SI_PRIM_DISCARD_DISABLED;
1083 }
1084
1085 unsigned num_subdraws = DIV_ROUND_UP(num_prims, SPLIT_PRIMS_PACKET_LEVEL);
1086 unsigned need_compute_dw = 11 /* shader */ + 34 /* first draw */ +
1087 24 * (num_subdraws - 1) + /* subdraws */
1088 20; /* leave some space at the end */
1089 unsigned need_gfx_dw = si_get_minimum_num_gfx_cs_dwords(sctx);
1090
1091 if (sctx->chip_class <= GFX7 || FORCE_REWIND_EMULATION)
1092 need_gfx_dw += 9; /* NOP(2) + WAIT_REG_MEM(7), then chain */
1093 else
1094 need_gfx_dw += num_subdraws * 8; /* use REWIND(2) + DRAW(6) */
1095
1096 if (ring_full ||
1097 (VERTEX_COUNTER_GDS_MODE == 1 && sctx->compute_gds_offset + 8 > GDS_SIZE_UNORDERED) ||
1098 !sctx->ws->cs_check_space(gfx_cs, need_gfx_dw, false)) {
1099 /* If the current IB is empty but the size is too small, add a NOP
1100 * packet to force a flush and get a bigger IB.
1101 */
1102 if (!radeon_emitted(gfx_cs, sctx->initial_gfx_cs_size) &&
1103 gfx_cs->current.cdw + need_gfx_dw > gfx_cs->current.max_dw) {
1104 radeon_emit(gfx_cs, PKT3(PKT3_NOP, 0, 0));
1105 radeon_emit(gfx_cs, 0);
1106 }
1107
1108 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1109 }
1110
1111 /* The compute IB is always chained, but we need to call cs_check_space to add more space. */
1112 struct radeon_cmdbuf *cs = sctx->prim_discard_compute_cs;
1113 ASSERTED bool compute_has_space = sctx->ws->cs_check_space(cs, need_compute_dw, false);
1114 assert(compute_has_space);
1115 assert(si_check_ring_space(sctx, out_indexbuf_size));
1116 return SI_PRIM_DISCARD_ENABLED;
1117 }
1118
1119 void si_compute_signal_gfx(struct si_context *sctx)
1120 {
1121 struct radeon_cmdbuf *cs = sctx->prim_discard_compute_cs;
1122 unsigned writeback_L2_flags = 0;
1123
1124 /* The writeback L2 flags vary with each chip generation. */
1125 /* CI needs to flush vertex indices to memory. */
1126 if (sctx->chip_class <= GFX7)
1127 writeback_L2_flags = EVENT_TC_WB_ACTION_ENA;
1128 else if (sctx->chip_class == GFX8 && VERTEX_COUNTER_GDS_MODE == 0)
1129 writeback_L2_flags = EVENT_TC_WB_ACTION_ENA | EVENT_TC_NC_ACTION_ENA;
1130
1131 if (!sctx->compute_num_prims_in_batch)
1132 return;
1133
1134 assert(sctx->compute_rewind_va);
1135
1136 /* After the queued dispatches are done and vertex counts are written to
1137 * the gfx IB, signal the gfx IB to continue. CP doesn't wait for
1138 * the dispatches to finish, it only adds the CS_DONE event into the event
1139 * queue.
1140 */
1141 si_cp_release_mem(sctx, cs, V_028A90_CS_DONE, writeback_L2_flags,
1142 sctx->chip_class <= GFX8 ? EOP_DST_SEL_MEM : EOP_DST_SEL_TC_L2,
1143 writeback_L2_flags ? EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM :
1144 EOP_INT_SEL_NONE,
1145 EOP_DATA_SEL_VALUE_32BIT,
1146 NULL,
1147 sctx->compute_rewind_va |
1148 ((uint64_t)sctx->screen->info.address32_hi << 32),
1149 REWIND_SIGNAL_BIT, /* signaling value for the REWIND packet */
1150 SI_NOT_QUERY);
1151
1152 sctx->compute_rewind_va = 0;
1153 sctx->compute_num_prims_in_batch = 0;
1154 }
1155
1156 /* Dispatch a primitive discard compute shader. */
1157 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1158 const struct pipe_draw_info *info,
1159 unsigned index_size,
1160 unsigned base_vertex,
1161 uint64_t input_indexbuf_va,
1162 unsigned input_indexbuf_num_elements)
1163 {
1164 struct radeon_cmdbuf *gfx_cs = sctx->gfx_cs;
1165 struct radeon_cmdbuf *cs = sctx->prim_discard_compute_cs;
1166 unsigned num_prims_per_instance = u_decomposed_prims_for_vertices(info->mode, info->count);
1167 if (!num_prims_per_instance)
1168 return;
1169
1170 unsigned num_prims = num_prims_per_instance * info->instance_count;
1171 unsigned vertices_per_prim, output_indexbuf_format;
1172
1173 switch (info->mode) {
1174 case PIPE_PRIM_TRIANGLES:
1175 case PIPE_PRIM_TRIANGLE_STRIP:
1176 case PIPE_PRIM_TRIANGLE_FAN:
1177 vertices_per_prim = 3;
1178 output_indexbuf_format = V_008F0C_BUF_DATA_FORMAT_32_32_32;
1179 break;
1180 default:
1181 unreachable("unsupported primitive type");
1182 return;
1183 }
1184
1185 unsigned out_indexbuf_offset;
1186 uint64_t output_indexbuf_size = num_prims * vertices_per_prim * 4;
1187 bool first_dispatch = !sctx->prim_discard_compute_ib_initialized;
1188
1189 /* Initialize the compute IB if it's empty. */
1190 if (!sctx->prim_discard_compute_ib_initialized) {
1191 /* 1) State initialization. */
1192 sctx->compute_gds_offset = 0;
1193 sctx->compute_ib_last_shader = NULL;
1194
1195 if (sctx->last_ib_barrier_fence) {
1196 assert(!sctx->last_ib_barrier_buf);
1197 sctx->ws->cs_add_fence_dependency(gfx_cs,
1198 sctx->last_ib_barrier_fence,
1199 RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY);
1200 }
1201
1202 /* 2) IB initialization. */
1203
1204 /* This needs to be done at the beginning of IBs due to possible
1205 * TTM buffer moves in the kernel.
1206 *
1207 * TODO: update for GFX10
1208 */
1209 si_emit_surface_sync(sctx, cs,
1210 S_0085F0_TC_ACTION_ENA(1) |
1211 S_0085F0_TCL1_ACTION_ENA(1) |
1212 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8) |
1213 S_0085F0_SH_ICACHE_ACTION_ENA(1) |
1214 S_0085F0_SH_KCACHE_ACTION_ENA(1));
1215
1216 /* Restore the GDS prim restart counter if needed. */
1217 if (sctx->preserve_prim_restart_gds_at_flush) {
1218 si_cp_copy_data(sctx, cs,
1219 COPY_DATA_GDS, NULL, 4,
1220 COPY_DATA_SRC_MEM, sctx->wait_mem_scratch, 4);
1221 }
1222
1223 si_emit_initial_compute_regs(sctx, cs);
1224
1225 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
1226 S_00B860_WAVES(sctx->scratch_waves) |
1227 S_00B860_WAVESIZE(0)); /* no scratch */
1228
1229 /* Only 1D grids are launched. */
1230 radeon_set_sh_reg_seq(cs, R_00B820_COMPUTE_NUM_THREAD_Y, 2);
1231 radeon_emit(cs, S_00B820_NUM_THREAD_FULL(1) |
1232 S_00B820_NUM_THREAD_PARTIAL(1));
1233 radeon_emit(cs, S_00B824_NUM_THREAD_FULL(1) |
1234 S_00B824_NUM_THREAD_PARTIAL(1));
1235
1236 radeon_set_sh_reg_seq(cs, R_00B814_COMPUTE_START_Y, 2);
1237 radeon_emit(cs, 0);
1238 radeon_emit(cs, 0);
1239
1240 /* Disable ordered alloc for OA resources. */
1241 for (unsigned i = 0; i < 2; i++) {
1242 radeon_set_uconfig_reg_seq(cs, R_031074_GDS_OA_CNTL, 3);
1243 radeon_emit(cs, S_031074_INDEX(i));
1244 radeon_emit(cs, 0);
1245 radeon_emit(cs, S_03107C_ENABLE(0));
1246 }
1247
1248 if (sctx->last_ib_barrier_buf) {
1249 assert(!sctx->last_ib_barrier_fence);
1250 radeon_add_to_buffer_list(sctx, gfx_cs, sctx->last_ib_barrier_buf,
1251 RADEON_USAGE_READ, RADEON_PRIO_FENCE);
1252 si_cp_wait_mem(sctx, cs,
1253 sctx->last_ib_barrier_buf->gpu_address +
1254 sctx->last_ib_barrier_buf_offset, 1, 1,
1255 WAIT_REG_MEM_EQUAL);
1256 }
1257
1258 sctx->prim_discard_compute_ib_initialized = true;
1259 }
1260
1261 /* Allocate the output index buffer. */
1262 output_indexbuf_size = align(output_indexbuf_size,
1263 sctx->screen->info.tcc_cache_line_size);
1264 assert(sctx->index_ring_offset + output_indexbuf_size <= sctx->index_ring_size_per_ib);
1265 out_indexbuf_offset = sctx->index_ring_base + sctx->index_ring_offset;
1266 sctx->index_ring_offset += output_indexbuf_size;
1267
1268 radeon_add_to_buffer_list(sctx, gfx_cs, sctx->index_ring, RADEON_USAGE_READWRITE,
1269 RADEON_PRIO_SHADER_RW_BUFFER);
1270 uint64_t out_indexbuf_va = sctx->index_ring->gpu_address + out_indexbuf_offset;
1271
1272 /* Prepare index buffer descriptors. */
1273 struct si_resource *indexbuf_desc = NULL;
1274 unsigned indexbuf_desc_offset;
1275 unsigned desc_size = 12 * 4;
1276 uint32_t *desc;
1277
1278 u_upload_alloc(sctx->b.const_uploader, 0, desc_size,
1279 si_optimal_tcc_alignment(sctx, desc_size),
1280 &indexbuf_desc_offset, (struct pipe_resource**)&indexbuf_desc,
1281 (void**)&desc);
1282 radeon_add_to_buffer_list(sctx, gfx_cs, indexbuf_desc, RADEON_USAGE_READ,
1283 RADEON_PRIO_DESCRIPTORS);
1284
1285 /* Input index buffer. */
1286 desc[0] = input_indexbuf_va;
1287 desc[1] = S_008F04_BASE_ADDRESS_HI(input_indexbuf_va >> 32) |
1288 S_008F04_STRIDE(index_size);
1289 desc[2] = input_indexbuf_num_elements * (sctx->chip_class == GFX8 ? index_size : 1);
1290 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1291 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
1292 S_008F0C_DATA_FORMAT(index_size == 1 ? V_008F0C_BUF_DATA_FORMAT_8 :
1293 index_size == 2 ? V_008F0C_BUF_DATA_FORMAT_16 :
1294 V_008F0C_BUF_DATA_FORMAT_32);
1295
1296 /* Output index buffer. */
1297 desc[4] = out_indexbuf_va;
1298 desc[5] = S_008F04_BASE_ADDRESS_HI(out_indexbuf_va >> 32) |
1299 S_008F04_STRIDE(vertices_per_prim * 4);
1300 desc[6] = num_prims * (sctx->chip_class == GFX8 ? vertices_per_prim * 4 : 1);
1301 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1302 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1303 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1304 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_0) |
1305 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT) |
1306 S_008F0C_DATA_FORMAT(output_indexbuf_format);
1307
1308 /* Viewport state. */
1309 struct si_small_prim_cull_info cull_info;
1310 si_get_small_prim_cull_info(sctx, &cull_info);
1311
1312 desc[8] = fui(cull_info.scale[0]);
1313 desc[9] = fui(cull_info.scale[1]);
1314 desc[10] = fui(cull_info.translate[0]);
1315 desc[11] = fui(cull_info.translate[1]);
1316
1317 /* Better subpixel precision increases the efficiency of small
1318 * primitive culling. */
1319 unsigned num_samples = sctx->framebuffer.nr_samples;
1320 unsigned quant_mode = sctx->viewports.as_scissor[0].quant_mode;
1321 float small_prim_cull_precision;
1322
1323 if (quant_mode == SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH)
1324 small_prim_cull_precision = num_samples / 4096.0;
1325 else if (quant_mode == SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH)
1326 small_prim_cull_precision = num_samples / 1024.0;
1327 else
1328 small_prim_cull_precision = num_samples / 256.0;
1329
1330 /* Set user data SGPRs. */
1331 /* This can't be greater than 14 if we want the fastest launch rate. */
1332 unsigned user_sgprs = 13;
1333
1334 uint64_t index_buffers_va = indexbuf_desc->gpu_address + indexbuf_desc_offset;
1335 unsigned vs_const_desc = si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX);
1336 unsigned vs_sampler_desc = si_sampler_and_image_descriptors_idx(PIPE_SHADER_VERTEX);
1337 uint64_t vs_const_desc_va = sctx->descriptors[vs_const_desc].gpu_address;
1338 uint64_t vs_sampler_desc_va = sctx->descriptors[vs_sampler_desc].gpu_address;
1339 uint64_t vb_desc_va = sctx->vb_descriptors_buffer ?
1340 sctx->vb_descriptors_buffer->gpu_address +
1341 sctx->vb_descriptors_offset : 0;
1342 unsigned gds_offset, gds_size;
1343 struct si_fast_udiv_info32 num_prims_udiv = {};
1344
1345 if (info->instance_count > 1)
1346 num_prims_udiv = si_compute_fast_udiv_info32(num_prims_per_instance, 31);
1347
1348 /* Limitations on how these two are packed in the user SGPR. */
1349 assert(num_prims_udiv.post_shift < 32);
1350 assert(num_prims_per_instance < 1 << 27);
1351
1352 si_resource_reference(&indexbuf_desc, NULL);
1353
1354 bool primitive_restart = sctx->cs_prim_discard_state.current->key.opt.cs_primitive_restart;
1355
1356 if (VERTEX_COUNTER_GDS_MODE == 1) {
1357 gds_offset = sctx->compute_gds_offset;
1358 gds_size = primitive_restart ? 8 : 4;
1359 sctx->compute_gds_offset += gds_size;
1360
1361 /* Reset the counters in GDS for the first dispatch using WRITE_DATA.
1362 * The remainder of the GDS will be cleared after the dispatch packet
1363 * in parallel with compute shaders.
1364 */
1365 if (first_dispatch) {
1366 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + gds_size/4, 0));
1367 radeon_emit(cs, S_370_DST_SEL(V_370_GDS) | S_370_WR_CONFIRM(1));
1368 radeon_emit(cs, gds_offset);
1369 radeon_emit(cs, 0);
1370 radeon_emit(cs, 0); /* value to write */
1371 if (gds_size == 8)
1372 radeon_emit(cs, 0);
1373 }
1374 }
1375
1376 /* Set shader registers. */
1377 struct si_shader *shader = sctx->cs_prim_discard_state.current;
1378
1379 if (shader != sctx->compute_ib_last_shader) {
1380 radeon_add_to_buffer_list(sctx, gfx_cs, shader->bo, RADEON_USAGE_READ,
1381 RADEON_PRIO_SHADER_BINARY);
1382 uint64_t shader_va = shader->bo->gpu_address;
1383
1384 assert(shader->config.scratch_bytes_per_wave == 0);
1385 assert(shader->config.num_vgprs * WAVES_PER_TG <= 256 * 4);
1386
1387 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
1388 radeon_emit(cs, shader_va >> 8);
1389 radeon_emit(cs, S_00B834_DATA(shader_va >> 40));
1390
1391 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
1392 radeon_emit(cs, S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
1393 S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
1394 S_00B848_FLOAT_MODE(shader->config.float_mode) |
1395 S_00B848_DX10_CLAMP(1));
1396 radeon_emit(cs, S_00B84C_SCRATCH_EN(0 /* no scratch */) |
1397 S_00B84C_USER_SGPR(user_sgprs) |
1398 S_00B84C_TGID_X_EN(1 /* only blockID.x is used */) |
1399 S_00B84C_TG_SIZE_EN(VERTEX_COUNTER_GDS_MODE == 2 /* need the wave ID */) |
1400 S_00B84C_TIDIG_COMP_CNT(0 /* only threadID.x is used */) |
1401 S_00B84C_LDS_SIZE(shader->config.lds_size));
1402
1403 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
1404 ac_get_compute_resource_limits(&sctx->screen->info,
1405 WAVES_PER_TG,
1406 MAX_WAVES_PER_SH,
1407 THREADGROUPS_PER_CU));
1408 sctx->compute_ib_last_shader = shader;
1409 }
1410
1411 STATIC_ASSERT(SPLIT_PRIMS_PACKET_LEVEL % THREADGROUP_SIZE == 0);
1412
1413 /* Big draw calls are split into smaller dispatches and draw packets. */
1414 for (unsigned start_prim = 0; start_prim < num_prims; start_prim += SPLIT_PRIMS_PACKET_LEVEL) {
1415 unsigned num_subdraw_prims;
1416
1417 if (start_prim + SPLIT_PRIMS_PACKET_LEVEL < num_prims)
1418 num_subdraw_prims = SPLIT_PRIMS_PACKET_LEVEL;
1419 else
1420 num_subdraw_prims = num_prims - start_prim;
1421
1422 /* Small dispatches are executed back to back until a specific primitive
1423 * count is reached. Then, a CS_DONE is inserted to signal the gfx IB
1424 * to start drawing the batch. This batching adds latency to the gfx IB,
1425 * but CS_DONE and REWIND are too slow.
1426 */
1427 if (sctx->compute_num_prims_in_batch + num_subdraw_prims > PRIMS_PER_BATCH)
1428 si_compute_signal_gfx(sctx);
1429
1430 if (sctx->compute_num_prims_in_batch == 0) {
1431 assert((gfx_cs->gpu_address >> 32) == sctx->screen->info.address32_hi);
1432 sctx->compute_rewind_va = gfx_cs->gpu_address + (gfx_cs->current.cdw + 1) * 4;
1433
1434 if (sctx->chip_class <= GFX7 || FORCE_REWIND_EMULATION) {
1435 radeon_emit(gfx_cs, PKT3(PKT3_NOP, 0, 0));
1436 radeon_emit(gfx_cs, 0);
1437
1438 si_cp_wait_mem(sctx, gfx_cs,
1439 sctx->compute_rewind_va |
1440 (uint64_t)sctx->screen->info.address32_hi << 32,
1441 REWIND_SIGNAL_BIT, REWIND_SIGNAL_BIT,
1442 WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_PFP);
1443
1444 /* Use INDIRECT_BUFFER to chain to a different buffer
1445 * to discard the CP prefetch cache.
1446 */
1447 sctx->ws->cs_check_space(gfx_cs, 0, true);
1448 } else {
1449 radeon_emit(gfx_cs, PKT3(PKT3_REWIND, 0, 0));
1450 radeon_emit(gfx_cs, 0);
1451 }
1452 }
1453
1454 sctx->compute_num_prims_in_batch += num_subdraw_prims;
1455
1456 uint32_t count_va = gfx_cs->gpu_address + (gfx_cs->current.cdw + 4) * 4;
1457 uint64_t index_va = out_indexbuf_va + start_prim * 12;
1458
1459 /* Emit the draw packet into the gfx IB. */
1460 radeon_emit(gfx_cs, PKT3(PKT3_DRAW_INDEX_2, 4, 0));
1461 radeon_emit(gfx_cs, num_prims * vertices_per_prim);
1462 radeon_emit(gfx_cs, index_va);
1463 radeon_emit(gfx_cs, index_va >> 32);
1464 radeon_emit(gfx_cs, 0);
1465 radeon_emit(gfx_cs, V_0287F0_DI_SRC_SEL_DMA);
1466
1467 /* Continue with the compute IB. */
1468 if (start_prim == 0) {
1469 uint32_t gds_prim_restart_continue_bit = 0;
1470
1471 if (sctx->preserve_prim_restart_gds_at_flush) {
1472 assert(primitive_restart &&
1473 info->mode == PIPE_PRIM_TRIANGLE_STRIP);
1474 assert(start_prim < 1 << 31);
1475 gds_prim_restart_continue_bit = 1 << 31;
1476 }
1477
1478 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, user_sgprs);
1479 radeon_emit(cs, index_buffers_va);
1480 radeon_emit(cs,
1481 VERTEX_COUNTER_GDS_MODE == 0 ? count_va :
1482 VERTEX_COUNTER_GDS_MODE == 1 ? gds_offset :
1483 start_prim |
1484 gds_prim_restart_continue_bit);
1485 radeon_emit(cs, start_prim + num_subdraw_prims - 1);
1486 radeon_emit(cs, count_va);
1487 radeon_emit(cs, vb_desc_va);
1488 radeon_emit(cs, vs_const_desc_va);
1489 radeon_emit(cs, vs_sampler_desc_va);
1490 radeon_emit(cs, base_vertex);
1491 radeon_emit(cs, info->start_instance);
1492 radeon_emit(cs, num_prims_udiv.multiplier);
1493 radeon_emit(cs, num_prims_udiv.post_shift |
1494 (num_prims_per_instance << 5));
1495 radeon_emit(cs, info->restart_index);
1496 /* small-prim culling precision (same as rasterizer precision = QUANT_MODE) */
1497 radeon_emit(cs, fui(small_prim_cull_precision));
1498 } else {
1499 assert(VERTEX_COUNTER_GDS_MODE == 2);
1500 /* Only update the SGPRs that changed. */
1501 radeon_set_sh_reg_seq(cs, R_00B904_COMPUTE_USER_DATA_1, 3);
1502 radeon_emit(cs, start_prim);
1503 radeon_emit(cs, start_prim + num_subdraw_prims - 1);
1504 radeon_emit(cs, count_va);
1505 }
1506
1507 /* Set grid dimensions. */
1508 unsigned start_block = start_prim / THREADGROUP_SIZE;
1509 unsigned num_full_blocks = num_subdraw_prims / THREADGROUP_SIZE;
1510 unsigned partial_block_size = num_subdraw_prims % THREADGROUP_SIZE;
1511
1512 radeon_set_sh_reg(cs, R_00B810_COMPUTE_START_X, start_block);
1513 radeon_set_sh_reg(cs, R_00B81C_COMPUTE_NUM_THREAD_X,
1514 S_00B81C_NUM_THREAD_FULL(THREADGROUP_SIZE) |
1515 S_00B81C_NUM_THREAD_PARTIAL(partial_block_size));
1516
1517 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
1518 PKT3_SHADER_TYPE_S(1));
1519 radeon_emit(cs, start_block + num_full_blocks + !!partial_block_size);
1520 radeon_emit(cs, 1);
1521 radeon_emit(cs, 1);
1522 radeon_emit(cs, S_00B800_COMPUTE_SHADER_EN(1) |
1523 S_00B800_PARTIAL_TG_EN(!!partial_block_size) |
1524 S_00B800_ORDERED_APPEND_ENBL(VERTEX_COUNTER_GDS_MODE == 2) |
1525 S_00B800_ORDER_MODE(0 /* launch in order */));
1526
1527 /* This is only for unordered append. Ordered append writes this from
1528 * the shader.
1529 *
1530 * Note that EOP and EOS events are super slow, so emulating the event
1531 * in a shader is an important optimization.
1532 */
1533 if (VERTEX_COUNTER_GDS_MODE == 1) {
1534 si_cp_release_mem(sctx, cs, V_028A90_CS_DONE, 0,
1535 sctx->chip_class <= GFX8 ? EOP_DST_SEL_MEM : EOP_DST_SEL_TC_L2,
1536 EOP_INT_SEL_NONE,
1537 EOP_DATA_SEL_GDS,
1538 NULL,
1539 count_va | ((uint64_t)sctx->screen->info.address32_hi << 32),
1540 EOP_DATA_GDS(gds_offset / 4, 1),
1541 SI_NOT_QUERY);
1542
1543 /* Now that compute shaders are running, clear the remainder of GDS. */
1544 if (first_dispatch) {
1545 unsigned offset = gds_offset + gds_size;
1546 si_cp_dma_clear_buffer(sctx, cs, NULL, offset,
1547 GDS_SIZE_UNORDERED - offset,
1548 0,
1549 SI_CPDMA_SKIP_CHECK_CS_SPACE |
1550 SI_CPDMA_SKIP_GFX_SYNC |
1551 SI_CPDMA_SKIP_SYNC_BEFORE,
1552 SI_COHERENCY_NONE, L2_BYPASS);
1553 }
1554 }
1555 first_dispatch = false;
1556
1557 assert(cs->current.cdw <= cs->current.max_dw);
1558 assert(gfx_cs->current.cdw <= gfx_cs->current.max_dw);
1559 }
1560 }