2 * Copyright 2019 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_shader_internal.h"
29 #include "si_build_pm4.h"
30 #include "ac_llvm_cull.h"
32 #include "util/u_prim.h"
33 #include "util/u_suballoc.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
38 * https://frostbite-wp-prd.s3.amazonaws.com/wp-content/uploads/2016/03/29204330/GDC_2016_Compute.pdf
41 /* This file implements primitive culling using asynchronous compute.
42 * It's written to be GL conformant.
44 * It takes a monolithic VS in LLVM IR returning gl_Position and invokes it
45 * in a compute shader. The shader processes 1 primitive/thread by invoking
46 * the VS for each vertex to get the positions, decomposes strips and fans
47 * into triangles (if needed), eliminates primitive restart (if needed),
48 * does (W<0) culling, face culling, view XY culling, zero-area and
49 * small-primitive culling, and generates a new index buffer that doesn't
50 * contain culled primitives.
52 * The index buffer is generated using the Ordered Count feature of GDS,
53 * which is an atomic counter that is incremented in the wavefront launch
54 * order, so that the original primitive order is preserved.
56 * Another GDS ordered counter is used to eliminate primitive restart indices.
57 * If a restart index lands on an even thread ID, the compute shader has to flip
58 * the primitive orientation of the whole following triangle strip. The primitive
59 * orientation has to be correct after strip and fan decomposition for two-sided
60 * shading to behave correctly. The decomposition also needs to be aware of
61 * which vertex is the provoking vertex for flat shading to behave correctly.
63 * IB = a GPU command buffer
65 * Both the compute and gfx IBs run in parallel sort of like CE and DE.
66 * The gfx IB has a CP barrier (REWIND packet) before a draw packet. REWIND
67 * doesn't continue if its word isn't 0x80000000. Once compute shaders are
68 * finished culling, the last wave will write the final primitive count from
69 * GDS directly into the count word of the draw packet in the gfx IB, and
70 * a CS_DONE event will signal the REWIND packet to continue. It's really
71 * a direct draw with command buffer patching from the compute queue.
73 * The compute IB doesn't have to start when its corresponding gfx IB starts,
74 * but can start sooner. The compute IB is signaled to start after the last
75 * execution barrier in the *previous* gfx IB. This is handled as follows.
76 * The kernel GPU scheduler starts the compute IB after the previous gfx IB has
77 * started. The compute IB then waits (WAIT_REG_MEM) for a mid-IB fence that
78 * represents the barrier in the previous gfx IB.
81 * - Triangle strips and fans are decomposed into an indexed triangle list.
82 * The decomposition differs based on the provoking vertex state.
83 * - Instanced draws are converted into non-instanced draws for 16-bit indices.
84 * (InstanceID is stored in the high bits of VertexID and unpacked by VS)
85 * - Primitive restart is fully supported with triangle strips, including
86 * correct primitive orientation across multiple waves. (restart indices
87 * reset primitive orientation)
88 * - W<0 culling (W<0 is behind the viewer, sort of like near Z culling).
89 * - Back face culling, incl. culling zero-area / degenerate primitives.
91 * - View Z culling (disabled due to limited impact with perspective projection).
92 * - Small primitive culling for all MSAA modes and all quant modes.
94 * The following are not implemented:
95 * - ClipVertex/ClipDistance/CullDistance-based culling.
99 * Limitations (and unimplemented features that may be possible to implement):
100 * - Only triangles, triangle strips, and triangle fans are supported.
101 * - Primitive restart is only supported with triangle strips.
102 * - Instancing and primitive restart can't be used together.
103 * - Instancing is only supported with 16-bit indices and instance count <= 2^16.
104 * - The instance divisor buffer is unavailable, so all divisors must be
106 * - Multidraws where the vertex shader reads gl_DrawID are unsupported.
107 * - No support for tessellation and geometry shaders.
108 * (patch elimination where tess factors are 0 would be possible to implement)
109 * - The vertex shader must not contain memory stores.
110 * - All VS resources must not have a write usage in the command buffer.
111 * (TODO: all shader buffers currently set the write usage)
112 * - Bindless textures and images must not occur in the vertex shader.
114 * User data SGPR layout:
115 * INDEX_BUFFERS: pointer to constants
116 * 0..3: input index buffer - typed buffer view
117 * 4..7: output index buffer - typed buffer view
118 * 8..11: viewport state - scale.xy, translate.xy
119 * VERTEX_COUNTER: counter address or first primitive ID
120 * - If unordered memory counter: address of "count" in the draw packet
121 * and is incremented atomically by the shader.
122 * - If unordered GDS counter: address of "count" in GDS starting from 0,
123 * must be initialized to 0 before the dispatch.
124 * - If ordered GDS counter: the primitive ID that should reset the vertex
125 * counter to 0 in GDS
126 * LAST_WAVE_PRIM_ID: the primitive ID that should write the final vertex
127 * count to memory if using GDS ordered append
128 * VERTEX_COUNT_ADDR: where the last wave should write the vertex count if
129 * using GDS ordered append
130 * VS.VERTEX_BUFFERS: same value as VS
131 * VS.CONST_AND_SHADER_BUFFERS: same value as VS
132 * VS.SAMPLERS_AND_IMAGES: same value as VS
133 * VS.BASE_VERTEX: same value as VS
134 * VS.START_INSTANCE: same value as VS
135 * NUM_PRIMS_UDIV_MULTIPLIER: For fast 31-bit division by the number of primitives
136 * per instance for instancing.
137 * NUM_PRIMS_UDIV_TERMS:
138 * - Bits [0:4]: "post_shift" for fast 31-bit division for instancing.
139 * - Bits [5:31]: The number of primitives per instance for computing the remainder.
140 * PRIMITIVE_RESTART_INDEX
141 * SMALL_PRIM_CULLING_PRECISION: Scale the primitive bounding box by this number.
144 * The code contains 3 codepaths:
145 * - Unordered memory counter (for debugging, random primitive order, no primitive restart)
146 * - Unordered GDS counter (for debugging, random primitive order, no primitive restart)
147 * - Ordered GDS counter (it preserves the primitive order)
149 * How to test primitive restart (the most complicated part because it needs
150 * to get the primitive orientation right):
151 * Set THREADGROUP_SIZE to 2 to exercise both intra-wave and inter-wave
152 * primitive orientation flips with small draw calls, which is what most tests use.
153 * You can also enable draw call splitting into draw calls with just 2 primitives.
156 /* At least 256 is needed for the fastest wave launch rate from compute queues
157 * due to hw constraints. Nothing in the code needs more than 1 wave/threadgroup. */
158 #define THREADGROUP_SIZE 256 /* high numbers limit available VGPRs */
159 #define THREADGROUPS_PER_CU 1 /* TGs to launch on 1 CU before going onto the next, max 8 */
160 #define MAX_WAVES_PER_SH 0 /* no limit */
161 #define INDEX_STORES_USE_SLC 1 /* don't cache indices if L2 is full */
162 /* Don't cull Z. We already do (W < 0) culling for primitives behind the viewer. */
164 /* 0 = unordered memory counter, 1 = unordered GDS counter, 2 = ordered GDS counter */
165 #define VERTEX_COUNTER_GDS_MODE 2
166 #define GDS_SIZE_UNORDERED (4 * 1024) /* only for the unordered GDS counter */
168 /* Grouping compute dispatches for small draw calls: How many primitives from multiple
169 * draw calls to process by compute before signaling the gfx IB. This reduces the number
170 * of EOP events + REWIND packets, because they decrease performance. */
171 #define PRIMS_PER_BATCH (512 * 1024)
172 /* Draw call splitting at the packet level. This allows signaling the gfx IB
173 * for big draw calls sooner, but doesn't allow context flushes between packets.
174 * Primitive restart is supported. Only implemented for ordered append. */
175 #define SPLIT_PRIMS_PACKET_LEVEL_VALUE PRIMS_PER_BATCH
176 /* If there is not enough ring buffer space for the current IB, split draw calls into
177 * this number of primitives, so that we can flush the context and get free ring space. */
178 #define SPLIT_PRIMS_DRAW_LEVEL PRIMS_PER_BATCH
180 /* Derived values. */
181 #define WAVES_PER_TG DIV_ROUND_UP(THREADGROUP_SIZE, 64)
182 #define SPLIT_PRIMS_PACKET_LEVEL (VERTEX_COUNTER_GDS_MODE == 2 ? \
183 SPLIT_PRIMS_PACKET_LEVEL_VALUE : \
184 UINT_MAX & ~(THREADGROUP_SIZE - 1))
186 #define REWIND_SIGNAL_BIT 0x80000000
187 /* For emulating the rewind packet on CI. */
188 #define FORCE_REWIND_EMULATION 0
190 void si_initialize_prim_discard_tunables(struct si_context
*sctx
)
192 sctx
->prim_discard_vertex_count_threshold
= UINT_MAX
; /* disable */
194 if (sctx
->chip_class
== GFX6
|| /* SI support is not implemented */
195 !sctx
->screen
->info
.has_gds_ordered_append
||
196 sctx
->screen
->debug_flags
& DBG(NO_PD
) ||
197 /* If aux_context == NULL, we are initializing aux_context right now. */
198 !sctx
->screen
->aux_context
)
201 /* TODO: enable this after the GDS kernel memory management is fixed */
202 bool enable_on_pro_graphics_by_default
= false;
204 if (sctx
->screen
->debug_flags
& DBG(ALWAYS_PD
) ||
205 sctx
->screen
->debug_flags
& DBG(PD
) ||
206 (enable_on_pro_graphics_by_default
&&
207 sctx
->screen
->info
.is_pro_graphics
&&
208 (sctx
->family
== CHIP_BONAIRE
||
209 sctx
->family
== CHIP_HAWAII
||
210 sctx
->family
== CHIP_TONGA
||
211 sctx
->family
== CHIP_FIJI
||
212 sctx
->family
== CHIP_POLARIS10
||
213 sctx
->family
== CHIP_POLARIS11
||
214 sctx
->family
== CHIP_VEGA10
||
215 sctx
->family
== CHIP_VEGA20
))) {
216 sctx
->prim_discard_vertex_count_threshold
= 6000 * 3; /* 6K triangles */
218 if (sctx
->screen
->debug_flags
& DBG(ALWAYS_PD
))
219 sctx
->prim_discard_vertex_count_threshold
= 0; /* always enable */
221 const uint32_t MB
= 1024 * 1024;
222 const uint64_t GB
= 1024 * 1024 * 1024;
224 /* The total size is double this per context.
225 * Greater numbers allow bigger gfx IBs.
227 if (sctx
->screen
->info
.vram_size
<= 2 * GB
)
228 sctx
->index_ring_size_per_ib
= 64 * MB
;
229 else if (sctx
->screen
->info
.vram_size
<= 4 * GB
)
230 sctx
->index_ring_size_per_ib
= 128 * MB
;
232 sctx
->index_ring_size_per_ib
= 256 * MB
;
236 /* Opcode can be "add" or "swap". */
238 si_build_ds_ordered_op(struct si_shader_context
*ctx
, const char *opcode
,
239 LLVMValueRef m0
, LLVMValueRef value
, unsigned ordered_count_index
,
240 bool release
, bool done
)
242 LLVMValueRef args
[] = {
243 LLVMBuildIntToPtr(ctx
->ac
.builder
, m0
,
244 LLVMPointerType(ctx
->i32
, AC_ADDR_SPACE_GDS
), ""),
246 LLVMConstInt(ctx
->i32
, LLVMAtomicOrderingMonotonic
, 0), /* ordering */
247 ctx
->i32_0
, /* scope */
248 ctx
->i1false
, /* volatile */
249 LLVMConstInt(ctx
->i32
, ordered_count_index
, 0),
250 LLVMConstInt(ctx
->i1
, release
, 0),
251 LLVMConstInt(ctx
->i1
, done
, 0),
255 snprintf(intrinsic
, sizeof(intrinsic
), "llvm.amdgcn.ds.ordered.%s", opcode
);
256 return ac_build_intrinsic(&ctx
->ac
, intrinsic
, ctx
->i32
, args
, ARRAY_SIZE(args
), 0);
259 static LLVMValueRef
si_expand_32bit_pointer(struct si_shader_context
*ctx
, LLVMValueRef ptr
)
261 uint64_t hi
= (uint64_t)ctx
->screen
->info
.address32_hi
<< 32;
262 ptr
= LLVMBuildZExt(ctx
->ac
.builder
, ptr
, ctx
->i64
, "");
263 ptr
= LLVMBuildOr(ctx
->ac
.builder
, ptr
, LLVMConstInt(ctx
->i64
, hi
, 0), "");
264 return LLVMBuildIntToPtr(ctx
->ac
.builder
, ptr
,
265 LLVMPointerType(ctx
->i32
, AC_ADDR_SPACE_GLOBAL
), "");
268 struct si_thread0_section
{
269 struct si_shader_context
*ctx
;
270 LLVMValueRef vgpr_result
; /* a VGPR for the value on thread 0. */
271 LLVMValueRef saved_exec
;
274 /* Enter a section that only executes on thread 0. */
275 static void si_enter_thread0_section(struct si_shader_context
*ctx
,
276 struct si_thread0_section
*section
,
277 LLVMValueRef thread_id
)
280 section
->vgpr_result
= ac_build_alloca_undef(&ctx
->ac
, ctx
->i32
, "result0");
282 /* This IF has 4 instructions:
283 * v_and_b32_e32 v, 63, v ; get the thread ID
284 * v_cmp_eq_u32_e32 vcc, 0, v ; thread ID == 0
285 * s_and_saveexec_b64 s, vcc
286 * s_cbranch_execz BB0_4
288 * It could just be s_and_saveexec_b64 s, 1.
290 ac_build_ifcc(&ctx
->ac
,
291 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, thread_id
,
292 ctx
->i32_0
, ""), 12601);
295 /* Exit a section that only executes on thread 0 and broadcast the result
297 static void si_exit_thread0_section(struct si_thread0_section
*section
,
298 LLVMValueRef
*result
)
300 struct si_shader_context
*ctx
= section
->ctx
;
302 LLVMBuildStore(ctx
->ac
.builder
, *result
, section
->vgpr_result
);
304 ac_build_endif(&ctx
->ac
, 12601);
306 /* Broadcast the result from thread 0 to all threads. */
307 *result
= ac_build_readlane(&ctx
->ac
,
308 LLVMBuildLoad(ctx
->ac
.builder
, section
->vgpr_result
, ""), NULL
);
311 void si_build_prim_discard_compute_shader(struct si_shader_context
*ctx
)
313 struct si_shader_key
*key
= &ctx
->shader
->key
;
314 LLVMBuilderRef builder
= ctx
->ac
.builder
;
315 LLVMValueRef vs
= ctx
->main_fn
;
317 /* Always inline the VS function. */
318 ac_add_function_attr(ctx
->ac
.context
, vs
, -1, AC_FUNC_ATTR_ALWAYSINLINE
);
319 LLVMSetLinkage(vs
, LLVMPrivateLinkage
);
321 LLVMTypeRef const_desc_type
;
322 if (ctx
->shader
->selector
->info
.const_buffers_declared
== 1 &&
323 ctx
->shader
->selector
->info
.shader_buffers_declared
== 0)
324 const_desc_type
= ctx
->f32
;
326 const_desc_type
= ctx
->v4i32
;
328 struct si_function_info fninfo
;
329 si_init_function_info(&fninfo
);
331 LLVMValueRef index_buffers_and_constants
, vertex_counter
, vb_desc
, const_desc
;
332 LLVMValueRef base_vertex
, start_instance
, block_id
, local_id
, ordered_wave_id
;
333 LLVMValueRef restart_index
, vp_scale
[2], vp_translate
[2], smallprim_precision
;
334 LLVMValueRef num_prims_udiv_multiplier
, num_prims_udiv_terms
, sampler_desc
;
335 LLVMValueRef last_wave_prim_id
, vertex_count_addr
;
337 add_arg_assign(&fninfo
, ARG_SGPR
, ac_array_in_const32_addr_space(ctx
->v4i32
),
338 &index_buffers_and_constants
);
339 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &vertex_counter
);
340 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &last_wave_prim_id
);
341 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &vertex_count_addr
);
342 add_arg_assign(&fninfo
, ARG_SGPR
, ac_array_in_const32_addr_space(ctx
->v4i32
),
344 add_arg_assign(&fninfo
, ARG_SGPR
, ac_array_in_const32_addr_space(const_desc_type
),
346 add_arg_assign(&fninfo
, ARG_SGPR
, ac_array_in_const32_addr_space(ctx
->v8i32
),
348 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &base_vertex
);
349 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &start_instance
);
350 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &num_prims_udiv_multiplier
);
351 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &num_prims_udiv_terms
);
352 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &restart_index
);
353 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->f32
, &smallprim_precision
);
355 /* Block ID and thread ID inputs. */
356 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &block_id
);
357 if (VERTEX_COUNTER_GDS_MODE
== 2)
358 add_arg_assign(&fninfo
, ARG_SGPR
, ctx
->i32
, &ordered_wave_id
);
359 add_arg_assign(&fninfo
, ARG_VGPR
, ctx
->i32
, &local_id
);
361 /* Create the compute shader function. */
362 unsigned old_type
= ctx
->type
;
363 ctx
->type
= PIPE_SHADER_COMPUTE
;
364 si_create_function(ctx
, "prim_discard_cs", NULL
, 0, &fninfo
, THREADGROUP_SIZE
);
365 ctx
->type
= old_type
;
367 if (VERTEX_COUNTER_GDS_MODE
== 1) {
368 ac_llvm_add_target_dep_function_attr(ctx
->main_fn
, "amdgpu-gds-size",
372 /* Assemble parameters for VS. */
373 LLVMValueRef vs_params
[16];
374 unsigned num_vs_params
= 0;
375 unsigned param_vertex_id
, param_instance_id
;
377 vs_params
[num_vs_params
++] = LLVMGetUndef(LLVMTypeOf(LLVMGetParam(vs
, 0))); /* RW_BUFFERS */
378 vs_params
[num_vs_params
++] = LLVMGetUndef(LLVMTypeOf(LLVMGetParam(vs
, 1))); /* BINDLESS */
379 vs_params
[num_vs_params
++] = const_desc
;
380 vs_params
[num_vs_params
++] = sampler_desc
;
381 vs_params
[num_vs_params
++] = LLVMConstInt(ctx
->i32
,
382 S_VS_STATE_INDEXED(key
->opt
.cs_indexed
), 0);
383 vs_params
[num_vs_params
++] = base_vertex
;
384 vs_params
[num_vs_params
++] = start_instance
;
385 vs_params
[num_vs_params
++] = ctx
->i32_0
; /* DrawID */
386 vs_params
[num_vs_params
++] = vb_desc
;
388 vs_params
[(param_vertex_id
= num_vs_params
++)] = NULL
; /* VertexID */
389 vs_params
[(param_instance_id
= num_vs_params
++)] = NULL
; /* InstanceID */
390 vs_params
[num_vs_params
++] = ctx
->i32_0
; /* unused (PrimID) */
391 vs_params
[num_vs_params
++] = ctx
->i32_0
; /* unused */
393 assert(num_vs_params
<= ARRAY_SIZE(vs_params
));
394 assert(num_vs_params
== LLVMCountParamTypes(LLVMGetElementType(LLVMTypeOf(vs
))));
396 /* Load descriptors. (load 8 dwords at once) */
397 LLVMValueRef input_indexbuf
, output_indexbuf
, tmp
, desc
[8];
399 tmp
= LLVMBuildPointerCast(builder
, index_buffers_and_constants
,
400 ac_array_in_const32_addr_space(ctx
->v8i32
), "");
401 tmp
= ac_build_load_to_sgpr(&ctx
->ac
, tmp
, ctx
->i32_0
);
403 for (unsigned i
= 0; i
< 8; i
++)
404 desc
[i
] = ac_llvm_extract_elem(&ctx
->ac
, tmp
, i
);
406 input_indexbuf
= ac_build_gather_values(&ctx
->ac
, desc
, 4);
407 output_indexbuf
= ac_build_gather_values(&ctx
->ac
, desc
+ 4, 4);
409 /* Compute PrimID and InstanceID. */
410 LLVMValueRef global_thread_id
=
411 ac_build_imad(&ctx
->ac
, block_id
,
412 LLVMConstInt(ctx
->i32
, THREADGROUP_SIZE
, 0), local_id
);
413 LLVMValueRef prim_id
= global_thread_id
; /* PrimID within an instance */
414 LLVMValueRef instance_id
= ctx
->i32_0
;
416 if (key
->opt
.cs_instancing
) {
417 /* Unpack num_prims_udiv_terms. */
418 LLVMValueRef post_shift
= LLVMBuildAnd(builder
, num_prims_udiv_terms
,
419 LLVMConstInt(ctx
->i32
, 0x1f, 0), "");
420 LLVMValueRef prims_per_instance
= LLVMBuildLShr(builder
, num_prims_udiv_terms
,
421 LLVMConstInt(ctx
->i32
, 5, 0), "");
422 /* Divide the total prim_id by the number of prims per instance. */
423 instance_id
= ac_build_fast_udiv_u31_d_not_one(&ctx
->ac
, prim_id
,
424 num_prims_udiv_multiplier
,
426 /* Compute the remainder. */
427 prim_id
= LLVMBuildSub(builder
, prim_id
,
428 LLVMBuildMul(builder
, instance_id
,
429 prims_per_instance
, ""), "");
432 /* Generate indices (like a non-indexed draw call). */
433 LLVMValueRef index
[4] = {NULL
, NULL
, NULL
, LLVMGetUndef(ctx
->i32
)};
434 unsigned vertices_per_prim
= 3;
436 switch (key
->opt
.cs_prim_type
) {
437 case PIPE_PRIM_TRIANGLES
:
438 for (unsigned i
= 0; i
< 3; i
++) {
439 index
[i
] = ac_build_imad(&ctx
->ac
, prim_id
,
440 LLVMConstInt(ctx
->i32
, 3, 0),
441 LLVMConstInt(ctx
->i32
, i
, 0));
444 case PIPE_PRIM_TRIANGLE_STRIP
:
445 for (unsigned i
= 0; i
< 3; i
++) {
446 index
[i
] = LLVMBuildAdd(builder
, prim_id
,
447 LLVMConstInt(ctx
->i32
, i
, 0), "");
450 case PIPE_PRIM_TRIANGLE_FAN
:
451 /* Vertex 1 is first and vertex 2 is last. This will go to the hw clipper
452 * and rasterizer as a normal triangle, so we need to put the provoking
453 * vertex into the correct index variable and preserve orientation at the same time.
454 * gl_VertexID is preserved, because it's equal to the index.
456 if (key
->opt
.cs_provoking_vertex_first
) {
457 index
[0] = LLVMBuildAdd(builder
, prim_id
, LLVMConstInt(ctx
->i32
, 1, 0), "");
458 index
[1] = LLVMBuildAdd(builder
, prim_id
, LLVMConstInt(ctx
->i32
, 2, 0), "");
459 index
[2] = ctx
->i32_0
;
461 index
[0] = ctx
->i32_0
;
462 index
[1] = LLVMBuildAdd(builder
, prim_id
, LLVMConstInt(ctx
->i32
, 1, 0), "");
463 index
[2] = LLVMBuildAdd(builder
, prim_id
, LLVMConstInt(ctx
->i32
, 2, 0), "");
467 unreachable("unexpected primitive type");
471 if (key
->opt
.cs_indexed
) {
472 for (unsigned i
= 0; i
< 3; i
++) {
473 index
[i
] = ac_build_buffer_load_format(&ctx
->ac
, input_indexbuf
,
474 index
[i
], ctx
->i32_0
, 1,
476 index
[i
] = ac_to_integer(&ctx
->ac
, index
[i
]);
480 /* Extract the ordered wave ID. */
481 if (VERTEX_COUNTER_GDS_MODE
== 2) {
482 ordered_wave_id
= LLVMBuildLShr(builder
, ordered_wave_id
,
483 LLVMConstInt(ctx
->i32
, 6, 0), "");
484 ordered_wave_id
= LLVMBuildAnd(builder
, ordered_wave_id
,
485 LLVMConstInt(ctx
->i32
, 0xfff, 0), "");
487 LLVMValueRef thread_id
=
488 LLVMBuildAnd(builder
, local_id
, LLVMConstInt(ctx
->i32
, 63, 0), "");
490 /* Every other triangle in a strip has a reversed vertex order, so we
491 * need to swap vertices of odd primitives to get the correct primitive
492 * orientation when converting triangle strips to triangles. Primitive
493 * restart complicates it, because a strip can start anywhere.
495 LLVMValueRef prim_restart_accepted
= ctx
->i1true
;
497 if (key
->opt
.cs_prim_type
== PIPE_PRIM_TRIANGLE_STRIP
) {
498 /* Without primitive restart, odd primitives have reversed orientation.
499 * Only primitive restart can flip it with respect to the first vertex
502 LLVMValueRef first_is_odd
= ctx
->i1false
;
504 /* Handle primitive restart. */
505 if (key
->opt
.cs_primitive_restart
) {
506 /* Get the GDS primitive restart continue flag and clear
507 * the flag in vertex_counter. This flag is used when the draw
508 * call was split and we need to load the primitive orientation
509 * flag from GDS for the first wave too.
511 LLVMValueRef gds_prim_restart_continue
=
512 LLVMBuildLShr(builder
, vertex_counter
,
513 LLVMConstInt(ctx
->i32
, 31, 0), "");
514 gds_prim_restart_continue
=
515 LLVMBuildTrunc(builder
, gds_prim_restart_continue
, ctx
->i1
, "");
516 vertex_counter
= LLVMBuildAnd(builder
, vertex_counter
,
517 LLVMConstInt(ctx
->i32
, 0x7fffffff, 0), "");
519 LLVMValueRef index0_is_reset
;
521 for (unsigned i
= 0; i
< 3; i
++) {
522 LLVMValueRef not_reset
= LLVMBuildICmp(builder
, LLVMIntNE
, index
[i
],
525 index0_is_reset
= LLVMBuildNot(builder
, not_reset
, "");
526 prim_restart_accepted
= LLVMBuildAnd(builder
, prim_restart_accepted
,
530 /* If the previous waves flip the primitive orientation
531 * of the current triangle strip, it will be stored in GDS.
533 * Sometimes the correct orientation is not needed, in which case
534 * we don't need to execute this.
536 if (key
->opt
.cs_need_correct_orientation
&& VERTEX_COUNTER_GDS_MODE
== 2) {
537 /* If there are reset indices in this wave, get the thread index
538 * where the most recent strip starts relative to each thread.
540 LLVMValueRef preceding_threads_mask
=
541 LLVMBuildSub(builder
,
542 LLVMBuildShl(builder
, ctx
->ac
.i64_1
,
543 LLVMBuildZExt(builder
, thread_id
, ctx
->i64
, ""), ""),
546 LLVMValueRef reset_threadmask
= ac_get_i1_sgpr_mask(&ctx
->ac
, index0_is_reset
);
547 LLVMValueRef preceding_reset_threadmask
=
548 LLVMBuildAnd(builder
, reset_threadmask
, preceding_threads_mask
, "");
549 LLVMValueRef strip_start
=
550 ac_build_umsb(&ctx
->ac
, preceding_reset_threadmask
, NULL
);
551 strip_start
= LLVMBuildAdd(builder
, strip_start
, ctx
->i32_1
, "");
553 /* This flips the orientatino based on reset indices within this wave only. */
554 first_is_odd
= LLVMBuildTrunc(builder
, strip_start
, ctx
->i1
, "");
556 LLVMValueRef last_strip_start
, prev_wave_state
, ret
, tmp
;
557 LLVMValueRef is_first_wave
, current_wave_resets_index
;
559 /* Get the thread index where the last strip starts in this wave.
561 * If the last strip doesn't start in this wave, the thread index
564 * If the last strip starts in the next wave, the thread index will
567 last_strip_start
= ac_build_umsb(&ctx
->ac
, reset_threadmask
, NULL
);
568 last_strip_start
= LLVMBuildAdd(builder
, last_strip_start
, ctx
->i32_1
, "");
570 struct si_thread0_section section
;
571 si_enter_thread0_section(ctx
, §ion
, thread_id
);
573 /* This must be done in the thread 0 section, because
574 * we expect PrimID to be 0 for the whole first wave
575 * in this expression.
577 * NOTE: This will need to be different if we wanna support
578 * instancing with primitive restart.
580 is_first_wave
= LLVMBuildICmp(builder
, LLVMIntEQ
, prim_id
, ctx
->i32_0
, "");
581 is_first_wave
= LLVMBuildAnd(builder
, is_first_wave
,
582 LLVMBuildNot(builder
,
583 gds_prim_restart_continue
, ""), "");
584 current_wave_resets_index
= LLVMBuildICmp(builder
, LLVMIntNE
,
585 last_strip_start
, ctx
->i32_0
, "");
587 ret
= ac_build_alloca_undef(&ctx
->ac
, ctx
->i32
, "prev_state");
589 /* Save the last strip start primitive index in GDS and read
590 * the value that previous waves stored.
592 * if (is_first_wave || current_wave_resets_strip)
593 * // Read the value that previous waves stored and store a new one.
594 * first_is_odd = ds.ordered.swap(last_strip_start);
596 * // Just read the value that previous waves stored.
597 * first_is_odd = ds.ordered.add(0);
599 ac_build_ifcc(&ctx
->ac
,
600 LLVMBuildOr(builder
, is_first_wave
,
601 current_wave_resets_index
, ""), 12602);
603 /* The GDS address is always 0 with ordered append. */
604 tmp
= si_build_ds_ordered_op(ctx
, "swap",
605 ordered_wave_id
, last_strip_start
,
607 LLVMBuildStore(builder
, tmp
, ret
);
609 ac_build_else(&ctx
->ac
, 12603);
611 /* Just read the value from GDS. */
612 tmp
= si_build_ds_ordered_op(ctx
, "add",
613 ordered_wave_id
, ctx
->i32_0
,
615 LLVMBuildStore(builder
, tmp
, ret
);
617 ac_build_endif(&ctx
->ac
, 12602);
619 prev_wave_state
= LLVMBuildLoad(builder
, ret
, "");
620 /* Ignore the return value if this is the first wave. */
621 prev_wave_state
= LLVMBuildSelect(builder
, is_first_wave
,
622 ctx
->i32_0
, prev_wave_state
, "");
623 si_exit_thread0_section(§ion
, &prev_wave_state
);
624 prev_wave_state
= LLVMBuildTrunc(builder
, prev_wave_state
, ctx
->i1
, "");
626 /* If the strip start appears to be on thread 0 for the current primitive
627 * (meaning the reset index is not present in this wave and might have
628 * appeared in previous waves), use the value from GDS to determine
629 * primitive orientation.
631 * If the strip start is in this wave for the current primitive, use
632 * the value from the current wave to determine primitive orientation.
634 LLVMValueRef strip_start_is0
= LLVMBuildICmp(builder
, LLVMIntEQ
,
635 strip_start
, ctx
->i32_0
, "");
636 first_is_odd
= LLVMBuildSelect(builder
, strip_start_is0
, prev_wave_state
,
640 /* prim_is_odd = (first_is_odd + current_is_odd) % 2. */
641 LLVMValueRef prim_is_odd
=
642 LLVMBuildXor(builder
, first_is_odd
,
643 LLVMBuildTrunc(builder
, thread_id
, ctx
->i1
, ""), "");
645 /* Determine the primitive orientation.
646 * Only swap the vertices that are not the provoking vertex. We need to keep
647 * the provoking vertex in place.
649 if (key
->opt
.cs_provoking_vertex_first
) {
650 LLVMValueRef index1
= index
[1];
651 LLVMValueRef index2
= index
[2];
652 index
[1] = LLVMBuildSelect(builder
, prim_is_odd
, index2
, index1
, "");
653 index
[2] = LLVMBuildSelect(builder
, prim_is_odd
, index1
, index2
, "");
655 LLVMValueRef index0
= index
[0];
656 LLVMValueRef index1
= index
[1];
657 index
[0] = LLVMBuildSelect(builder
, prim_is_odd
, index1
, index0
, "");
658 index
[1] = LLVMBuildSelect(builder
, prim_is_odd
, index0
, index1
, "");
662 /* Execute the vertex shader for each vertex to get vertex positions. */
663 LLVMValueRef pos
[3][4];
664 for (unsigned i
= 0; i
< vertices_per_prim
; i
++) {
665 vs_params
[param_vertex_id
] = index
[i
];
666 vs_params
[param_instance_id
] = instance_id
;
668 LLVMValueRef ret
= ac_build_call(&ctx
->ac
, vs
, vs_params
, num_vs_params
);
669 for (unsigned chan
= 0; chan
< 4; chan
++)
670 pos
[i
][chan
] = LLVMBuildExtractValue(builder
, ret
, chan
, "");
673 /* Divide XYZ by W. */
674 for (unsigned i
= 0; i
< vertices_per_prim
; i
++) {
675 for (unsigned chan
= 0; chan
< 3; chan
++)
676 pos
[i
][chan
] = ac_build_fdiv(&ctx
->ac
, pos
[i
][chan
], pos
[i
][3]);
679 /* Load the viewport state. */
680 LLVMValueRef vp
= ac_build_load_invariant(&ctx
->ac
, index_buffers_and_constants
,
681 LLVMConstInt(ctx
->i32
, 2, 0));
682 vp
= LLVMBuildBitCast(builder
, vp
, ctx
->v4f32
, "");
683 vp_scale
[0] = ac_llvm_extract_elem(&ctx
->ac
, vp
, 0);
684 vp_scale
[1] = ac_llvm_extract_elem(&ctx
->ac
, vp
, 1);
685 vp_translate
[0] = ac_llvm_extract_elem(&ctx
->ac
, vp
, 2);
686 vp_translate
[1] = ac_llvm_extract_elem(&ctx
->ac
, vp
, 3);
689 struct ac_cull_options options
= {};
690 options
.cull_front
= key
->opt
.cs_cull_front
;
691 options
.cull_back
= key
->opt
.cs_cull_back
;
692 options
.cull_view_xy
= true;
693 options
.cull_view_near_z
= CULL_Z
&& key
->opt
.cs_cull_z
;
694 options
.cull_view_far_z
= CULL_Z
&& key
->opt
.cs_cull_z
;
695 options
.cull_small_prims
= true;
696 options
.cull_zero_area
= true;
697 options
.cull_w
= true;
698 options
.use_halfz_clip_space
= key
->opt
.cs_halfz_clip_space
;
700 LLVMValueRef accepted
=
701 ac_cull_triangle(&ctx
->ac
, pos
, prim_restart_accepted
,
702 vp_scale
, vp_translate
, smallprim_precision
,
705 LLVMValueRef accepted_threadmask
= ac_get_i1_sgpr_mask(&ctx
->ac
, accepted
);
707 /* Count the number of active threads by doing bitcount(accepted). */
708 LLVMValueRef num_prims_accepted
=
709 ac_build_intrinsic(&ctx
->ac
, "llvm.ctpop.i64", ctx
->i64
,
710 &accepted_threadmask
, 1, AC_FUNC_ATTR_READNONE
);
711 num_prims_accepted
= LLVMBuildTrunc(builder
, num_prims_accepted
, ctx
->i32
, "");
715 /* Execute atomic_add on the vertex count. */
716 struct si_thread0_section section
;
717 si_enter_thread0_section(ctx
, §ion
, thread_id
);
719 if (VERTEX_COUNTER_GDS_MODE
== 0) {
720 LLVMValueRef num_indices
= LLVMBuildMul(builder
, num_prims_accepted
,
721 LLVMConstInt(ctx
->i32
, vertices_per_prim
, 0), "");
722 vertex_counter
= si_expand_32bit_pointer(ctx
, vertex_counter
);
723 start
= LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpAdd
,
724 vertex_counter
, num_indices
,
725 LLVMAtomicOrderingMonotonic
, false);
726 } else if (VERTEX_COUNTER_GDS_MODE
== 1) {
727 LLVMValueRef num_indices
= LLVMBuildMul(builder
, num_prims_accepted
,
728 LLVMConstInt(ctx
->i32
, vertices_per_prim
, 0), "");
729 vertex_counter
= LLVMBuildIntToPtr(builder
, vertex_counter
,
730 LLVMPointerType(ctx
->i32
, AC_ADDR_SPACE_GDS
), "");
731 start
= LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpAdd
,
732 vertex_counter
, num_indices
,
733 LLVMAtomicOrderingMonotonic
, false);
734 } else if (VERTEX_COUNTER_GDS_MODE
== 2) {
735 LLVMValueRef tmp_store
= ac_build_alloca_undef(&ctx
->ac
, ctx
->i32
, "");
737 /* If the draw call was split into multiple subdraws, each using
738 * a separate draw packet, we need to start counting from 0 for
739 * the first compute wave of the subdraw.
741 * vertex_counter contains the primitive ID of the first thread
744 * This is only correct with VERTEX_COUNTER_GDS_MODE == 2:
746 LLVMValueRef is_first_wave
=
747 LLVMBuildICmp(builder
, LLVMIntEQ
, global_thread_id
,
750 /* Store the primitive count for ordered append, not vertex count.
751 * The idea is to avoid GDS initialization via CP DMA. The shader
752 * effectively stores the first count using "swap".
755 * ds.ordered.swap(num_prims_accepted); // store the first primitive count
758 * previous = ds.ordered.add(num_prims_accepted) // add the primitive count
761 ac_build_ifcc(&ctx
->ac
, is_first_wave
, 12604);
763 /* The GDS address is always 0 with ordered append. */
764 si_build_ds_ordered_op(ctx
, "swap", ordered_wave_id
,
765 num_prims_accepted
, 0, true, true);
766 LLVMBuildStore(builder
, ctx
->i32_0
, tmp_store
);
768 ac_build_else(&ctx
->ac
, 12605);
770 LLVMBuildStore(builder
,
771 si_build_ds_ordered_op(ctx
, "add", ordered_wave_id
,
772 num_prims_accepted
, 0,
776 ac_build_endif(&ctx
->ac
, 12604);
778 start
= LLVMBuildLoad(builder
, tmp_store
, "");
781 si_exit_thread0_section(§ion
, &start
);
783 /* Write the final vertex count to memory. An EOS/EOP event could do this,
784 * but those events are super slow and should be avoided if performance
785 * is a concern. Thanks to GDS ordered append, we can emulate a CS_DONE
788 if (VERTEX_COUNTER_GDS_MODE
== 2) {
789 ac_build_ifcc(&ctx
->ac
,
790 LLVMBuildICmp(builder
, LLVMIntEQ
, global_thread_id
,
791 last_wave_prim_id
, ""), 12606);
792 LLVMValueRef count
= LLVMBuildAdd(builder
, start
, num_prims_accepted
, "");
793 count
= LLVMBuildMul(builder
, count
,
794 LLVMConstInt(ctx
->i32
, vertices_per_prim
, 0), "");
796 /* GFX8 needs to disable caching, so that the CP can see the stored value.
797 * MTYPE=3 bypasses TC L2.
799 if (ctx
->screen
->info
.chip_class
<= GFX8
) {
800 LLVMValueRef desc
[] = {
802 LLVMConstInt(ctx
->i32
,
803 S_008F04_BASE_ADDRESS_HI(ctx
->screen
->info
.address32_hi
), 0),
804 LLVMConstInt(ctx
->i32
, 4, 0),
805 LLVMConstInt(ctx
->i32
, S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
806 S_008F0C_MTYPE(3 /* uncached */), 0),
808 LLVMValueRef rsrc
= ac_build_gather_values(&ctx
->ac
, desc
, 4);
809 ac_build_buffer_store_dword(&ctx
->ac
, rsrc
, count
, 1, ctx
->i32_0
,
810 ctx
->i32_0
, 0, ac_glc
| ac_slc
, false);
812 LLVMBuildStore(builder
, count
,
813 si_expand_32bit_pointer(ctx
, vertex_count_addr
));
815 ac_build_endif(&ctx
->ac
, 12606);
817 /* For unordered modes that increment a vertex count instead of
818 * primitive count, convert it into the primitive index.
820 start
= LLVMBuildUDiv(builder
, start
,
821 LLVMConstInt(ctx
->i32
, vertices_per_prim
, 0), "");
824 /* Now we need to store the indices of accepted primitives into
825 * the output index buffer.
827 ac_build_ifcc(&ctx
->ac
, accepted
, 16607);
829 /* Get the number of bits set before the index of this thread. */
830 LLVMValueRef prim_index
= ac_build_mbcnt(&ctx
->ac
, accepted_threadmask
);
832 /* We have lowered instancing. Pack the instance ID into vertex ID. */
833 if (key
->opt
.cs_instancing
) {
834 instance_id
= LLVMBuildShl(builder
, instance_id
,
835 LLVMConstInt(ctx
->i32
, 16, 0), "");
837 for (unsigned i
= 0; i
< vertices_per_prim
; i
++)
838 index
[i
] = LLVMBuildOr(builder
, index
[i
], instance_id
, "");
841 if (VERTEX_COUNTER_GDS_MODE
== 2) {
842 /* vertex_counter contains the first primitive ID
843 * for this dispatch. If the draw call was split into
844 * multiple subdraws, the first primitive ID is > 0
845 * for subsequent subdraws. Each subdraw uses a different
846 * portion of the output index buffer. Offset the store
847 * vindex by the first primitive ID to get the correct
848 * store address for the subdraw.
850 start
= LLVMBuildAdd(builder
, start
, vertex_counter
, "");
853 /* Write indices for accepted primitives. */
854 LLVMValueRef vindex
= LLVMBuildAdd(builder
, start
, prim_index
, "");
855 LLVMValueRef vdata
= ac_build_gather_values(&ctx
->ac
, index
, 3);
857 if (!ac_has_vec3_support(ctx
->ac
.chip_class
, true))
858 vdata
= ac_build_expand_to_vec4(&ctx
->ac
, vdata
, 3);
860 ac_build_buffer_store_format(&ctx
->ac
, output_indexbuf
, vdata
,
861 vindex
, ctx
->i32_0
, 3,
862 ac_glc
| (INDEX_STORES_USE_SLC
? ac_slc
: 0));
864 ac_build_endif(&ctx
->ac
, 16607);
866 LLVMBuildRetVoid(builder
);
869 /* Return false if the shader isn't ready. */
870 static bool si_shader_select_prim_discard_cs(struct si_context
*sctx
,
871 const struct pipe_draw_info
*info
,
872 bool primitive_restart
)
874 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
875 struct si_shader_key key
;
877 /* Primitive restart needs ordered counters. */
878 assert(!primitive_restart
|| VERTEX_COUNTER_GDS_MODE
== 2);
879 assert(!primitive_restart
|| info
->instance_count
== 1);
881 memset(&key
, 0, sizeof(key
));
882 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
, &key
, &key
.part
.vs
.prolog
);
883 assert(!key
.part
.vs
.prolog
.instance_divisor_is_fetched
);
885 key
.part
.vs
.prolog
.unpack_instance_id_from_vertex_id
= 0;
886 key
.opt
.vs_as_prim_discard_cs
= 1;
887 key
.opt
.cs_prim_type
= info
->mode
;
888 key
.opt
.cs_indexed
= info
->index_size
!= 0;
889 key
.opt
.cs_instancing
= info
->instance_count
> 1;
890 key
.opt
.cs_primitive_restart
= primitive_restart
;
891 key
.opt
.cs_provoking_vertex_first
= rs
->provoking_vertex_first
;
893 /* Primitive restart with triangle strips needs to preserve primitive
894 * orientation for cases where front and back primitive orientation matters.
896 if (primitive_restart
) {
897 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
899 key
.opt
.cs_need_correct_orientation
=
900 rs
->cull_front
!= rs
->cull_back
||
901 ps
->info
.uses_frontface
||
902 (rs
->two_side
&& ps
->info
.colors_read
);
905 if (rs
->rasterizer_discard
) {
906 /* Just for performance testing and analysis of trivial bottlenecks.
907 * This should result in a very short compute shader. */
908 key
.opt
.cs_cull_front
= 1;
909 key
.opt
.cs_cull_back
= 1;
911 key
.opt
.cs_cull_front
=
912 sctx
->viewports
.y_inverted
? rs
->cull_back
: rs
->cull_front
;
913 key
.opt
.cs_cull_back
=
914 sctx
->viewports
.y_inverted
? rs
->cull_front
: rs
->cull_back
;
917 if (!rs
->depth_clamp_any
&& CULL_Z
) {
918 key
.opt
.cs_cull_z
= 1;
919 key
.opt
.cs_halfz_clip_space
= rs
->clip_halfz
;
922 sctx
->cs_prim_discard_state
.cso
= sctx
->vs_shader
.cso
;
923 sctx
->cs_prim_discard_state
.current
= NULL
;
925 struct si_compiler_ctx_state compiler_state
;
926 compiler_state
.compiler
= &sctx
->compiler
;
927 compiler_state
.debug
= sctx
->debug
;
928 compiler_state
.is_debug_context
= sctx
->is_debug
;
930 return si_shader_select_with_key(sctx
->screen
, &sctx
->cs_prim_discard_state
,
931 &compiler_state
, &key
, -1, true) == 0 &&
932 /* Disallow compute shaders using the scratch buffer. */
933 sctx
->cs_prim_discard_state
.current
->config
.scratch_bytes_per_wave
== 0;
936 static bool si_initialize_prim_discard_cmdbuf(struct si_context
*sctx
)
938 if (sctx
->index_ring
)
941 if (!sctx
->prim_discard_compute_cs
) {
942 struct radeon_winsys
*ws
= sctx
->ws
;
943 unsigned gds_size
= VERTEX_COUNTER_GDS_MODE
== 1 ? GDS_SIZE_UNORDERED
:
944 VERTEX_COUNTER_GDS_MODE
== 2 ? 8 : 0;
945 unsigned num_oa_counters
= VERTEX_COUNTER_GDS_MODE
== 2 ? 2 : 0;
948 sctx
->gds
= ws
->buffer_create(ws
, gds_size
, 4,
949 RADEON_DOMAIN_GDS
, 0);
953 ws
->cs_add_buffer(sctx
->gfx_cs
, sctx
->gds
,
954 RADEON_USAGE_READWRITE
, 0, 0);
956 if (num_oa_counters
) {
958 sctx
->gds_oa
= ws
->buffer_create(ws
, num_oa_counters
,
959 1, RADEON_DOMAIN_OA
, 0);
963 ws
->cs_add_buffer(sctx
->gfx_cs
, sctx
->gds_oa
,
964 RADEON_USAGE_READWRITE
, 0, 0);
967 sctx
->prim_discard_compute_cs
=
968 ws
->cs_add_parallel_compute_ib(sctx
->gfx_cs
,
969 num_oa_counters
> 0);
970 if (!sctx
->prim_discard_compute_cs
)
974 if (!sctx
->index_ring
) {
976 si_aligned_buffer_create(sctx
->b
.screen
,
977 SI_RESOURCE_FLAG_UNMAPPABLE
,
979 sctx
->index_ring_size_per_ib
* 2,
981 if (!sctx
->index_ring
)
987 static bool si_check_ring_space(struct si_context
*sctx
, unsigned out_indexbuf_size
)
989 return sctx
->index_ring_offset
+
990 align(out_indexbuf_size
, sctx
->screen
->info
.tcc_cache_line_size
) <=
991 sctx
->index_ring_size_per_ib
;
994 enum si_prim_discard_outcome
995 si_prepare_prim_discard_or_split_draw(struct si_context
*sctx
,
996 const struct pipe_draw_info
*info
,
997 bool primitive_restart
)
999 /* If the compute shader compilation isn't finished, this returns false. */
1000 if (!si_shader_select_prim_discard_cs(sctx
, info
, primitive_restart
))
1001 return SI_PRIM_DISCARD_DISABLED
;
1003 if (!si_initialize_prim_discard_cmdbuf(sctx
))
1004 return SI_PRIM_DISCARD_DISABLED
;
1006 struct radeon_cmdbuf
*gfx_cs
= sctx
->gfx_cs
;
1007 unsigned prim
= info
->mode
;
1008 unsigned count
= info
->count
;
1009 unsigned instance_count
= info
->instance_count
;
1010 unsigned num_prims_per_instance
= u_decomposed_prims_for_vertices(prim
, count
);
1011 unsigned num_prims
= num_prims_per_instance
* instance_count
;
1012 unsigned out_indexbuf_size
= num_prims
* 12;
1013 bool ring_full
= !si_check_ring_space(sctx
, out_indexbuf_size
);
1014 const unsigned split_prims_draw_level
= SPLIT_PRIMS_DRAW_LEVEL
;
1016 /* Split draws at the draw call level if the ring is full. This makes
1017 * better use of the ring space.
1020 num_prims
> split_prims_draw_level
&&
1021 instance_count
== 1 && /* TODO: support splitting instanced draws */
1022 (1 << prim
) & ((1 << PIPE_PRIM_TRIANGLES
) |
1023 (1 << PIPE_PRIM_TRIANGLE_STRIP
))) {
1025 struct pipe_draw_info split_draw
= *info
;
1026 split_draw
.primitive_restart
= primitive_restart
;
1028 unsigned base_start
= split_draw
.start
;
1030 if (prim
== PIPE_PRIM_TRIANGLES
) {
1031 unsigned vert_count_per_subdraw
= split_prims_draw_level
* 3;
1032 assert(vert_count_per_subdraw
< count
);
1034 for (unsigned start
= 0; start
< count
; start
+= vert_count_per_subdraw
) {
1035 split_draw
.start
= base_start
+ start
;
1036 split_draw
.count
= MIN2(count
- start
, vert_count_per_subdraw
);
1038 sctx
->b
.draw_vbo(&sctx
->b
, &split_draw
);
1040 } else if (prim
== PIPE_PRIM_TRIANGLE_STRIP
) {
1041 /* No primitive pair can be split, because strips reverse orientation
1042 * for odd primitives. */
1043 STATIC_ASSERT(split_prims_draw_level
% 2 == 0);
1045 unsigned vert_count_per_subdraw
= split_prims_draw_level
;
1047 for (unsigned start
= 0; start
< count
- 2; start
+= vert_count_per_subdraw
) {
1048 split_draw
.start
= base_start
+ start
;
1049 split_draw
.count
= MIN2(count
- start
, vert_count_per_subdraw
+ 2);
1051 sctx
->b
.draw_vbo(&sctx
->b
, &split_draw
);
1054 primitive_restart
&&
1055 sctx
->cs_prim_discard_state
.current
->key
.opt
.cs_need_correct_orientation
)
1056 sctx
->preserve_prim_restart_gds_at_flush
= true;
1058 sctx
->preserve_prim_restart_gds_at_flush
= false;
1063 return SI_PRIM_DISCARD_DRAW_SPLIT
;
1066 /* Just quit if the draw call doesn't fit into the ring and can't be split. */
1067 if (out_indexbuf_size
> sctx
->index_ring_size_per_ib
) {
1068 if (SI_PRIM_DISCARD_DEBUG
)
1069 puts("PD failed: draw call too big, can't be split");
1070 return SI_PRIM_DISCARD_DISABLED
;
1073 unsigned num_subdraws
= DIV_ROUND_UP(num_prims
, SPLIT_PRIMS_PACKET_LEVEL
);
1074 unsigned need_compute_dw
= 11 /* shader */ + 34 /* first draw */ +
1075 24 * (num_subdraws
- 1) + /* subdraws */
1076 20; /* leave some space at the end */
1077 unsigned need_gfx_dw
= si_get_minimum_num_gfx_cs_dwords(sctx
);
1079 if (sctx
->chip_class
<= GFX7
|| FORCE_REWIND_EMULATION
)
1080 need_gfx_dw
+= 9; /* NOP(2) + WAIT_REG_MEM(7), then chain */
1082 need_gfx_dw
+= num_subdraws
* 8; /* use REWIND(2) + DRAW(6) */
1085 (VERTEX_COUNTER_GDS_MODE
== 1 && sctx
->compute_gds_offset
+ 8 > GDS_SIZE_UNORDERED
) ||
1086 !sctx
->ws
->cs_check_space(gfx_cs
, need_gfx_dw
, false)) {
1087 /* If the current IB is empty but the size is too small, add a NOP
1088 * packet to force a flush and get a bigger IB.
1090 if (!radeon_emitted(gfx_cs
, sctx
->initial_gfx_cs_size
) &&
1091 gfx_cs
->current
.cdw
+ need_gfx_dw
> gfx_cs
->current
.max_dw
) {
1092 radeon_emit(gfx_cs
, PKT3(PKT3_NOP
, 0, 0));
1093 radeon_emit(gfx_cs
, 0);
1096 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1099 /* The compute IB is always chained, but we need to call cs_check_space to add more space. */
1100 struct radeon_cmdbuf
*cs
= sctx
->prim_discard_compute_cs
;
1101 ASSERTED
bool compute_has_space
= sctx
->ws
->cs_check_space(cs
, need_compute_dw
, false);
1102 assert(compute_has_space
);
1103 assert(si_check_ring_space(sctx
, out_indexbuf_size
));
1104 return SI_PRIM_DISCARD_ENABLED
;
1107 void si_compute_signal_gfx(struct si_context
*sctx
)
1109 struct radeon_cmdbuf
*cs
= sctx
->prim_discard_compute_cs
;
1110 unsigned writeback_L2_flags
= 0;
1112 /* The writeback L2 flags vary with each chip generation. */
1113 /* CI needs to flush vertex indices to memory. */
1114 if (sctx
->chip_class
<= GFX7
)
1115 writeback_L2_flags
= EVENT_TC_WB_ACTION_ENA
;
1116 else if (sctx
->chip_class
== GFX8
&& VERTEX_COUNTER_GDS_MODE
== 0)
1117 writeback_L2_flags
= EVENT_TC_WB_ACTION_ENA
| EVENT_TC_NC_ACTION_ENA
;
1119 if (!sctx
->compute_num_prims_in_batch
)
1122 assert(sctx
->compute_rewind_va
);
1124 /* After the queued dispatches are done and vertex counts are written to
1125 * the gfx IB, signal the gfx IB to continue. CP doesn't wait for
1126 * the dispatches to finish, it only adds the CS_DONE event into the event
1129 si_cp_release_mem(sctx
, cs
, V_028A90_CS_DONE
, writeback_L2_flags
,
1130 sctx
->chip_class
<= GFX8
? EOP_DST_SEL_MEM
: EOP_DST_SEL_TC_L2
,
1131 writeback_L2_flags
? EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM
:
1133 EOP_DATA_SEL_VALUE_32BIT
,
1135 sctx
->compute_rewind_va
|
1136 ((uint64_t)sctx
->screen
->info
.address32_hi
<< 32),
1137 REWIND_SIGNAL_BIT
, /* signaling value for the REWIND packet */
1140 sctx
->compute_rewind_va
= 0;
1141 sctx
->compute_num_prims_in_batch
= 0;
1144 /* Dispatch a primitive discard compute shader. */
1145 void si_dispatch_prim_discard_cs_and_draw(struct si_context
*sctx
,
1146 const struct pipe_draw_info
*info
,
1147 unsigned index_size
,
1148 unsigned base_vertex
,
1149 uint64_t input_indexbuf_va
,
1150 unsigned input_indexbuf_num_elements
)
1152 struct radeon_cmdbuf
*gfx_cs
= sctx
->gfx_cs
;
1153 struct radeon_cmdbuf
*cs
= sctx
->prim_discard_compute_cs
;
1154 unsigned num_prims_per_instance
= u_decomposed_prims_for_vertices(info
->mode
, info
->count
);
1155 if (!num_prims_per_instance
)
1158 unsigned num_prims
= num_prims_per_instance
* info
->instance_count
;
1159 unsigned vertices_per_prim
, output_indexbuf_format
;
1161 switch (info
->mode
) {
1162 case PIPE_PRIM_TRIANGLES
:
1163 case PIPE_PRIM_TRIANGLE_STRIP
:
1164 case PIPE_PRIM_TRIANGLE_FAN
:
1165 vertices_per_prim
= 3;
1166 output_indexbuf_format
= V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1169 unreachable("unsupported primitive type");
1173 unsigned out_indexbuf_offset
;
1174 uint64_t output_indexbuf_size
= num_prims
* vertices_per_prim
* 4;
1175 bool first_dispatch
= !sctx
->prim_discard_compute_ib_initialized
;
1177 /* Initialize the compute IB if it's empty. */
1178 if (!sctx
->prim_discard_compute_ib_initialized
) {
1179 /* 1) State initialization. */
1180 sctx
->compute_gds_offset
= 0;
1181 sctx
->compute_ib_last_shader
= NULL
;
1183 if (sctx
->last_ib_barrier_fence
) {
1184 assert(!sctx
->last_ib_barrier_buf
);
1185 sctx
->ws
->cs_add_fence_dependency(gfx_cs
,
1186 sctx
->last_ib_barrier_fence
,
1187 RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY
);
1190 /* 2) IB initialization. */
1192 /* This needs to be done at the beginning of IBs due to possible
1193 * TTM buffer moves in the kernel.
1195 * TODO: update for GFX10
1197 si_emit_surface_sync(sctx
, cs
,
1198 S_0085F0_TC_ACTION_ENA(1) |
1199 S_0085F0_TCL1_ACTION_ENA(1) |
1200 S_0301F0_TC_WB_ACTION_ENA(sctx
->chip_class
>= GFX8
) |
1201 S_0085F0_SH_ICACHE_ACTION_ENA(1) |
1202 S_0085F0_SH_KCACHE_ACTION_ENA(1));
1204 /* Restore the GDS prim restart counter if needed. */
1205 if (sctx
->preserve_prim_restart_gds_at_flush
) {
1206 si_cp_copy_data(sctx
, cs
,
1207 COPY_DATA_GDS
, NULL
, 4,
1208 COPY_DATA_SRC_MEM
, sctx
->wait_mem_scratch
, 4);
1211 si_emit_initial_compute_regs(sctx
, cs
);
1213 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
1214 S_00B860_WAVES(sctx
->scratch_waves
) |
1215 S_00B860_WAVESIZE(0)); /* no scratch */
1217 /* Only 1D grids are launched. */
1218 radeon_set_sh_reg_seq(cs
, R_00B820_COMPUTE_NUM_THREAD_Y
, 2);
1219 radeon_emit(cs
, S_00B820_NUM_THREAD_FULL(1) |
1220 S_00B820_NUM_THREAD_PARTIAL(1));
1221 radeon_emit(cs
, S_00B824_NUM_THREAD_FULL(1) |
1222 S_00B824_NUM_THREAD_PARTIAL(1));
1224 radeon_set_sh_reg_seq(cs
, R_00B814_COMPUTE_START_Y
, 2);
1228 /* Disable ordered alloc for OA resources. */
1229 for (unsigned i
= 0; i
< 2; i
++) {
1230 radeon_set_uconfig_reg_seq(cs
, R_031074_GDS_OA_CNTL
, 3);
1231 radeon_emit(cs
, S_031074_INDEX(i
));
1233 radeon_emit(cs
, S_03107C_ENABLE(0));
1236 if (sctx
->last_ib_barrier_buf
) {
1237 assert(!sctx
->last_ib_barrier_fence
);
1238 radeon_add_to_buffer_list(sctx
, gfx_cs
, sctx
->last_ib_barrier_buf
,
1239 RADEON_USAGE_READ
, RADEON_PRIO_FENCE
);
1240 si_cp_wait_mem(sctx
, cs
,
1241 sctx
->last_ib_barrier_buf
->gpu_address
+
1242 sctx
->last_ib_barrier_buf_offset
, 1, 1,
1243 WAIT_REG_MEM_EQUAL
);
1246 sctx
->prim_discard_compute_ib_initialized
= true;
1249 /* Allocate the output index buffer. */
1250 output_indexbuf_size
= align(output_indexbuf_size
,
1251 sctx
->screen
->info
.tcc_cache_line_size
);
1252 assert(sctx
->index_ring_offset
+ output_indexbuf_size
<= sctx
->index_ring_size_per_ib
);
1253 out_indexbuf_offset
= sctx
->index_ring_base
+ sctx
->index_ring_offset
;
1254 sctx
->index_ring_offset
+= output_indexbuf_size
;
1256 radeon_add_to_buffer_list(sctx
, gfx_cs
, sctx
->index_ring
, RADEON_USAGE_READWRITE
,
1257 RADEON_PRIO_SHADER_RW_BUFFER
);
1258 uint64_t out_indexbuf_va
= sctx
->index_ring
->gpu_address
+ out_indexbuf_offset
;
1260 /* Prepare index buffer descriptors. */
1261 struct si_resource
*indexbuf_desc
= NULL
;
1262 unsigned indexbuf_desc_offset
;
1263 unsigned desc_size
= 12 * 4;
1266 u_upload_alloc(sctx
->b
.const_uploader
, 0, desc_size
,
1267 si_optimal_tcc_alignment(sctx
, desc_size
),
1268 &indexbuf_desc_offset
, (struct pipe_resource
**)&indexbuf_desc
,
1270 radeon_add_to_buffer_list(sctx
, gfx_cs
, indexbuf_desc
, RADEON_USAGE_READ
,
1271 RADEON_PRIO_DESCRIPTORS
);
1273 /* Input index buffer. */
1274 desc
[0] = input_indexbuf_va
;
1275 desc
[1] = S_008F04_BASE_ADDRESS_HI(input_indexbuf_va
>> 32) |
1276 S_008F04_STRIDE(index_size
);
1277 desc
[2] = input_indexbuf_num_elements
* (sctx
->chip_class
== GFX8
? index_size
: 1);
1278 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1279 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
1280 S_008F0C_DATA_FORMAT(index_size
== 1 ? V_008F0C_BUF_DATA_FORMAT_8
:
1281 index_size
== 2 ? V_008F0C_BUF_DATA_FORMAT_16
:
1282 V_008F0C_BUF_DATA_FORMAT_32
);
1284 /* Output index buffer. */
1285 desc
[4] = out_indexbuf_va
;
1286 desc
[5] = S_008F04_BASE_ADDRESS_HI(out_indexbuf_va
>> 32) |
1287 S_008F04_STRIDE(vertices_per_prim
* 4);
1288 desc
[6] = num_prims
* (sctx
->chip_class
== GFX8
? vertices_per_prim
* 4 : 1);
1289 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1290 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1291 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1292 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_0
) |
1293 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_UINT
) |
1294 S_008F0C_DATA_FORMAT(output_indexbuf_format
);
1297 * This is needed by the small primitive culling, because it's done
1300 float scale
[2], translate
[2];
1302 scale
[0] = sctx
->viewports
.states
[0].scale
[0];
1303 scale
[1] = sctx
->viewports
.states
[0].scale
[1];
1304 translate
[0] = sctx
->viewports
.states
[0].translate
[0];
1305 translate
[1] = sctx
->viewports
.states
[0].translate
[1];
1307 /* The viewport shouldn't flip the X axis for the small prim culling to work. */
1308 assert(-scale
[0] + translate
[0] <= scale
[0] + translate
[0]);
1310 /* If the Y axis is inverted (OpenGL default framebuffer), reverse it.
1311 * This is because the viewport transformation inverts the clip space
1312 * bounding box, so min becomes max, which breaks small primitive
1315 if (sctx
->viewports
.y_inverted
) {
1316 scale
[1] = -scale
[1];
1317 translate
[1] = -translate
[1];
1320 /* Scale the framebuffer up, so that samples become pixels and small
1321 * primitive culling is the same for all sample counts.
1322 * This only works with the standard DX sample positions, because
1323 * the samples are evenly spaced on both X and Y axes.
1325 unsigned num_samples
= sctx
->framebuffer
.nr_samples
;
1326 assert(num_samples
>= 1);
1328 for (unsigned i
= 0; i
< 2; i
++) {
1329 scale
[i
] *= num_samples
;
1330 translate
[i
] *= num_samples
;
1333 desc
[8] = fui(scale
[0]);
1334 desc
[9] = fui(scale
[1]);
1335 desc
[10] = fui(translate
[0]);
1336 desc
[11] = fui(translate
[1]);
1338 /* Better subpixel precision increases the efficiency of small
1339 * primitive culling. */
1340 unsigned quant_mode
= sctx
->viewports
.as_scissor
[0].quant_mode
;
1341 float small_prim_cull_precision
;
1343 if (quant_mode
== SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
)
1344 small_prim_cull_precision
= num_samples
/ 4096.0;
1345 else if (quant_mode
== SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
)
1346 small_prim_cull_precision
= num_samples
/ 1024.0;
1348 small_prim_cull_precision
= num_samples
/ 256.0;
1350 /* Set user data SGPRs. */
1351 /* This can't be greater than 14 if we want the fastest launch rate. */
1352 unsigned user_sgprs
= 13;
1354 uint64_t index_buffers_va
= indexbuf_desc
->gpu_address
+ indexbuf_desc_offset
;
1355 unsigned vs_const_desc
= si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX
);
1356 unsigned vs_sampler_desc
= si_sampler_and_image_descriptors_idx(PIPE_SHADER_VERTEX
);
1357 uint64_t vs_const_desc_va
= sctx
->descriptors
[vs_const_desc
].gpu_address
;
1358 uint64_t vs_sampler_desc_va
= sctx
->descriptors
[vs_sampler_desc
].gpu_address
;
1359 uint64_t vb_desc_va
= sctx
->vb_descriptors_buffer
?
1360 sctx
->vb_descriptors_buffer
->gpu_address
+
1361 sctx
->vb_descriptors_offset
: 0;
1362 unsigned gds_offset
, gds_size
;
1363 struct si_fast_udiv_info32 num_prims_udiv
= {};
1365 if (info
->instance_count
> 1)
1366 num_prims_udiv
= si_compute_fast_udiv_info32(num_prims_per_instance
, 31);
1368 /* Limitations on how these two are packed in the user SGPR. */
1369 assert(num_prims_udiv
.post_shift
< 32);
1370 assert(num_prims_per_instance
< 1 << 27);
1372 si_resource_reference(&indexbuf_desc
, NULL
);
1374 bool primitive_restart
= sctx
->cs_prim_discard_state
.current
->key
.opt
.cs_primitive_restart
;
1376 if (VERTEX_COUNTER_GDS_MODE
== 1) {
1377 gds_offset
= sctx
->compute_gds_offset
;
1378 gds_size
= primitive_restart
? 8 : 4;
1379 sctx
->compute_gds_offset
+= gds_size
;
1381 /* Reset the counters in GDS for the first dispatch using WRITE_DATA.
1382 * The remainder of the GDS will be cleared after the dispatch packet
1383 * in parallel with compute shaders.
1385 if (first_dispatch
) {
1386 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 2 + gds_size
/4, 0));
1387 radeon_emit(cs
, S_370_DST_SEL(V_370_GDS
) | S_370_WR_CONFIRM(1));
1388 radeon_emit(cs
, gds_offset
);
1390 radeon_emit(cs
, 0); /* value to write */
1396 /* Set shader registers. */
1397 struct si_shader
*shader
= sctx
->cs_prim_discard_state
.current
;
1399 if (shader
!= sctx
->compute_ib_last_shader
) {
1400 radeon_add_to_buffer_list(sctx
, gfx_cs
, shader
->bo
, RADEON_USAGE_READ
,
1401 RADEON_PRIO_SHADER_BINARY
);
1402 uint64_t shader_va
= shader
->bo
->gpu_address
;
1404 assert(shader
->config
.scratch_bytes_per_wave
== 0);
1405 assert(shader
->config
.num_vgprs
* WAVES_PER_TG
<= 256 * 4);
1407 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
1408 radeon_emit(cs
, shader_va
>> 8);
1409 radeon_emit(cs
, S_00B834_DATA(shader_va
>> 40));
1411 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
1412 radeon_emit(cs
, S_00B848_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1413 S_00B848_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1414 S_00B848_FLOAT_MODE(shader
->config
.float_mode
) |
1415 S_00B848_DX10_CLAMP(1));
1416 radeon_emit(cs
, S_00B84C_SCRATCH_EN(0 /* no scratch */) |
1417 S_00B84C_USER_SGPR(user_sgprs
) |
1418 S_00B84C_TGID_X_EN(1 /* only blockID.x is used */) |
1419 S_00B84C_TG_SIZE_EN(VERTEX_COUNTER_GDS_MODE
== 2 /* need the wave ID */) |
1420 S_00B84C_TIDIG_COMP_CNT(0 /* only threadID.x is used */) |
1421 S_00B84C_LDS_SIZE(shader
->config
.lds_size
));
1423 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
1424 ac_get_compute_resource_limits(&sctx
->screen
->info
,
1427 THREADGROUPS_PER_CU
));
1428 sctx
->compute_ib_last_shader
= shader
;
1431 STATIC_ASSERT(SPLIT_PRIMS_PACKET_LEVEL
% THREADGROUP_SIZE
== 0);
1433 /* Big draw calls are split into smaller dispatches and draw packets. */
1434 for (unsigned start_prim
= 0; start_prim
< num_prims
; start_prim
+= SPLIT_PRIMS_PACKET_LEVEL
) {
1435 unsigned num_subdraw_prims
;
1437 if (start_prim
+ SPLIT_PRIMS_PACKET_LEVEL
< num_prims
)
1438 num_subdraw_prims
= SPLIT_PRIMS_PACKET_LEVEL
;
1440 num_subdraw_prims
= num_prims
- start_prim
;
1442 /* Small dispatches are executed back to back until a specific primitive
1443 * count is reached. Then, a CS_DONE is inserted to signal the gfx IB
1444 * to start drawing the batch. This batching adds latency to the gfx IB,
1445 * but CS_DONE and REWIND are too slow.
1447 if (sctx
->compute_num_prims_in_batch
+ num_subdraw_prims
> PRIMS_PER_BATCH
)
1448 si_compute_signal_gfx(sctx
);
1450 if (sctx
->compute_num_prims_in_batch
== 0) {
1451 assert((gfx_cs
->gpu_address
>> 32) == sctx
->screen
->info
.address32_hi
);
1452 sctx
->compute_rewind_va
= gfx_cs
->gpu_address
+ (gfx_cs
->current
.cdw
+ 1) * 4;
1454 if (sctx
->chip_class
<= GFX7
|| FORCE_REWIND_EMULATION
) {
1455 radeon_emit(gfx_cs
, PKT3(PKT3_NOP
, 0, 0));
1456 radeon_emit(gfx_cs
, 0);
1458 si_cp_wait_mem(sctx
, gfx_cs
,
1459 sctx
->compute_rewind_va
|
1460 (uint64_t)sctx
->screen
->info
.address32_hi
<< 32,
1461 REWIND_SIGNAL_BIT
, REWIND_SIGNAL_BIT
,
1462 WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_PFP
);
1464 /* Use INDIRECT_BUFFER to chain to a different buffer
1465 * to discard the CP prefetch cache.
1467 sctx
->ws
->cs_check_space(gfx_cs
, 0, true);
1469 radeon_emit(gfx_cs
, PKT3(PKT3_REWIND
, 0, 0));
1470 radeon_emit(gfx_cs
, 0);
1474 sctx
->compute_num_prims_in_batch
+= num_subdraw_prims
;
1476 uint32_t count_va
= gfx_cs
->gpu_address
+ (gfx_cs
->current
.cdw
+ 4) * 4;
1477 uint64_t index_va
= out_indexbuf_va
+ start_prim
* 12;
1479 /* Emit the draw packet into the gfx IB. */
1480 radeon_emit(gfx_cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, 0));
1481 radeon_emit(gfx_cs
, num_prims
* vertices_per_prim
);
1482 radeon_emit(gfx_cs
, index_va
);
1483 radeon_emit(gfx_cs
, index_va
>> 32);
1484 radeon_emit(gfx_cs
, 0);
1485 radeon_emit(gfx_cs
, V_0287F0_DI_SRC_SEL_DMA
);
1487 /* Continue with the compute IB. */
1488 if (start_prim
== 0) {
1489 uint32_t gds_prim_restart_continue_bit
= 0;
1491 if (sctx
->preserve_prim_restart_gds_at_flush
) {
1492 assert(primitive_restart
&&
1493 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP
);
1494 assert(start_prim
< 1 << 31);
1495 gds_prim_restart_continue_bit
= 1 << 31;
1498 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, user_sgprs
);
1499 radeon_emit(cs
, index_buffers_va
);
1501 VERTEX_COUNTER_GDS_MODE
== 0 ? count_va
:
1502 VERTEX_COUNTER_GDS_MODE
== 1 ? gds_offset
:
1504 gds_prim_restart_continue_bit
);
1505 radeon_emit(cs
, start_prim
+ num_subdraw_prims
- 1);
1506 radeon_emit(cs
, count_va
);
1507 radeon_emit(cs
, vb_desc_va
);
1508 radeon_emit(cs
, vs_const_desc_va
);
1509 radeon_emit(cs
, vs_sampler_desc_va
);
1510 radeon_emit(cs
, base_vertex
);
1511 radeon_emit(cs
, info
->start_instance
);
1512 radeon_emit(cs
, num_prims_udiv
.multiplier
);
1513 radeon_emit(cs
, num_prims_udiv
.post_shift
|
1514 (num_prims_per_instance
<< 5));
1515 radeon_emit(cs
, info
->restart_index
);
1516 /* small-prim culling precision (same as rasterizer precision = QUANT_MODE) */
1517 radeon_emit(cs
, fui(small_prim_cull_precision
));
1519 assert(VERTEX_COUNTER_GDS_MODE
== 2);
1520 /* Only update the SGPRs that changed. */
1521 radeon_set_sh_reg_seq(cs
, R_00B904_COMPUTE_USER_DATA_1
, 3);
1522 radeon_emit(cs
, start_prim
);
1523 radeon_emit(cs
, start_prim
+ num_subdraw_prims
- 1);
1524 radeon_emit(cs
, count_va
);
1527 /* Set grid dimensions. */
1528 unsigned start_block
= start_prim
/ THREADGROUP_SIZE
;
1529 unsigned num_full_blocks
= num_subdraw_prims
/ THREADGROUP_SIZE
;
1530 unsigned partial_block_size
= num_subdraw_prims
% THREADGROUP_SIZE
;
1532 radeon_set_sh_reg(cs
, R_00B810_COMPUTE_START_X
, start_block
);
1533 radeon_set_sh_reg(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
,
1534 S_00B81C_NUM_THREAD_FULL(THREADGROUP_SIZE
) |
1535 S_00B81C_NUM_THREAD_PARTIAL(partial_block_size
));
1537 radeon_emit(cs
, PKT3(PKT3_DISPATCH_DIRECT
, 3, 0) |
1538 PKT3_SHADER_TYPE_S(1));
1539 radeon_emit(cs
, start_block
+ num_full_blocks
+ !!partial_block_size
);
1542 radeon_emit(cs
, S_00B800_COMPUTE_SHADER_EN(1) |
1543 S_00B800_PARTIAL_TG_EN(!!partial_block_size
) |
1544 S_00B800_ORDERED_APPEND_ENBL(VERTEX_COUNTER_GDS_MODE
== 2) |
1545 S_00B800_ORDER_MODE(0 /* launch in order */));
1547 /* This is only for unordered append. Ordered append writes this from
1550 * Note that EOP and EOS events are super slow, so emulating the event
1551 * in a shader is an important optimization.
1553 if (VERTEX_COUNTER_GDS_MODE
== 1) {
1554 si_cp_release_mem(sctx
, cs
, V_028A90_CS_DONE
, 0,
1555 sctx
->chip_class
<= GFX8
? EOP_DST_SEL_MEM
: EOP_DST_SEL_TC_L2
,
1559 count_va
| ((uint64_t)sctx
->screen
->info
.address32_hi
<< 32),
1560 EOP_DATA_GDS(gds_offset
/ 4, 1),
1563 /* Now that compute shaders are running, clear the remainder of GDS. */
1564 if (first_dispatch
) {
1565 unsigned offset
= gds_offset
+ gds_size
;
1566 si_cp_dma_clear_buffer(sctx
, cs
, NULL
, offset
,
1567 GDS_SIZE_UNORDERED
- offset
,
1569 SI_CPDMA_SKIP_CHECK_CS_SPACE
|
1570 SI_CPDMA_SKIP_GFX_SYNC
|
1571 SI_CPDMA_SKIP_SYNC_BEFORE
,
1572 SI_COHERENCY_NONE
, L2_BYPASS
);
1575 first_dispatch
= false;
1577 assert(cs
->current
.cdw
<= cs
->current
.max_dw
);
1578 assert(gfx_cs
->current
.cdw
<= gfx_cs
->current
.max_dw
);