2 * Copyright 2015 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "si_compute.h"
28 #include "sid_tables.h"
29 #include "tgsi/tgsi_from_mesa.h"
30 #include "driver_ddebug/dd_util.h"
31 #include "util/u_dump.h"
32 #include "util/u_log.h"
33 #include "util/u_memory.h"
34 #include "util/u_string.h"
38 static void si_dump_bo_list(struct si_context
*sctx
,
39 const struct radeon_saved_cs
*saved
, FILE *f
);
41 DEBUG_GET_ONCE_OPTION(replace_shaders
, "RADEON_REPLACE_SHADERS", NULL
)
44 * Store a linearized copy of all chunks of \p cs together with the buffer
47 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
48 struct radeon_saved_cs
*saved
, bool get_buffer_list
)
53 /* Save the IB chunks. */
54 saved
->num_dw
= cs
->prev_dw
+ cs
->current
.cdw
;
55 saved
->ib
= MALLOC(4 * saved
->num_dw
);
60 for (i
= 0; i
< cs
->num_prev
; ++i
) {
61 memcpy(buf
, cs
->prev
[i
].buf
, cs
->prev
[i
].cdw
* 4);
62 buf
+= cs
->prev
[i
].cdw
;
64 memcpy(buf
, cs
->current
.buf
, cs
->current
.cdw
* 4);
69 /* Save the buffer list. */
70 saved
->bo_count
= ws
->cs_get_buffer_list(cs
, NULL
);
71 saved
->bo_list
= CALLOC(saved
->bo_count
,
72 sizeof(saved
->bo_list
[0]));
73 if (!saved
->bo_list
) {
77 ws
->cs_get_buffer_list(cs
, saved
->bo_list
);
82 fprintf(stderr
, "%s: out of memory\n", __func__
);
83 memset(saved
, 0, sizeof(*saved
));
86 void si_clear_saved_cs(struct radeon_saved_cs
*saved
)
91 memset(saved
, 0, sizeof(*saved
));
94 void si_destroy_saved_cs(struct si_saved_cs
*scs
)
96 si_clear_saved_cs(&scs
->gfx
);
97 si_resource_reference(&scs
->trace_buf
, NULL
);
101 static void si_dump_shader(struct si_screen
*sscreen
,
102 struct si_shader
*shader
, FILE *f
)
104 if (shader
->shader_log
)
105 fwrite(shader
->shader_log
, shader
->shader_log_size
, 1, f
);
107 si_shader_dump(sscreen
, shader
, NULL
, f
, false);
109 if (shader
->bo
&& sscreen
->options
.dump_shader_binary
) {
110 unsigned size
= shader
->bo
->b
.b
.width0
;
111 fprintf(f
, "BO: VA=%"PRIx64
" Size=%u\n", shader
->bo
->gpu_address
, size
);
113 const char *mapped
= sscreen
->ws
->buffer_map(shader
->bo
->buf
, NULL
,
114 PIPE_TRANSFER_UNSYNCHRONIZED
|
116 RADEON_TRANSFER_TEMPORARY
);
118 for (unsigned i
= 0; i
< size
; i
+= 4) {
119 fprintf(f
, " %4x: %08x\n", i
, *(uint32_t*)(mapped
+ i
));
122 sscreen
->ws
->buffer_unmap(shader
->bo
->buf
);
128 struct si_log_chunk_shader
{
129 /* The shader destroy code assumes a current context for unlinking of
132 * While we should be able to destroy shaders without a context, doing
133 * so would happen only very rarely and be therefore likely to fail
134 * just when you're trying to debug something. Let's just remember the
135 * current context in the chunk.
137 struct si_context
*ctx
;
138 struct si_shader
*shader
;
140 /* For keep-alive reference counts */
141 struct si_shader_selector
*sel
;
142 struct si_compute
*program
;
146 si_log_chunk_shader_destroy(void *data
)
148 struct si_log_chunk_shader
*chunk
= data
;
149 si_shader_selector_reference(chunk
->ctx
, &chunk
->sel
, NULL
);
150 si_compute_reference(&chunk
->program
, NULL
);
155 si_log_chunk_shader_print(void *data
, FILE *f
)
157 struct si_log_chunk_shader
*chunk
= data
;
158 struct si_screen
*sscreen
= chunk
->ctx
->screen
;
159 si_dump_shader(sscreen
, chunk
->shader
, f
);
162 static struct u_log_chunk_type si_log_chunk_type_shader
= {
163 .destroy
= si_log_chunk_shader_destroy
,
164 .print
= si_log_chunk_shader_print
,
167 static void si_dump_gfx_shader(struct si_context
*ctx
,
168 const struct si_shader_ctx_state
*state
,
169 struct u_log_context
*log
)
171 struct si_shader
*current
= state
->current
;
173 if (!state
->cso
|| !current
)
176 struct si_log_chunk_shader
*chunk
= CALLOC_STRUCT(si_log_chunk_shader
);
178 chunk
->shader
= current
;
179 si_shader_selector_reference(ctx
, &chunk
->sel
, current
->selector
);
180 u_log_chunk(log
, &si_log_chunk_type_shader
, chunk
);
183 static void si_dump_compute_shader(struct si_context
*ctx
,
184 struct u_log_context
*log
)
186 const struct si_cs_shader_state
*state
= &ctx
->cs_shader_state
;
191 struct si_log_chunk_shader
*chunk
= CALLOC_STRUCT(si_log_chunk_shader
);
193 chunk
->shader
= &state
->program
->shader
;
194 si_compute_reference(&chunk
->program
, state
->program
);
195 u_log_chunk(log
, &si_log_chunk_type_shader
, chunk
);
199 * Shader compiles can be overridden with arbitrary ELF objects by setting
200 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
202 * TODO: key this off some hash
204 bool si_replace_shader(unsigned num
, struct si_shader_binary
*binary
)
206 const char *p
= debug_get_option_replace_shaders();
207 const char *semicolon
;
210 long filesize
, nread
;
211 bool replaced
= false;
219 i
= strtoul(p
, &endp
, 0);
223 fprintf(stderr
, "RADEON_REPLACE_SHADERS formatted badly.\n");
239 semicolon
= strchr(p
, ';');
241 p
= copy
= strndup(p
, semicolon
- p
);
243 fprintf(stderr
, "out of memory\n");
248 fprintf(stderr
, "radeonsi: replace shader %u by %s\n", num
, p
);
252 perror("radeonsi: failed to open file");
256 if (fseek(f
, 0, SEEK_END
) != 0)
263 if (fseek(f
, 0, SEEK_SET
) != 0)
266 binary
->elf_buffer
= MALLOC(filesize
);
267 if (!binary
->elf_buffer
) {
268 fprintf(stderr
, "out of memory\n");
272 nread
= fread((void*)binary
->elf_buffer
, 1, filesize
, f
);
273 if (nread
!= filesize
) {
274 FREE((void*)binary
->elf_buffer
);
275 binary
->elf_buffer
= NULL
;
279 binary
->elf_size
= nread
;
289 perror("radeonsi: reading shader");
293 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
294 * read them, or use "aha -b -f file" to convert them to html.
296 #define COLOR_RESET "\033[0m"
297 #define COLOR_RED "\033[31m"
298 #define COLOR_GREEN "\033[1;32m"
299 #define COLOR_YELLOW "\033[1;33m"
300 #define COLOR_CYAN "\033[1;36m"
302 static void si_dump_mmapped_reg(struct si_context
*sctx
, FILE *f
,
305 struct radeon_winsys
*ws
= sctx
->ws
;
308 if (ws
->read_registers(ws
, offset
, 1, &value
))
309 ac_dump_reg(f
, sctx
->chip_class
, offset
, value
, ~0);
312 static void si_dump_debug_registers(struct si_context
*sctx
, FILE *f
)
314 if (!sctx
->screen
->info
.has_read_registers_query
)
317 fprintf(f
, "Memory-mapped registers:\n");
318 si_dump_mmapped_reg(sctx
, f
, R_008010_GRBM_STATUS
);
320 /* No other registers can be read on DRM < 3.1.0. */
321 if (!sctx
->screen
->info
.is_amdgpu
||
322 sctx
->screen
->info
.drm_minor
< 1) {
327 si_dump_mmapped_reg(sctx
, f
, R_008008_GRBM_STATUS2
);
328 si_dump_mmapped_reg(sctx
, f
, R_008014_GRBM_STATUS_SE0
);
329 si_dump_mmapped_reg(sctx
, f
, R_008018_GRBM_STATUS_SE1
);
330 si_dump_mmapped_reg(sctx
, f
, R_008038_GRBM_STATUS_SE2
);
331 si_dump_mmapped_reg(sctx
, f
, R_00803C_GRBM_STATUS_SE3
);
332 si_dump_mmapped_reg(sctx
, f
, R_00D034_SDMA0_STATUS_REG
);
333 si_dump_mmapped_reg(sctx
, f
, R_00D834_SDMA1_STATUS_REG
);
334 if (sctx
->chip_class
<= GFX8
) {
335 si_dump_mmapped_reg(sctx
, f
, R_000E50_SRBM_STATUS
);
336 si_dump_mmapped_reg(sctx
, f
, R_000E4C_SRBM_STATUS2
);
337 si_dump_mmapped_reg(sctx
, f
, R_000E54_SRBM_STATUS3
);
339 si_dump_mmapped_reg(sctx
, f
, R_008680_CP_STAT
);
340 si_dump_mmapped_reg(sctx
, f
, R_008674_CP_STALLED_STAT1
);
341 si_dump_mmapped_reg(sctx
, f
, R_008678_CP_STALLED_STAT2
);
342 si_dump_mmapped_reg(sctx
, f
, R_008670_CP_STALLED_STAT3
);
343 si_dump_mmapped_reg(sctx
, f
, R_008210_CP_CPC_STATUS
);
344 si_dump_mmapped_reg(sctx
, f
, R_008214_CP_CPC_BUSY_STAT
);
345 si_dump_mmapped_reg(sctx
, f
, R_008218_CP_CPC_STALLED_STAT1
);
346 si_dump_mmapped_reg(sctx
, f
, R_00821C_CP_CPF_STATUS
);
347 si_dump_mmapped_reg(sctx
, f
, R_008220_CP_CPF_BUSY_STAT
);
348 si_dump_mmapped_reg(sctx
, f
, R_008224_CP_CPF_STALLED_STAT1
);
352 struct si_log_chunk_cs
{
353 struct si_context
*ctx
;
354 struct si_saved_cs
*cs
;
356 unsigned gfx_begin
, gfx_end
;
357 unsigned compute_begin
, compute_end
;
360 static void si_log_chunk_type_cs_destroy(void *data
)
362 struct si_log_chunk_cs
*chunk
= data
;
363 si_saved_cs_reference(&chunk
->cs
, NULL
);
367 static void si_parse_current_ib(FILE *f
, struct radeon_cmdbuf
*cs
,
368 unsigned begin
, unsigned end
,
369 int *last_trace_id
, unsigned trace_id_count
,
370 const char *name
, enum chip_class chip_class
)
372 unsigned orig_end
= end
;
374 assert(begin
<= end
);
376 fprintf(f
, "------------------ %s begin (dw = %u) ------------------\n",
379 for (unsigned prev_idx
= 0; prev_idx
< cs
->num_prev
; ++prev_idx
) {
380 struct radeon_cmdbuf_chunk
*chunk
= &cs
->prev
[prev_idx
];
382 if (begin
< chunk
->cdw
) {
383 ac_parse_ib_chunk(f
, chunk
->buf
+ begin
,
384 MIN2(end
, chunk
->cdw
) - begin
,
385 last_trace_id
, trace_id_count
,
386 chip_class
, NULL
, NULL
);
389 if (end
<= chunk
->cdw
)
392 if (begin
< chunk
->cdw
)
393 fprintf(f
, "\n---------- Next %s Chunk ----------\n\n",
396 begin
-= MIN2(begin
, chunk
->cdw
);
400 assert(end
<= cs
->current
.cdw
);
402 ac_parse_ib_chunk(f
, cs
->current
.buf
+ begin
, end
- begin
, last_trace_id
,
403 trace_id_count
, chip_class
, NULL
, NULL
);
405 fprintf(f
, "------------------- %s end (dw = %u) -------------------\n\n",
409 static void si_log_chunk_type_cs_print(void *data
, FILE *f
)
411 struct si_log_chunk_cs
*chunk
= data
;
412 struct si_context
*ctx
= chunk
->ctx
;
413 struct si_saved_cs
*scs
= chunk
->cs
;
414 int last_trace_id
= -1;
415 int last_compute_trace_id
= -1;
417 /* We are expecting that the ddebug pipe has already
418 * waited for the context, so this buffer should be idle.
419 * If the GPU is hung, there is no point in waiting for it.
421 uint32_t *map
= ctx
->ws
->buffer_map(scs
->trace_buf
->buf
,
423 PIPE_TRANSFER_UNSYNCHRONIZED
|
426 last_trace_id
= map
[0];
427 last_compute_trace_id
= map
[1];
430 if (chunk
->gfx_end
!= chunk
->gfx_begin
) {
431 if (chunk
->gfx_begin
== 0) {
432 if (ctx
->init_config
)
433 ac_parse_ib(f
, ctx
->init_config
->pm4
, ctx
->init_config
->ndw
,
434 NULL
, 0, "IB2: Init config", ctx
->chip_class
,
437 if (ctx
->init_config_gs_rings
)
438 ac_parse_ib(f
, ctx
->init_config_gs_rings
->pm4
,
439 ctx
->init_config_gs_rings
->ndw
,
440 NULL
, 0, "IB2: Init GS rings", ctx
->chip_class
,
445 ac_parse_ib(f
, scs
->gfx
.ib
+ chunk
->gfx_begin
,
446 chunk
->gfx_end
- chunk
->gfx_begin
,
447 &last_trace_id
, map
? 1 : 0, "IB", ctx
->chip_class
,
450 si_parse_current_ib(f
, ctx
->gfx_cs
, chunk
->gfx_begin
,
451 chunk
->gfx_end
, &last_trace_id
, map
? 1 : 0,
452 "IB", ctx
->chip_class
);
456 if (chunk
->compute_end
!= chunk
->compute_begin
) {
457 assert(ctx
->prim_discard_compute_cs
);
460 ac_parse_ib(f
, scs
->compute
.ib
+ chunk
->compute_begin
,
461 chunk
->compute_end
- chunk
->compute_begin
,
462 &last_compute_trace_id
, map
? 1 : 0, "Compute IB", ctx
->chip_class
,
465 si_parse_current_ib(f
, ctx
->prim_discard_compute_cs
, chunk
->compute_begin
,
466 chunk
->compute_end
, &last_compute_trace_id
,
467 map
? 1 : 0, "Compute IB", ctx
->chip_class
);
471 if (chunk
->dump_bo_list
) {
472 fprintf(f
, "Flushing. Time: ");
473 util_dump_ns(f
, scs
->time_flush
);
475 si_dump_bo_list(ctx
, &scs
->gfx
, f
);
479 static const struct u_log_chunk_type si_log_chunk_type_cs
= {
480 .destroy
= si_log_chunk_type_cs_destroy
,
481 .print
= si_log_chunk_type_cs_print
,
484 static void si_log_cs(struct si_context
*ctx
, struct u_log_context
*log
,
487 assert(ctx
->current_saved_cs
);
489 struct si_saved_cs
*scs
= ctx
->current_saved_cs
;
490 unsigned gfx_cur
= ctx
->gfx_cs
->prev_dw
+ ctx
->gfx_cs
->current
.cdw
;
491 unsigned compute_cur
= 0;
493 if (ctx
->prim_discard_compute_cs
)
494 compute_cur
= ctx
->prim_discard_compute_cs
->prev_dw
+ ctx
->prim_discard_compute_cs
->current
.cdw
;
497 gfx_cur
== scs
->gfx_last_dw
&&
498 compute_cur
== scs
->compute_last_dw
)
501 struct si_log_chunk_cs
*chunk
= calloc(1, sizeof(*chunk
));
504 si_saved_cs_reference(&chunk
->cs
, scs
);
505 chunk
->dump_bo_list
= dump_bo_list
;
507 chunk
->gfx_begin
= scs
->gfx_last_dw
;
508 chunk
->gfx_end
= gfx_cur
;
509 scs
->gfx_last_dw
= gfx_cur
;
511 chunk
->compute_begin
= scs
->compute_last_dw
;
512 chunk
->compute_end
= compute_cur
;
513 scs
->compute_last_dw
= compute_cur
;
515 u_log_chunk(log
, &si_log_chunk_type_cs
, chunk
);
518 void si_auto_log_cs(void *data
, struct u_log_context
*log
)
520 struct si_context
*ctx
= (struct si_context
*)data
;
521 si_log_cs(ctx
, log
, false);
524 void si_log_hw_flush(struct si_context
*sctx
)
529 si_log_cs(sctx
, sctx
->log
, true);
531 if (&sctx
->b
== sctx
->screen
->aux_context
) {
532 /* The aux context isn't captured by the ddebug wrapper,
533 * so we dump it on a flush-by-flush basis here.
535 FILE *f
= dd_get_debug_file(false);
537 fprintf(stderr
, "radeonsi: error opening aux context dump file.\n");
539 dd_write_header(f
, &sctx
->screen
->b
, 0);
541 fprintf(f
, "Aux context dump:\n\n");
542 u_log_new_page_print(sctx
->log
, f
);
549 static const char *priority_to_string(enum radeon_bo_priority priority
)
551 #define ITEM(x) [RADEON_PRIO_##x] = #x
552 static const char *table
[64] = {
555 ITEM(SO_FILLED_SIZE
),
565 ITEM(SAMPLER_BUFFER
),
567 ITEM(SHADER_RW_BUFFER
),
568 ITEM(COMPUTE_GLOBAL
),
569 ITEM(SAMPLER_TEXTURE
),
570 ITEM(SHADER_RW_IMAGE
),
571 ITEM(SAMPLER_TEXTURE_MSAA
),
574 ITEM(COLOR_BUFFER_MSAA
),
575 ITEM(DEPTH_BUFFER_MSAA
),
579 ITEM(SCRATCH_BUFFER
),
583 assert(priority
< ARRAY_SIZE(table
));
584 return table
[priority
];
587 static int bo_list_compare_va(const struct radeon_bo_list_item
*a
,
588 const struct radeon_bo_list_item
*b
)
590 return a
->vm_address
< b
->vm_address
? -1 :
591 a
->vm_address
> b
->vm_address
? 1 : 0;
594 static void si_dump_bo_list(struct si_context
*sctx
,
595 const struct radeon_saved_cs
*saved
, FILE *f
)
602 /* Sort the list according to VM adddresses first. */
603 qsort(saved
->bo_list
, saved
->bo_count
,
604 sizeof(saved
->bo_list
[0]), (void*)bo_list_compare_va
);
606 fprintf(f
, "Buffer list (in units of pages = 4kB):\n"
607 COLOR_YELLOW
" Size VM start page "
608 "VM end page Usage" COLOR_RESET
"\n");
610 for (i
= 0; i
< saved
->bo_count
; i
++) {
611 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
612 const unsigned page_size
= sctx
->screen
->info
.gart_page_size
;
613 uint64_t va
= saved
->bo_list
[i
].vm_address
;
614 uint64_t size
= saved
->bo_list
[i
].bo_size
;
617 /* If there's unused virtual memory between 2 buffers, print it. */
619 uint64_t previous_va_end
= saved
->bo_list
[i
-1].vm_address
+
620 saved
->bo_list
[i
-1].bo_size
;
622 if (va
> previous_va_end
) {
623 fprintf(f
, " %10"PRIu64
" -- hole --\n",
624 (va
- previous_va_end
) / page_size
);
628 /* Print the buffer. */
629 fprintf(f
, " %10"PRIu64
" 0x%013"PRIX64
" 0x%013"PRIX64
" ",
630 size
/ page_size
, va
/ page_size
, (va
+ size
) / page_size
);
632 /* Print the usage. */
633 for (j
= 0; j
< 32; j
++) {
634 if (!(saved
->bo_list
[i
].priority_usage
& (1u << j
)))
637 fprintf(f
, "%s%s", !hit
? "" : ", ", priority_to_string(j
));
642 fprintf(f
, "\nNote: The holes represent memory not used by the IB.\n"
643 " Other buffers can still be allocated there.\n\n");
646 static void si_dump_framebuffer(struct si_context
*sctx
, struct u_log_context
*log
)
648 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
649 struct si_texture
*tex
;
652 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
653 if (!state
->cbufs
[i
])
656 tex
= (struct si_texture
*)state
->cbufs
[i
]->texture
;
657 u_log_printf(log
, COLOR_YELLOW
"Color buffer %i:" COLOR_RESET
"\n", i
);
658 si_print_texture_info(sctx
->screen
, tex
, log
);
659 u_log_printf(log
, "\n");
663 tex
= (struct si_texture
*)state
->zsbuf
->texture
;
664 u_log_printf(log
, COLOR_YELLOW
"Depth-stencil buffer:" COLOR_RESET
"\n");
665 si_print_texture_info(sctx
->screen
, tex
, log
);
666 u_log_printf(log
, "\n");
670 typedef unsigned (*slot_remap_func
)(unsigned);
672 struct si_log_chunk_desc_list
{
673 /** Pointer to memory map of buffer where the list is uploader */
675 /** Reference of buffer where the list is uploaded, so that gpu_list
677 struct si_resource
*buf
;
679 const char *shader_name
;
680 const char *elem_name
;
681 slot_remap_func slot_remap
;
682 enum chip_class chip_class
;
683 unsigned element_dw_size
;
684 unsigned num_elements
;
690 si_log_chunk_desc_list_destroy(void *data
)
692 struct si_log_chunk_desc_list
*chunk
= data
;
693 si_resource_reference(&chunk
->buf
, NULL
);
698 si_log_chunk_desc_list_print(void *data
, FILE *f
)
700 struct si_log_chunk_desc_list
*chunk
= data
;
701 unsigned sq_img_rsrc_word0
= chunk
->chip_class
>= GFX10
? R_00A000_SQ_IMG_RSRC_WORD0
702 : R_008F10_SQ_IMG_RSRC_WORD0
;
704 for (unsigned i
= 0; i
< chunk
->num_elements
; i
++) {
705 unsigned cpu_dw_offset
= i
* chunk
->element_dw_size
;
706 unsigned gpu_dw_offset
= chunk
->slot_remap(i
) * chunk
->element_dw_size
;
707 const char *list_note
= chunk
->gpu_list
? "GPU list" : "CPU list";
708 uint32_t *cpu_list
= chunk
->list
+ cpu_dw_offset
;
709 uint32_t *gpu_list
= chunk
->gpu_list
? chunk
->gpu_list
+ gpu_dw_offset
: cpu_list
;
711 fprintf(f
, COLOR_GREEN
"%s%s slot %u (%s):" COLOR_RESET
"\n",
712 chunk
->shader_name
, chunk
->elem_name
, i
, list_note
);
714 switch (chunk
->element_dw_size
) {
716 for (unsigned j
= 0; j
< 4; j
++)
717 ac_dump_reg(f
, chunk
->chip_class
,
718 R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
719 gpu_list
[j
], 0xffffffff);
722 for (unsigned j
= 0; j
< 8; j
++)
723 ac_dump_reg(f
, chunk
->chip_class
,
724 sq_img_rsrc_word0
+ j
*4,
725 gpu_list
[j
], 0xffffffff);
727 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
728 for (unsigned j
= 0; j
< 4; j
++)
729 ac_dump_reg(f
, chunk
->chip_class
,
730 R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
731 gpu_list
[4+j
], 0xffffffff);
734 for (unsigned j
= 0; j
< 8; j
++)
735 ac_dump_reg(f
, chunk
->chip_class
,
736 sq_img_rsrc_word0
+ j
*4,
737 gpu_list
[j
], 0xffffffff);
739 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
740 for (unsigned j
= 0; j
< 4; j
++)
741 ac_dump_reg(f
, chunk
->chip_class
,
742 R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
743 gpu_list
[4+j
], 0xffffffff);
745 fprintf(f
, COLOR_CYAN
" FMASK:" COLOR_RESET
"\n");
746 for (unsigned j
= 0; j
< 8; j
++)
747 ac_dump_reg(f
, chunk
->chip_class
,
748 sq_img_rsrc_word0
+ j
*4,
749 gpu_list
[8+j
], 0xffffffff);
751 fprintf(f
, COLOR_CYAN
" Sampler state:" COLOR_RESET
"\n");
752 for (unsigned j
= 0; j
< 4; j
++)
753 ac_dump_reg(f
, chunk
->chip_class
,
754 R_008F30_SQ_IMG_SAMP_WORD0
+ j
*4,
755 gpu_list
[12+j
], 0xffffffff);
759 if (memcmp(gpu_list
, cpu_list
, chunk
->element_dw_size
* 4) != 0) {
760 fprintf(f
, COLOR_RED
"!!!!! This slot was corrupted in GPU memory !!!!!"
769 static const struct u_log_chunk_type si_log_chunk_type_descriptor_list
= {
770 .destroy
= si_log_chunk_desc_list_destroy
,
771 .print
= si_log_chunk_desc_list_print
,
774 static void si_dump_descriptor_list(struct si_screen
*screen
,
775 struct si_descriptors
*desc
,
776 const char *shader_name
,
777 const char *elem_name
,
778 unsigned element_dw_size
,
779 unsigned num_elements
,
780 slot_remap_func slot_remap
,
781 struct u_log_context
*log
)
786 /* In some cases, the caller doesn't know how many elements are really
787 * uploaded. Reduce num_elements to fit in the range of active slots. */
788 unsigned active_range_dw_begin
=
789 desc
->first_active_slot
* desc
->element_dw_size
;
790 unsigned active_range_dw_end
=
791 active_range_dw_begin
+ desc
->num_active_slots
* desc
->element_dw_size
;
793 while (num_elements
> 0) {
794 int i
= slot_remap(num_elements
- 1);
795 unsigned dw_begin
= i
* element_dw_size
;
796 unsigned dw_end
= dw_begin
+ element_dw_size
;
798 if (dw_begin
>= active_range_dw_begin
&& dw_end
<= active_range_dw_end
)
804 struct si_log_chunk_desc_list
*chunk
=
805 CALLOC_VARIANT_LENGTH_STRUCT(si_log_chunk_desc_list
,
806 4 * element_dw_size
* num_elements
);
807 chunk
->shader_name
= shader_name
;
808 chunk
->elem_name
= elem_name
;
809 chunk
->element_dw_size
= element_dw_size
;
810 chunk
->num_elements
= num_elements
;
811 chunk
->slot_remap
= slot_remap
;
812 chunk
->chip_class
= screen
->info
.chip_class
;
814 si_resource_reference(&chunk
->buf
, desc
->buffer
);
815 chunk
->gpu_list
= desc
->gpu_list
;
817 for (unsigned i
= 0; i
< num_elements
; ++i
) {
818 memcpy(&chunk
->list
[i
* element_dw_size
],
819 &desc
->list
[slot_remap(i
) * element_dw_size
],
820 4 * element_dw_size
);
823 u_log_chunk(log
, &si_log_chunk_type_descriptor_list
, chunk
);
826 static unsigned si_identity(unsigned slot
)
831 static void si_dump_descriptors(struct si_context
*sctx
,
832 enum pipe_shader_type processor
,
833 const struct si_shader_info
*info
,
834 struct u_log_context
*log
)
836 struct si_descriptors
*descs
=
837 &sctx
->descriptors
[SI_DESCS_FIRST_SHADER
+
838 processor
* SI_NUM_SHADER_DESCS
];
839 static const char *shader_name
[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
840 const char *name
= shader_name
[processor
];
841 unsigned enabled_constbuf
, enabled_shaderbuf
, enabled_samplers
;
842 unsigned enabled_images
;
845 enabled_constbuf
= info
->const_buffers_declared
;
846 enabled_shaderbuf
= info
->shader_buffers_declared
;
847 enabled_samplers
= info
->samplers_declared
;
848 enabled_images
= info
->images_declared
;
850 enabled_constbuf
= sctx
->const_and_shader_buffers
[processor
].enabled_mask
>>
851 SI_NUM_SHADER_BUFFERS
;
852 enabled_shaderbuf
= sctx
->const_and_shader_buffers
[processor
].enabled_mask
&
853 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
);
854 enabled_shaderbuf
= util_bitreverse(enabled_shaderbuf
) >>
855 (32 - SI_NUM_SHADER_BUFFERS
);
856 enabled_samplers
= sctx
->samplers
[processor
].enabled_mask
;
857 enabled_images
= sctx
->images
[processor
].enabled_mask
;
860 if (processor
== PIPE_SHADER_VERTEX
&&
861 sctx
->vb_descriptors_buffer
&&
862 sctx
->vb_descriptors_gpu_list
&&
863 sctx
->vertex_elements
) {
864 assert(info
); /* only CS may not have an info struct */
865 struct si_descriptors desc
= {};
867 desc
.buffer
= sctx
->vb_descriptors_buffer
;
868 desc
.list
= sctx
->vb_descriptors_gpu_list
;
869 desc
.gpu_list
= sctx
->vb_descriptors_gpu_list
;
870 desc
.element_dw_size
= 4;
871 desc
.num_active_slots
= sctx
->vertex_elements
->vb_desc_list_alloc_size
/ 16;
873 si_dump_descriptor_list(sctx
->screen
, &desc
, name
,
874 " - Vertex buffer", 4, info
->num_inputs
,
878 si_dump_descriptor_list(sctx
->screen
,
879 &descs
[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
],
880 name
, " - Constant buffer", 4,
881 util_last_bit(enabled_constbuf
),
882 si_get_constbuf_slot
, log
);
883 si_dump_descriptor_list(sctx
->screen
,
884 &descs
[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
],
885 name
, " - Shader buffer", 4,
886 util_last_bit(enabled_shaderbuf
),
887 si_get_shaderbuf_slot
, log
);
888 si_dump_descriptor_list(sctx
->screen
,
889 &descs
[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
],
890 name
, " - Sampler", 16,
891 util_last_bit(enabled_samplers
),
892 si_get_sampler_slot
, log
);
893 si_dump_descriptor_list(sctx
->screen
,
894 &descs
[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
],
896 util_last_bit(enabled_images
),
897 si_get_image_slot
, log
);
900 static void si_dump_gfx_descriptors(struct si_context
*sctx
,
901 const struct si_shader_ctx_state
*state
,
902 struct u_log_context
*log
)
904 if (!state
->cso
|| !state
->current
)
907 si_dump_descriptors(sctx
, state
->cso
->type
, &state
->cso
->info
, log
);
910 static void si_dump_compute_descriptors(struct si_context
*sctx
,
911 struct u_log_context
*log
)
913 if (!sctx
->cs_shader_state
.program
)
916 si_dump_descriptors(sctx
, PIPE_SHADER_COMPUTE
, NULL
, log
);
919 struct si_shader_inst
{
920 const char *text
; /* start of disassembly for this instruction */
922 unsigned size
; /* instruction size = 4 or 8 */
923 uint64_t addr
; /* instruction address */
927 * Open the given \p binary as \p rtld_binary and split the contained
928 * disassembly string into instructions and add them to the array
929 * pointed to by \p instructions, which must be sufficiently large.
931 * Labels are considered to be part of the following instruction.
933 * The caller must keep \p rtld_binary alive as long as \p instructions are
934 * used and then close it afterwards.
936 static void si_add_split_disasm(struct si_screen
*screen
,
937 struct ac_rtld_binary
*rtld_binary
,
938 struct si_shader_binary
*binary
,
941 struct si_shader_inst
*instructions
,
942 enum pipe_shader_type shader_type
,
945 if (!ac_rtld_open(rtld_binary
, (struct ac_rtld_open_info
){
946 .info
= &screen
->info
,
947 .shader_type
= tgsi_processor_to_shader_stage(shader_type
),
948 .wave_size
= wave_size
,
950 .elf_ptrs
= &binary
->elf_buffer
,
951 .elf_sizes
= &binary
->elf_size
}))
956 if (!ac_rtld_get_section_by_name(rtld_binary
, ".AMDGPU.disasm",
960 const char *end
= disasm
+ nbytes
;
961 while (disasm
< end
) {
962 const char *semicolon
= memchr(disasm
, ';', end
- disasm
);
966 struct si_shader_inst
*inst
= &instructions
[(*num
)++];
967 const char *inst_end
= memchr(semicolon
+ 1, '\n', end
- semicolon
- 1);
972 inst
->textlen
= inst_end
- disasm
;
975 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
976 inst
->size
= inst_end
- semicolon
> 16 ? 8 : 4;
981 disasm
= inst_end
+ 1;
985 /* If the shader is being executed, print its asm instructions, and annotate
986 * those that are being executed right now with information about waves that
987 * execute them. This is most useful during a GPU hang.
989 static void si_print_annotated_shader(struct si_shader
*shader
,
990 struct ac_wave_info
*waves
,
997 struct si_screen
*screen
= shader
->selector
->screen
;
998 enum pipe_shader_type shader_type
= shader
->selector
->type
;
999 uint64_t start_addr
= shader
->bo
->gpu_address
;
1000 uint64_t end_addr
= start_addr
+ shader
->bo
->b
.b
.width0
;
1003 /* See if any wave executes the shader. */
1004 for (i
= 0; i
< num_waves
; i
++) {
1005 if (start_addr
<= waves
[i
].pc
&& waves
[i
].pc
<= end_addr
)
1009 return; /* the shader is not being executed */
1011 /* Remember the first found wave. The waves are sorted according to PC. */
1015 /* Get the list of instructions.
1016 * Buffer size / 4 is the upper bound of the instruction count.
1018 unsigned num_inst
= 0;
1019 uint64_t inst_addr
= start_addr
;
1020 unsigned wave_size
= si_get_shader_wave_size(shader
);
1021 struct ac_rtld_binary rtld_binaries
[5] = {};
1022 struct si_shader_inst
*instructions
=
1023 calloc(shader
->bo
->b
.b
.width0
/ 4, sizeof(struct si_shader_inst
));
1025 if (shader
->prolog
) {
1026 si_add_split_disasm(screen
, &rtld_binaries
[0], &shader
->prolog
->binary
,
1027 &inst_addr
, &num_inst
, instructions
, shader_type
, wave_size
);
1029 if (shader
->previous_stage
) {
1030 si_add_split_disasm(screen
, &rtld_binaries
[1], &shader
->previous_stage
->binary
,
1031 &inst_addr
, &num_inst
, instructions
, shader_type
, wave_size
);
1033 if (shader
->prolog2
) {
1034 si_add_split_disasm(screen
, &rtld_binaries
[2], &shader
->prolog2
->binary
,
1035 &inst_addr
, &num_inst
, instructions
, shader_type
, wave_size
);
1037 si_add_split_disasm(screen
, &rtld_binaries
[3], &shader
->binary
,
1038 &inst_addr
, &num_inst
, instructions
, shader_type
, wave_size
);
1039 if (shader
->epilog
) {
1040 si_add_split_disasm(screen
, &rtld_binaries
[4], &shader
->epilog
->binary
,
1041 &inst_addr
, &num_inst
, instructions
, shader_type
, wave_size
);
1044 fprintf(f
, COLOR_YELLOW
"%s - annotated disassembly:" COLOR_RESET
"\n",
1045 si_get_shader_name(shader
));
1047 /* Print instructions with annotations. */
1048 for (i
= 0; i
< num_inst
; i
++) {
1049 struct si_shader_inst
*inst
= &instructions
[i
];
1051 fprintf(f
, "%.*s [PC=0x%"PRIx64
", size=%u]\n",
1052 inst
->textlen
, inst
->text
, inst
->addr
, inst
->size
);
1054 /* Print which waves execute the instruction right now. */
1055 while (num_waves
&& inst
->addr
== waves
->pc
) {
1057 " " COLOR_GREEN
"^ SE%u SH%u CU%u "
1058 "SIMD%u WAVE%u EXEC=%016"PRIx64
" ",
1059 waves
->se
, waves
->sh
, waves
->cu
, waves
->simd
,
1060 waves
->wave
, waves
->exec
);
1062 if (inst
->size
== 4) {
1063 fprintf(f
, "INST32=%08X" COLOR_RESET
"\n",
1066 fprintf(f
, "INST64=%08X %08X" COLOR_RESET
"\n",
1067 waves
->inst_dw0
, waves
->inst_dw1
);
1070 waves
->matched
= true;
1078 for (unsigned i
= 0; i
< ARRAY_SIZE(rtld_binaries
); ++i
)
1079 ac_rtld_close(&rtld_binaries
[i
]);
1082 static void si_dump_annotated_shaders(struct si_context
*sctx
, FILE *f
)
1084 struct ac_wave_info waves
[AC_MAX_WAVES_PER_CHIP
];
1085 unsigned num_waves
= ac_get_wave_info(sctx
->chip_class
, waves
);
1087 fprintf(f
, COLOR_CYAN
"The number of active waves = %u" COLOR_RESET
1090 si_print_annotated_shader(sctx
->vs_shader
.current
, waves
, num_waves
, f
);
1091 si_print_annotated_shader(sctx
->tcs_shader
.current
, waves
, num_waves
, f
);
1092 si_print_annotated_shader(sctx
->tes_shader
.current
, waves
, num_waves
, f
);
1093 si_print_annotated_shader(sctx
->gs_shader
.current
, waves
, num_waves
, f
);
1094 si_print_annotated_shader(sctx
->ps_shader
.current
, waves
, num_waves
, f
);
1096 /* Print waves executing shaders that are not currently bound. */
1099 for (i
= 0; i
< num_waves
; i
++) {
1100 if (waves
[i
].matched
)
1104 fprintf(f
, COLOR_CYAN
1105 "Waves not executing currently-bound shaders:"
1109 fprintf(f
, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64
1110 " INST=%08X %08X PC=%"PRIx64
"\n",
1111 waves
[i
].se
, waves
[i
].sh
, waves
[i
].cu
, waves
[i
].simd
,
1112 waves
[i
].wave
, waves
[i
].exec
, waves
[i
].inst_dw0
,
1113 waves
[i
].inst_dw1
, waves
[i
].pc
);
1119 static void si_dump_command(const char *title
, const char *command
, FILE *f
)
1123 FILE *p
= popen(command
, "r");
1127 fprintf(f
, COLOR_YELLOW
"%s: " COLOR_RESET
"\n", title
);
1128 while (fgets(line
, sizeof(line
), p
))
1134 static void si_dump_debug_state(struct pipe_context
*ctx
, FILE *f
,
1137 struct si_context
*sctx
= (struct si_context
*)ctx
;
1140 u_log_flush(sctx
->log
);
1142 if (flags
& PIPE_DUMP_DEVICE_STATUS_REGISTERS
) {
1143 si_dump_debug_registers(sctx
, f
);
1145 si_dump_annotated_shaders(sctx
, f
);
1146 si_dump_command("Active waves (raw data)", "umr -O halt_waves -wa | column -t", f
);
1147 si_dump_command("Wave information", "umr -O halt_waves,bits -wa", f
);
1151 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
)
1153 struct si_shader_ctx_state
*tcs_shader
;
1158 tcs_shader
= &sctx
->tcs_shader
;
1159 if (sctx
->tes_shader
.cso
&& !sctx
->tcs_shader
.cso
)
1160 tcs_shader
= &sctx
->fixed_func_tcs_shader
;
1162 si_dump_framebuffer(sctx
, log
);
1164 si_dump_gfx_shader(sctx
, &sctx
->vs_shader
, log
);
1165 si_dump_gfx_shader(sctx
, tcs_shader
, log
);
1166 si_dump_gfx_shader(sctx
, &sctx
->tes_shader
, log
);
1167 si_dump_gfx_shader(sctx
, &sctx
->gs_shader
, log
);
1168 si_dump_gfx_shader(sctx
, &sctx
->ps_shader
, log
);
1170 si_dump_descriptor_list(sctx
->screen
,
1171 &sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
1172 "", "RW buffers", 4,
1173 sctx
->descriptors
[SI_DESCS_RW_BUFFERS
].num_active_slots
,
1175 si_dump_gfx_descriptors(sctx
, &sctx
->vs_shader
, log
);
1176 si_dump_gfx_descriptors(sctx
, tcs_shader
, log
);
1177 si_dump_gfx_descriptors(sctx
, &sctx
->tes_shader
, log
);
1178 si_dump_gfx_descriptors(sctx
, &sctx
->gs_shader
, log
);
1179 si_dump_gfx_descriptors(sctx
, &sctx
->ps_shader
, log
);
1182 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
)
1187 si_dump_compute_shader(sctx
, log
);
1188 si_dump_compute_descriptors(sctx
, log
);
1191 static void si_dump_dma(struct si_context
*sctx
,
1192 struct radeon_saved_cs
*saved
, FILE *f
)
1194 static const char ib_name
[] = "sDMA IB";
1197 si_dump_bo_list(sctx
, saved
, f
);
1199 fprintf(f
, "------------------ %s begin ------------------\n", ib_name
);
1201 for (i
= 0; i
< saved
->num_dw
; ++i
) {
1202 fprintf(f
, " %08x\n", saved
->ib
[i
]);
1205 fprintf(f
, "------------------- %s end -------------------\n", ib_name
);
1208 fprintf(f
, "SDMA Dump Done.\n");
1211 void si_check_vm_faults(struct si_context
*sctx
,
1212 struct radeon_saved_cs
*saved
, enum ring_type ring
)
1214 struct pipe_screen
*screen
= sctx
->b
.screen
;
1217 char cmd_line
[4096];
1219 if (!ac_vm_fault_occured(sctx
->chip_class
,
1220 &sctx
->dmesg_timestamp
, &addr
))
1223 f
= dd_get_debug_file(false);
1227 fprintf(f
, "VM fault report.\n\n");
1228 if (os_get_command_line(cmd_line
, sizeof(cmd_line
)))
1229 fprintf(f
, "Command: %s\n", cmd_line
);
1230 fprintf(f
, "Driver vendor: %s\n", screen
->get_vendor(screen
));
1231 fprintf(f
, "Device vendor: %s\n", screen
->get_device_vendor(screen
));
1232 fprintf(f
, "Device name: %s\n\n", screen
->get_name(screen
));
1233 fprintf(f
, "Failing VM page: 0x%08"PRIx64
"\n\n", addr
);
1235 if (sctx
->apitrace_call_number
)
1236 fprintf(f
, "Last apitrace call: %u\n\n",
1237 sctx
->apitrace_call_number
);
1241 struct u_log_context log
;
1242 u_log_context_init(&log
);
1244 si_log_draw_state(sctx
, &log
);
1245 si_log_compute_state(sctx
, &log
);
1246 si_log_cs(sctx
, &log
, true);
1248 u_log_new_page_print(&log
, f
);
1249 u_log_context_destroy(&log
);
1253 si_dump_dma(sctx
, saved
, f
);
1262 fprintf(stderr
, "Detected a VM fault, exiting...\n");
1266 void si_init_debug_functions(struct si_context
*sctx
)
1268 sctx
->b
.dump_debug_state
= si_dump_debug_state
;
1270 /* Set the initial dmesg timestamp for this context, so that
1271 * only new messages will be checked for VM faults.
1273 if (sctx
->screen
->debug_flags
& DBG(CHECK_VM
))
1274 ac_vm_fault_occured(sctx
->chip_class
,
1275 &sctx
->dmesg_timestamp
, NULL
);