radeonsi: remove redundant si_shader_info::shader_buffers_declared
[mesa.git] / src / gallium / drivers / radeonsi / si_debug.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "ac_debug.h"
26 #include "ac_rtld.h"
27 #include "driver_ddebug/dd_util.h"
28 #include "si_compute.h"
29 #include "si_pipe.h"
30 #include "sid.h"
31 #include "sid_tables.h"
32 #include "tgsi/tgsi_from_mesa.h"
33 #include "util/u_dump.h"
34 #include "util/u_log.h"
35 #include "util/u_memory.h"
36 #include "util/u_string.h"
37
38 static void si_dump_bo_list(struct si_context *sctx, const struct radeon_saved_cs *saved, FILE *f);
39
40 DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL)
41
42 /**
43 * Store a linearized copy of all chunks of \p cs together with the buffer
44 * list in \p saved.
45 */
46 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved,
47 bool get_buffer_list)
48 {
49 uint32_t *buf;
50 unsigned i;
51
52 /* Save the IB chunks. */
53 saved->num_dw = cs->prev_dw + cs->current.cdw;
54 saved->ib = MALLOC(4 * saved->num_dw);
55 if (!saved->ib)
56 goto oom;
57
58 buf = saved->ib;
59 for (i = 0; i < cs->num_prev; ++i) {
60 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
61 buf += cs->prev[i].cdw;
62 }
63 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
64
65 if (!get_buffer_list)
66 return;
67
68 /* Save the buffer list. */
69 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
70 saved->bo_list = CALLOC(saved->bo_count, sizeof(saved->bo_list[0]));
71 if (!saved->bo_list) {
72 FREE(saved->ib);
73 goto oom;
74 }
75 ws->cs_get_buffer_list(cs, saved->bo_list);
76
77 return;
78
79 oom:
80 fprintf(stderr, "%s: out of memory\n", __func__);
81 memset(saved, 0, sizeof(*saved));
82 }
83
84 void si_clear_saved_cs(struct radeon_saved_cs *saved)
85 {
86 FREE(saved->ib);
87 FREE(saved->bo_list);
88
89 memset(saved, 0, sizeof(*saved));
90 }
91
92 void si_destroy_saved_cs(struct si_saved_cs *scs)
93 {
94 si_clear_saved_cs(&scs->gfx);
95 si_resource_reference(&scs->trace_buf, NULL);
96 free(scs);
97 }
98
99 static void si_dump_shader(struct si_screen *sscreen, struct si_shader *shader, FILE *f)
100 {
101 if (shader->shader_log)
102 fwrite(shader->shader_log, shader->shader_log_size, 1, f);
103 else
104 si_shader_dump(sscreen, shader, NULL, f, false);
105
106 if (shader->bo && sscreen->options.dump_shader_binary) {
107 unsigned size = shader->bo->b.b.width0;
108 fprintf(f, "BO: VA=%" PRIx64 " Size=%u\n", shader->bo->gpu_address, size);
109
110 const char *mapped = sscreen->ws->buffer_map(
111 shader->bo->buf, NULL,
112 PIPE_TRANSFER_UNSYNCHRONIZED | PIPE_TRANSFER_READ | RADEON_TRANSFER_TEMPORARY);
113
114 for (unsigned i = 0; i < size; i += 4) {
115 fprintf(f, " %4x: %08x\n", i, *(uint32_t *)(mapped + i));
116 }
117
118 sscreen->ws->buffer_unmap(shader->bo->buf);
119
120 fprintf(f, "\n");
121 }
122 }
123
124 struct si_log_chunk_shader {
125 /* The shader destroy code assumes a current context for unlinking of
126 * PM4 packets etc.
127 *
128 * While we should be able to destroy shaders without a context, doing
129 * so would happen only very rarely and be therefore likely to fail
130 * just when you're trying to debug something. Let's just remember the
131 * current context in the chunk.
132 */
133 struct si_context *ctx;
134 struct si_shader *shader;
135
136 /* For keep-alive reference counts */
137 struct si_shader_selector *sel;
138 struct si_compute *program;
139 };
140
141 static void si_log_chunk_shader_destroy(void *data)
142 {
143 struct si_log_chunk_shader *chunk = data;
144 si_shader_selector_reference(chunk->ctx, &chunk->sel, NULL);
145 si_compute_reference(&chunk->program, NULL);
146 FREE(chunk);
147 }
148
149 static void si_log_chunk_shader_print(void *data, FILE *f)
150 {
151 struct si_log_chunk_shader *chunk = data;
152 struct si_screen *sscreen = chunk->ctx->screen;
153 si_dump_shader(sscreen, chunk->shader, f);
154 }
155
156 static struct u_log_chunk_type si_log_chunk_type_shader = {
157 .destroy = si_log_chunk_shader_destroy,
158 .print = si_log_chunk_shader_print,
159 };
160
161 static void si_dump_gfx_shader(struct si_context *ctx, const struct si_shader_ctx_state *state,
162 struct u_log_context *log)
163 {
164 struct si_shader *current = state->current;
165
166 if (!state->cso || !current)
167 return;
168
169 struct si_log_chunk_shader *chunk = CALLOC_STRUCT(si_log_chunk_shader);
170 chunk->ctx = ctx;
171 chunk->shader = current;
172 si_shader_selector_reference(ctx, &chunk->sel, current->selector);
173 u_log_chunk(log, &si_log_chunk_type_shader, chunk);
174 }
175
176 static void si_dump_compute_shader(struct si_context *ctx, struct u_log_context *log)
177 {
178 const struct si_cs_shader_state *state = &ctx->cs_shader_state;
179
180 if (!state->program)
181 return;
182
183 struct si_log_chunk_shader *chunk = CALLOC_STRUCT(si_log_chunk_shader);
184 chunk->ctx = ctx;
185 chunk->shader = &state->program->shader;
186 si_compute_reference(&chunk->program, state->program);
187 u_log_chunk(log, &si_log_chunk_type_shader, chunk);
188 }
189
190 /**
191 * Shader compiles can be overridden with arbitrary ELF objects by setting
192 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
193 *
194 * TODO: key this off some hash
195 */
196 bool si_replace_shader(unsigned num, struct si_shader_binary *binary)
197 {
198 const char *p = debug_get_option_replace_shaders();
199 const char *semicolon;
200 char *copy = NULL;
201 FILE *f;
202 long filesize, nread;
203 bool replaced = false;
204
205 if (!p)
206 return false;
207
208 while (*p) {
209 unsigned long i;
210 char *endp;
211 i = strtoul(p, &endp, 0);
212
213 p = endp;
214 if (*p != ':') {
215 fprintf(stderr, "RADEON_REPLACE_SHADERS formatted badly.\n");
216 exit(1);
217 }
218 ++p;
219
220 if (i == num)
221 break;
222
223 p = strchr(p, ';');
224 if (!p)
225 return false;
226 ++p;
227 }
228 if (!*p)
229 return false;
230
231 semicolon = strchr(p, ';');
232 if (semicolon) {
233 p = copy = strndup(p, semicolon - p);
234 if (!copy) {
235 fprintf(stderr, "out of memory\n");
236 return false;
237 }
238 }
239
240 fprintf(stderr, "radeonsi: replace shader %u by %s\n", num, p);
241
242 f = fopen(p, "r");
243 if (!f) {
244 perror("radeonsi: failed to open file");
245 goto out_free;
246 }
247
248 if (fseek(f, 0, SEEK_END) != 0)
249 goto file_error;
250
251 filesize = ftell(f);
252 if (filesize < 0)
253 goto file_error;
254
255 if (fseek(f, 0, SEEK_SET) != 0)
256 goto file_error;
257
258 binary->elf_buffer = MALLOC(filesize);
259 if (!binary->elf_buffer) {
260 fprintf(stderr, "out of memory\n");
261 goto out_close;
262 }
263
264 nread = fread((void *)binary->elf_buffer, 1, filesize, f);
265 if (nread != filesize) {
266 FREE((void *)binary->elf_buffer);
267 binary->elf_buffer = NULL;
268 goto file_error;
269 }
270
271 binary->elf_size = nread;
272 replaced = true;
273
274 out_close:
275 fclose(f);
276 out_free:
277 free(copy);
278 return replaced;
279
280 file_error:
281 perror("radeonsi: reading shader");
282 goto out_close;
283 }
284
285 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
286 * read them, or use "aha -b -f file" to convert them to html.
287 */
288 #define COLOR_RESET "\033[0m"
289 #define COLOR_RED "\033[31m"
290 #define COLOR_GREEN "\033[1;32m"
291 #define COLOR_YELLOW "\033[1;33m"
292 #define COLOR_CYAN "\033[1;36m"
293
294 static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f, unsigned offset)
295 {
296 struct radeon_winsys *ws = sctx->ws;
297 uint32_t value;
298
299 if (ws->read_registers(ws, offset, 1, &value))
300 ac_dump_reg(f, sctx->chip_class, offset, value, ~0);
301 }
302
303 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
304 {
305 if (!sctx->screen->info.has_read_registers_query)
306 return;
307
308 fprintf(f, "Memory-mapped registers:\n");
309 si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
310
311 /* No other registers can be read on DRM < 3.1.0. */
312 if (!sctx->screen->info.is_amdgpu || sctx->screen->info.drm_minor < 1) {
313 fprintf(f, "\n");
314 return;
315 }
316
317 si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2);
318 si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0);
319 si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1);
320 si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2);
321 si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3);
322 si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG);
323 si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG);
324 if (sctx->chip_class <= GFX8) {
325 si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS);
326 si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2);
327 si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3);
328 }
329 si_dump_mmapped_reg(sctx, f, R_008680_CP_STAT);
330 si_dump_mmapped_reg(sctx, f, R_008674_CP_STALLED_STAT1);
331 si_dump_mmapped_reg(sctx, f, R_008678_CP_STALLED_STAT2);
332 si_dump_mmapped_reg(sctx, f, R_008670_CP_STALLED_STAT3);
333 si_dump_mmapped_reg(sctx, f, R_008210_CP_CPC_STATUS);
334 si_dump_mmapped_reg(sctx, f, R_008214_CP_CPC_BUSY_STAT);
335 si_dump_mmapped_reg(sctx, f, R_008218_CP_CPC_STALLED_STAT1);
336 si_dump_mmapped_reg(sctx, f, R_00821C_CP_CPF_STATUS);
337 si_dump_mmapped_reg(sctx, f, R_008220_CP_CPF_BUSY_STAT);
338 si_dump_mmapped_reg(sctx, f, R_008224_CP_CPF_STALLED_STAT1);
339 fprintf(f, "\n");
340 }
341
342 struct si_log_chunk_cs {
343 struct si_context *ctx;
344 struct si_saved_cs *cs;
345 bool dump_bo_list;
346 unsigned gfx_begin, gfx_end;
347 unsigned compute_begin, compute_end;
348 };
349
350 static void si_log_chunk_type_cs_destroy(void *data)
351 {
352 struct si_log_chunk_cs *chunk = data;
353 si_saved_cs_reference(&chunk->cs, NULL);
354 free(chunk);
355 }
356
357 static void si_parse_current_ib(FILE *f, struct radeon_cmdbuf *cs, unsigned begin, unsigned end,
358 int *last_trace_id, unsigned trace_id_count, const char *name,
359 enum chip_class chip_class)
360 {
361 unsigned orig_end = end;
362
363 assert(begin <= end);
364
365 fprintf(f, "------------------ %s begin (dw = %u) ------------------\n", name, begin);
366
367 for (unsigned prev_idx = 0; prev_idx < cs->num_prev; ++prev_idx) {
368 struct radeon_cmdbuf_chunk *chunk = &cs->prev[prev_idx];
369
370 if (begin < chunk->cdw) {
371 ac_parse_ib_chunk(f, chunk->buf + begin, MIN2(end, chunk->cdw) - begin, last_trace_id,
372 trace_id_count, chip_class, NULL, NULL);
373 }
374
375 if (end <= chunk->cdw)
376 return;
377
378 if (begin < chunk->cdw)
379 fprintf(f, "\n---------- Next %s Chunk ----------\n\n", name);
380
381 begin -= MIN2(begin, chunk->cdw);
382 end -= chunk->cdw;
383 }
384
385 assert(end <= cs->current.cdw);
386
387 ac_parse_ib_chunk(f, cs->current.buf + begin, end - begin, last_trace_id, trace_id_count,
388 chip_class, NULL, NULL);
389
390 fprintf(f, "------------------- %s end (dw = %u) -------------------\n\n", name, orig_end);
391 }
392
393 static void si_log_chunk_type_cs_print(void *data, FILE *f)
394 {
395 struct si_log_chunk_cs *chunk = data;
396 struct si_context *ctx = chunk->ctx;
397 struct si_saved_cs *scs = chunk->cs;
398 int last_trace_id = -1;
399 int last_compute_trace_id = -1;
400
401 /* We are expecting that the ddebug pipe has already
402 * waited for the context, so this buffer should be idle.
403 * If the GPU is hung, there is no point in waiting for it.
404 */
405 uint32_t *map = ctx->ws->buffer_map(scs->trace_buf->buf, NULL,
406 PIPE_TRANSFER_UNSYNCHRONIZED | PIPE_TRANSFER_READ);
407 if (map) {
408 last_trace_id = map[0];
409 last_compute_trace_id = map[1];
410 }
411
412 if (chunk->gfx_end != chunk->gfx_begin) {
413 if (chunk->gfx_begin == 0) {
414 if (ctx->cs_preamble_state)
415 ac_parse_ib(f, ctx->cs_preamble_state->pm4, ctx->cs_preamble_state->ndw, NULL, 0,
416 "IB2: Init config", ctx->chip_class, NULL, NULL);
417
418 if (ctx->cs_preamble_gs_rings)
419 ac_parse_ib(f, ctx->cs_preamble_gs_rings->pm4, ctx->cs_preamble_gs_rings->ndw, NULL, 0,
420 "IB2: Init GS rings", ctx->chip_class, NULL, NULL);
421 }
422
423 if (scs->flushed) {
424 ac_parse_ib(f, scs->gfx.ib + chunk->gfx_begin, chunk->gfx_end - chunk->gfx_begin,
425 &last_trace_id, map ? 1 : 0, "IB", ctx->chip_class, NULL, NULL);
426 } else {
427 si_parse_current_ib(f, ctx->gfx_cs, chunk->gfx_begin, chunk->gfx_end, &last_trace_id,
428 map ? 1 : 0, "IB", ctx->chip_class);
429 }
430 }
431
432 if (chunk->compute_end != chunk->compute_begin) {
433 assert(ctx->prim_discard_compute_cs);
434
435 if (scs->flushed) {
436 ac_parse_ib(f, scs->compute.ib + chunk->compute_begin,
437 chunk->compute_end - chunk->compute_begin, &last_compute_trace_id, map ? 1 : 0,
438 "Compute IB", ctx->chip_class, NULL, NULL);
439 } else {
440 si_parse_current_ib(f, ctx->prim_discard_compute_cs, chunk->compute_begin,
441 chunk->compute_end, &last_compute_trace_id, map ? 1 : 0, "Compute IB",
442 ctx->chip_class);
443 }
444 }
445
446 if (chunk->dump_bo_list) {
447 fprintf(f, "Flushing. Time: ");
448 util_dump_ns(f, scs->time_flush);
449 fprintf(f, "\n\n");
450 si_dump_bo_list(ctx, &scs->gfx, f);
451 }
452 }
453
454 static const struct u_log_chunk_type si_log_chunk_type_cs = {
455 .destroy = si_log_chunk_type_cs_destroy,
456 .print = si_log_chunk_type_cs_print,
457 };
458
459 static void si_log_cs(struct si_context *ctx, struct u_log_context *log, bool dump_bo_list)
460 {
461 assert(ctx->current_saved_cs);
462
463 struct si_saved_cs *scs = ctx->current_saved_cs;
464 unsigned gfx_cur = ctx->gfx_cs->prev_dw + ctx->gfx_cs->current.cdw;
465 unsigned compute_cur = 0;
466
467 if (ctx->prim_discard_compute_cs)
468 compute_cur =
469 ctx->prim_discard_compute_cs->prev_dw + ctx->prim_discard_compute_cs->current.cdw;
470
471 if (!dump_bo_list && gfx_cur == scs->gfx_last_dw && compute_cur == scs->compute_last_dw)
472 return;
473
474 struct si_log_chunk_cs *chunk = calloc(1, sizeof(*chunk));
475
476 chunk->ctx = ctx;
477 si_saved_cs_reference(&chunk->cs, scs);
478 chunk->dump_bo_list = dump_bo_list;
479
480 chunk->gfx_begin = scs->gfx_last_dw;
481 chunk->gfx_end = gfx_cur;
482 scs->gfx_last_dw = gfx_cur;
483
484 chunk->compute_begin = scs->compute_last_dw;
485 chunk->compute_end = compute_cur;
486 scs->compute_last_dw = compute_cur;
487
488 u_log_chunk(log, &si_log_chunk_type_cs, chunk);
489 }
490
491 void si_auto_log_cs(void *data, struct u_log_context *log)
492 {
493 struct si_context *ctx = (struct si_context *)data;
494 si_log_cs(ctx, log, false);
495 }
496
497 void si_log_hw_flush(struct si_context *sctx)
498 {
499 if (!sctx->log)
500 return;
501
502 si_log_cs(sctx, sctx->log, true);
503
504 if (&sctx->b == sctx->screen->aux_context) {
505 /* The aux context isn't captured by the ddebug wrapper,
506 * so we dump it on a flush-by-flush basis here.
507 */
508 FILE *f = dd_get_debug_file(false);
509 if (!f) {
510 fprintf(stderr, "radeonsi: error opening aux context dump file.\n");
511 } else {
512 dd_write_header(f, &sctx->screen->b, 0);
513
514 fprintf(f, "Aux context dump:\n\n");
515 u_log_new_page_print(sctx->log, f);
516
517 fclose(f);
518 }
519 }
520 }
521
522 static const char *priority_to_string(enum radeon_bo_priority priority)
523 {
524 #define ITEM(x) [RADEON_PRIO_##x] = #x
525 static const char *table[64] = {
526 ITEM(FENCE),
527 ITEM(TRACE),
528 ITEM(SO_FILLED_SIZE),
529 ITEM(QUERY),
530 ITEM(IB1),
531 ITEM(IB2),
532 ITEM(DRAW_INDIRECT),
533 ITEM(INDEX_BUFFER),
534 ITEM(CP_DMA),
535 ITEM(CONST_BUFFER),
536 ITEM(DESCRIPTORS),
537 ITEM(BORDER_COLORS),
538 ITEM(SAMPLER_BUFFER),
539 ITEM(VERTEX_BUFFER),
540 ITEM(SHADER_RW_BUFFER),
541 ITEM(COMPUTE_GLOBAL),
542 ITEM(SAMPLER_TEXTURE),
543 ITEM(SHADER_RW_IMAGE),
544 ITEM(SAMPLER_TEXTURE_MSAA),
545 ITEM(COLOR_BUFFER),
546 ITEM(DEPTH_BUFFER),
547 ITEM(COLOR_BUFFER_MSAA),
548 ITEM(DEPTH_BUFFER_MSAA),
549 ITEM(SEPARATE_META),
550 ITEM(SHADER_BINARY),
551 ITEM(SHADER_RINGS),
552 ITEM(SCRATCH_BUFFER),
553 };
554 #undef ITEM
555
556 assert(priority < ARRAY_SIZE(table));
557 return table[priority];
558 }
559
560 static int bo_list_compare_va(const struct radeon_bo_list_item *a,
561 const struct radeon_bo_list_item *b)
562 {
563 return a->vm_address < b->vm_address ? -1 : a->vm_address > b->vm_address ? 1 : 0;
564 }
565
566 static void si_dump_bo_list(struct si_context *sctx, const struct radeon_saved_cs *saved, FILE *f)
567 {
568 unsigned i, j;
569
570 if (!saved->bo_list)
571 return;
572
573 /* Sort the list according to VM adddresses first. */
574 qsort(saved->bo_list, saved->bo_count, sizeof(saved->bo_list[0]), (void *)bo_list_compare_va);
575
576 fprintf(f, "Buffer list (in units of pages = 4kB):\n" COLOR_YELLOW
577 " Size VM start page "
578 "VM end page Usage" COLOR_RESET "\n");
579
580 for (i = 0; i < saved->bo_count; i++) {
581 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
582 const unsigned page_size = sctx->screen->info.gart_page_size;
583 uint64_t va = saved->bo_list[i].vm_address;
584 uint64_t size = saved->bo_list[i].bo_size;
585 bool hit = false;
586
587 /* If there's unused virtual memory between 2 buffers, print it. */
588 if (i) {
589 uint64_t previous_va_end =
590 saved->bo_list[i - 1].vm_address + saved->bo_list[i - 1].bo_size;
591
592 if (va > previous_va_end) {
593 fprintf(f, " %10" PRIu64 " -- hole --\n", (va - previous_va_end) / page_size);
594 }
595 }
596
597 /* Print the buffer. */
598 fprintf(f, " %10" PRIu64 " 0x%013" PRIX64 " 0x%013" PRIX64 " ",
599 size / page_size, va / page_size, (va + size) / page_size);
600
601 /* Print the usage. */
602 for (j = 0; j < 32; j++) {
603 if (!(saved->bo_list[i].priority_usage & (1u << j)))
604 continue;
605
606 fprintf(f, "%s%s", !hit ? "" : ", ", priority_to_string(j));
607 hit = true;
608 }
609 fprintf(f, "\n");
610 }
611 fprintf(f, "\nNote: The holes represent memory not used by the IB.\n"
612 " Other buffers can still be allocated there.\n\n");
613 }
614
615 static void si_dump_framebuffer(struct si_context *sctx, struct u_log_context *log)
616 {
617 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
618 struct si_texture *tex;
619 int i;
620
621 for (i = 0; i < state->nr_cbufs; i++) {
622 if (!state->cbufs[i])
623 continue;
624
625 tex = (struct si_texture *)state->cbufs[i]->texture;
626 u_log_printf(log, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i);
627 si_print_texture_info(sctx->screen, tex, log);
628 u_log_printf(log, "\n");
629 }
630
631 if (state->zsbuf) {
632 tex = (struct si_texture *)state->zsbuf->texture;
633 u_log_printf(log, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n");
634 si_print_texture_info(sctx->screen, tex, log);
635 u_log_printf(log, "\n");
636 }
637 }
638
639 typedef unsigned (*slot_remap_func)(unsigned);
640
641 struct si_log_chunk_desc_list {
642 /** Pointer to memory map of buffer where the list is uploader */
643 uint32_t *gpu_list;
644 /** Reference of buffer where the list is uploaded, so that gpu_list
645 * is kept live. */
646 struct si_resource *buf;
647
648 const char *shader_name;
649 const char *elem_name;
650 slot_remap_func slot_remap;
651 enum chip_class chip_class;
652 unsigned element_dw_size;
653 unsigned num_elements;
654
655 uint32_t list[0];
656 };
657
658 static void si_log_chunk_desc_list_destroy(void *data)
659 {
660 struct si_log_chunk_desc_list *chunk = data;
661 si_resource_reference(&chunk->buf, NULL);
662 FREE(chunk);
663 }
664
665 static void si_log_chunk_desc_list_print(void *data, FILE *f)
666 {
667 struct si_log_chunk_desc_list *chunk = data;
668 unsigned sq_img_rsrc_word0 =
669 chunk->chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0 : R_008F10_SQ_IMG_RSRC_WORD0;
670
671 for (unsigned i = 0; i < chunk->num_elements; i++) {
672 unsigned cpu_dw_offset = i * chunk->element_dw_size;
673 unsigned gpu_dw_offset = chunk->slot_remap(i) * chunk->element_dw_size;
674 const char *list_note = chunk->gpu_list ? "GPU list" : "CPU list";
675 uint32_t *cpu_list = chunk->list + cpu_dw_offset;
676 uint32_t *gpu_list = chunk->gpu_list ? chunk->gpu_list + gpu_dw_offset : cpu_list;
677
678 fprintf(f, COLOR_GREEN "%s%s slot %u (%s):" COLOR_RESET "\n", chunk->shader_name,
679 chunk->elem_name, i, list_note);
680
681 switch (chunk->element_dw_size) {
682 case 4:
683 for (unsigned j = 0; j < 4; j++)
684 ac_dump_reg(f, chunk->chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, gpu_list[j],
685 0xffffffff);
686 break;
687 case 8:
688 for (unsigned j = 0; j < 8; j++)
689 ac_dump_reg(f, chunk->chip_class, sq_img_rsrc_word0 + j * 4, gpu_list[j], 0xffffffff);
690
691 fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n");
692 for (unsigned j = 0; j < 4; j++)
693 ac_dump_reg(f, chunk->chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, gpu_list[4 + j],
694 0xffffffff);
695 break;
696 case 16:
697 for (unsigned j = 0; j < 8; j++)
698 ac_dump_reg(f, chunk->chip_class, sq_img_rsrc_word0 + j * 4, gpu_list[j], 0xffffffff);
699
700 fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n");
701 for (unsigned j = 0; j < 4; j++)
702 ac_dump_reg(f, chunk->chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, gpu_list[4 + j],
703 0xffffffff);
704
705 fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n");
706 for (unsigned j = 0; j < 8; j++)
707 ac_dump_reg(f, chunk->chip_class, sq_img_rsrc_word0 + j * 4, gpu_list[8 + j],
708 0xffffffff);
709
710 fprintf(f, COLOR_CYAN " Sampler state:" COLOR_RESET "\n");
711 for (unsigned j = 0; j < 4; j++)
712 ac_dump_reg(f, chunk->chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4, gpu_list[12 + j],
713 0xffffffff);
714 break;
715 }
716
717 if (memcmp(gpu_list, cpu_list, chunk->element_dw_size * 4) != 0) {
718 fprintf(f, COLOR_RED "!!!!! This slot was corrupted in GPU memory !!!!!" COLOR_RESET "\n");
719 }
720
721 fprintf(f, "\n");
722 }
723 }
724
725 static const struct u_log_chunk_type si_log_chunk_type_descriptor_list = {
726 .destroy = si_log_chunk_desc_list_destroy,
727 .print = si_log_chunk_desc_list_print,
728 };
729
730 static void si_dump_descriptor_list(struct si_screen *screen, struct si_descriptors *desc,
731 const char *shader_name, const char *elem_name,
732 unsigned element_dw_size, unsigned num_elements,
733 slot_remap_func slot_remap, struct u_log_context *log)
734 {
735 if (!desc->list)
736 return;
737
738 /* In some cases, the caller doesn't know how many elements are really
739 * uploaded. Reduce num_elements to fit in the range of active slots. */
740 unsigned active_range_dw_begin = desc->first_active_slot * desc->element_dw_size;
741 unsigned active_range_dw_end =
742 active_range_dw_begin + desc->num_active_slots * desc->element_dw_size;
743
744 while (num_elements > 0) {
745 int i = slot_remap(num_elements - 1);
746 unsigned dw_begin = i * element_dw_size;
747 unsigned dw_end = dw_begin + element_dw_size;
748
749 if (dw_begin >= active_range_dw_begin && dw_end <= active_range_dw_end)
750 break;
751
752 num_elements--;
753 }
754
755 struct si_log_chunk_desc_list *chunk =
756 CALLOC_VARIANT_LENGTH_STRUCT(si_log_chunk_desc_list, 4 * element_dw_size * num_elements);
757 chunk->shader_name = shader_name;
758 chunk->elem_name = elem_name;
759 chunk->element_dw_size = element_dw_size;
760 chunk->num_elements = num_elements;
761 chunk->slot_remap = slot_remap;
762 chunk->chip_class = screen->info.chip_class;
763
764 si_resource_reference(&chunk->buf, desc->buffer);
765 chunk->gpu_list = desc->gpu_list;
766
767 for (unsigned i = 0; i < num_elements; ++i) {
768 memcpy(&chunk->list[i * element_dw_size], &desc->list[slot_remap(i) * element_dw_size],
769 4 * element_dw_size);
770 }
771
772 u_log_chunk(log, &si_log_chunk_type_descriptor_list, chunk);
773 }
774
775 static unsigned si_identity(unsigned slot)
776 {
777 return slot;
778 }
779
780 static void si_dump_descriptors(struct si_context *sctx, gl_shader_stage stage,
781 const struct si_shader_info *info, struct u_log_context *log)
782 {
783 enum pipe_shader_type processor = pipe_shader_type_from_mesa(stage);
784 struct si_descriptors *descs =
785 &sctx->descriptors[SI_DESCS_FIRST_SHADER + processor * SI_NUM_SHADER_DESCS];
786 static const char *shader_name[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
787 const char *name = shader_name[processor];
788 unsigned enabled_constbuf, enabled_shaderbuf, enabled_samplers;
789 unsigned enabled_images;
790
791 if (info) {
792 enabled_constbuf = info->const_buffers_declared;
793 enabled_shaderbuf = u_bit_consecutive(0, info->base.num_ssbos);
794 enabled_samplers = info->base.textures_used;
795 enabled_images = info->images_declared;
796 } else {
797 enabled_constbuf =
798 sctx->const_and_shader_buffers[processor].enabled_mask >> SI_NUM_SHADER_BUFFERS;
799 enabled_shaderbuf = sctx->const_and_shader_buffers[processor].enabled_mask &
800 u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS);
801 enabled_shaderbuf = 0;
802 for (int i = 0; i < SI_NUM_SHADER_BUFFERS; i++) {
803 enabled_shaderbuf |=
804 (sctx->const_and_shader_buffers[processor].enabled_mask &
805 1llu << (SI_NUM_SHADER_BUFFERS - i - 1)) << i;
806 }
807 enabled_samplers = sctx->samplers[processor].enabled_mask;
808 enabled_images = sctx->images[processor].enabled_mask;
809 }
810
811 if (stage == MESA_SHADER_VERTEX && sctx->vb_descriptors_buffer &&
812 sctx->vb_descriptors_gpu_list && sctx->vertex_elements) {
813 assert(info); /* only CS may not have an info struct */
814 struct si_descriptors desc = {};
815
816 desc.buffer = sctx->vb_descriptors_buffer;
817 desc.list = sctx->vb_descriptors_gpu_list;
818 desc.gpu_list = sctx->vb_descriptors_gpu_list;
819 desc.element_dw_size = 4;
820 desc.num_active_slots = sctx->vertex_elements->vb_desc_list_alloc_size / 16;
821
822 si_dump_descriptor_list(sctx->screen, &desc, name, " - Vertex buffer", 4, info->num_inputs,
823 si_identity, log);
824 }
825
826 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS], name,
827 " - Constant buffer", 4, util_last_bit(enabled_constbuf),
828 si_get_constbuf_slot, log);
829 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS], name,
830 " - Shader buffer", 4, util_last_bit(enabled_shaderbuf),
831 si_get_shaderbuf_slot, log);
832 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES], name,
833 " - Sampler", 16, util_last_bit(enabled_samplers), si_get_sampler_slot,
834 log);
835 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES], name,
836 " - Image", 8, util_last_bit(enabled_images), si_get_image_slot, log);
837 }
838
839 static void si_dump_gfx_descriptors(struct si_context *sctx,
840 const struct si_shader_ctx_state *state,
841 struct u_log_context *log)
842 {
843 if (!state->cso || !state->current)
844 return;
845
846 si_dump_descriptors(sctx, state->cso->info.stage, &state->cso->info, log);
847 }
848
849 static void si_dump_compute_descriptors(struct si_context *sctx, struct u_log_context *log)
850 {
851 if (!sctx->cs_shader_state.program)
852 return;
853
854 si_dump_descriptors(sctx, MESA_SHADER_COMPUTE, NULL, log);
855 }
856
857 struct si_shader_inst {
858 const char *text; /* start of disassembly for this instruction */
859 unsigned textlen;
860 unsigned size; /* instruction size = 4 or 8 */
861 uint64_t addr; /* instruction address */
862 };
863
864 /**
865 * Open the given \p binary as \p rtld_binary and split the contained
866 * disassembly string into instructions and add them to the array
867 * pointed to by \p instructions, which must be sufficiently large.
868 *
869 * Labels are considered to be part of the following instruction.
870 *
871 * The caller must keep \p rtld_binary alive as long as \p instructions are
872 * used and then close it afterwards.
873 */
874 static void si_add_split_disasm(struct si_screen *screen, struct ac_rtld_binary *rtld_binary,
875 struct si_shader_binary *binary, uint64_t *addr, unsigned *num,
876 struct si_shader_inst *instructions,
877 gl_shader_stage stage, unsigned wave_size)
878 {
879 if (!ac_rtld_open(rtld_binary, (struct ac_rtld_open_info){
880 .info = &screen->info,
881 .shader_type = stage,
882 .wave_size = wave_size,
883 .num_parts = 1,
884 .elf_ptrs = &binary->elf_buffer,
885 .elf_sizes = &binary->elf_size}))
886 return;
887
888 const char *disasm;
889 size_t nbytes;
890 if (!ac_rtld_get_section_by_name(rtld_binary, ".AMDGPU.disasm", &disasm, &nbytes))
891 return;
892
893 const char *end = disasm + nbytes;
894 while (disasm < end) {
895 const char *semicolon = memchr(disasm, ';', end - disasm);
896 if (!semicolon)
897 break;
898
899 struct si_shader_inst *inst = &instructions[(*num)++];
900 const char *inst_end = memchr(semicolon + 1, '\n', end - semicolon - 1);
901 if (!inst_end)
902 inst_end = end;
903
904 inst->text = disasm;
905 inst->textlen = inst_end - disasm;
906
907 inst->addr = *addr;
908 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
909 inst->size = inst_end - semicolon > 16 ? 8 : 4;
910 *addr += inst->size;
911
912 if (inst_end == end)
913 break;
914 disasm = inst_end + 1;
915 }
916 }
917
918 /* If the shader is being executed, print its asm instructions, and annotate
919 * those that are being executed right now with information about waves that
920 * execute them. This is most useful during a GPU hang.
921 */
922 static void si_print_annotated_shader(struct si_shader *shader, struct ac_wave_info *waves,
923 unsigned num_waves, FILE *f)
924 {
925 if (!shader)
926 return;
927
928 struct si_screen *screen = shader->selector->screen;
929 gl_shader_stage stage = shader->selector->info.stage;
930 uint64_t start_addr = shader->bo->gpu_address;
931 uint64_t end_addr = start_addr + shader->bo->b.b.width0;
932 unsigned i;
933
934 /* See if any wave executes the shader. */
935 for (i = 0; i < num_waves; i++) {
936 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
937 break;
938 }
939 if (i == num_waves)
940 return; /* the shader is not being executed */
941
942 /* Remember the first found wave. The waves are sorted according to PC. */
943 waves = &waves[i];
944 num_waves -= i;
945
946 /* Get the list of instructions.
947 * Buffer size / 4 is the upper bound of the instruction count.
948 */
949 unsigned num_inst = 0;
950 uint64_t inst_addr = start_addr;
951 unsigned wave_size = si_get_shader_wave_size(shader);
952 struct ac_rtld_binary rtld_binaries[5] = {};
953 struct si_shader_inst *instructions =
954 calloc(shader->bo->b.b.width0 / 4, sizeof(struct si_shader_inst));
955
956 if (shader->prolog) {
957 si_add_split_disasm(screen, &rtld_binaries[0], &shader->prolog->binary, &inst_addr, &num_inst,
958 instructions, stage, wave_size);
959 }
960 if (shader->previous_stage) {
961 si_add_split_disasm(screen, &rtld_binaries[1], &shader->previous_stage->binary, &inst_addr,
962 &num_inst, instructions, stage, wave_size);
963 }
964 if (shader->prolog2) {
965 si_add_split_disasm(screen, &rtld_binaries[2], &shader->prolog2->binary, &inst_addr,
966 &num_inst, instructions, stage, wave_size);
967 }
968 si_add_split_disasm(screen, &rtld_binaries[3], &shader->binary, &inst_addr, &num_inst,
969 instructions, stage, wave_size);
970 if (shader->epilog) {
971 si_add_split_disasm(screen, &rtld_binaries[4], &shader->epilog->binary, &inst_addr, &num_inst,
972 instructions, stage, wave_size);
973 }
974
975 fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n",
976 si_get_shader_name(shader));
977
978 /* Print instructions with annotations. */
979 for (i = 0; i < num_inst; i++) {
980 struct si_shader_inst *inst = &instructions[i];
981
982 fprintf(f, "%.*s [PC=0x%" PRIx64 ", size=%u]\n", inst->textlen, inst->text, inst->addr,
983 inst->size);
984
985 /* Print which waves execute the instruction right now. */
986 while (num_waves && inst->addr == waves->pc) {
987 fprintf(f,
988 " " COLOR_GREEN "^ SE%u SH%u CU%u "
989 "SIMD%u WAVE%u EXEC=%016" PRIx64 " ",
990 waves->se, waves->sh, waves->cu, waves->simd, waves->wave, waves->exec);
991
992 if (inst->size == 4) {
993 fprintf(f, "INST32=%08X" COLOR_RESET "\n", waves->inst_dw0);
994 } else {
995 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n", waves->inst_dw0, waves->inst_dw1);
996 }
997
998 waves->matched = true;
999 waves = &waves[1];
1000 num_waves--;
1001 }
1002 }
1003
1004 fprintf(f, "\n\n");
1005 free(instructions);
1006 for (unsigned i = 0; i < ARRAY_SIZE(rtld_binaries); ++i)
1007 ac_rtld_close(&rtld_binaries[i]);
1008 }
1009
1010 static void si_dump_annotated_shaders(struct si_context *sctx, FILE *f)
1011 {
1012 struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
1013 unsigned num_waves = ac_get_wave_info(sctx->chip_class, waves);
1014
1015 fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET "\n\n", num_waves);
1016
1017 si_print_annotated_shader(sctx->vs_shader.current, waves, num_waves, f);
1018 si_print_annotated_shader(sctx->tcs_shader.current, waves, num_waves, f);
1019 si_print_annotated_shader(sctx->tes_shader.current, waves, num_waves, f);
1020 si_print_annotated_shader(sctx->gs_shader.current, waves, num_waves, f);
1021 si_print_annotated_shader(sctx->ps_shader.current, waves, num_waves, f);
1022
1023 /* Print waves executing shaders that are not currently bound. */
1024 unsigned i;
1025 bool found = false;
1026 for (i = 0; i < num_waves; i++) {
1027 if (waves[i].matched)
1028 continue;
1029
1030 if (!found) {
1031 fprintf(f, COLOR_CYAN "Waves not executing currently-bound shaders:" COLOR_RESET "\n");
1032 found = true;
1033 }
1034 fprintf(f,
1035 " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016" PRIx64 " INST=%08X %08X PC=%" PRIx64
1036 "\n",
1037 waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd, waves[i].wave, waves[i].exec,
1038 waves[i].inst_dw0, waves[i].inst_dw1, waves[i].pc);
1039 }
1040 if (found)
1041 fprintf(f, "\n\n");
1042 }
1043
1044 static void si_dump_command(const char *title, const char *command, FILE *f)
1045 {
1046 char line[2000];
1047
1048 FILE *p = popen(command, "r");
1049 if (!p)
1050 return;
1051
1052 fprintf(f, COLOR_YELLOW "%s: " COLOR_RESET "\n", title);
1053 while (fgets(line, sizeof(line), p))
1054 fputs(line, f);
1055 fprintf(f, "\n\n");
1056 pclose(p);
1057 }
1058
1059 static void si_dump_debug_state(struct pipe_context *ctx, FILE *f, unsigned flags)
1060 {
1061 struct si_context *sctx = (struct si_context *)ctx;
1062
1063 if (sctx->log)
1064 u_log_flush(sctx->log);
1065
1066 if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS) {
1067 si_dump_debug_registers(sctx, f);
1068
1069 si_dump_annotated_shaders(sctx, f);
1070 si_dump_command("Active waves (raw data)", "umr -O halt_waves -wa | column -t", f);
1071 si_dump_command("Wave information", "umr -O halt_waves,bits -wa", f);
1072 }
1073 }
1074
1075 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log)
1076 {
1077 struct si_shader_ctx_state *tcs_shader;
1078
1079 if (!log)
1080 return;
1081
1082 tcs_shader = &sctx->tcs_shader;
1083 if (sctx->tes_shader.cso && !sctx->tcs_shader.cso)
1084 tcs_shader = &sctx->fixed_func_tcs_shader;
1085
1086 si_dump_framebuffer(sctx, log);
1087
1088 si_dump_gfx_shader(sctx, &sctx->vs_shader, log);
1089 si_dump_gfx_shader(sctx, tcs_shader, log);
1090 si_dump_gfx_shader(sctx, &sctx->tes_shader, log);
1091 si_dump_gfx_shader(sctx, &sctx->gs_shader, log);
1092 si_dump_gfx_shader(sctx, &sctx->ps_shader, log);
1093
1094 si_dump_descriptor_list(sctx->screen, &sctx->descriptors[SI_DESCS_RW_BUFFERS], "", "RW buffers",
1095 4, sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots, si_identity,
1096 log);
1097 si_dump_gfx_descriptors(sctx, &sctx->vs_shader, log);
1098 si_dump_gfx_descriptors(sctx, tcs_shader, log);
1099 si_dump_gfx_descriptors(sctx, &sctx->tes_shader, log);
1100 si_dump_gfx_descriptors(sctx, &sctx->gs_shader, log);
1101 si_dump_gfx_descriptors(sctx, &sctx->ps_shader, log);
1102 }
1103
1104 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log)
1105 {
1106 if (!log)
1107 return;
1108
1109 si_dump_compute_shader(sctx, log);
1110 si_dump_compute_descriptors(sctx, log);
1111 }
1112
1113 static void si_dump_dma(struct si_context *sctx, struct radeon_saved_cs *saved, FILE *f)
1114 {
1115 static const char ib_name[] = "sDMA IB";
1116 unsigned i;
1117
1118 si_dump_bo_list(sctx, saved, f);
1119
1120 fprintf(f, "------------------ %s begin ------------------\n", ib_name);
1121
1122 for (i = 0; i < saved->num_dw; ++i) {
1123 fprintf(f, " %08x\n", saved->ib[i]);
1124 }
1125
1126 fprintf(f, "------------------- %s end -------------------\n", ib_name);
1127 fprintf(f, "\n");
1128
1129 fprintf(f, "SDMA Dump Done.\n");
1130 }
1131
1132 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved, enum ring_type ring)
1133 {
1134 struct pipe_screen *screen = sctx->b.screen;
1135 FILE *f;
1136 uint64_t addr;
1137 char cmd_line[4096];
1138
1139 if (!ac_vm_fault_occured(sctx->chip_class, &sctx->dmesg_timestamp, &addr))
1140 return;
1141
1142 f = dd_get_debug_file(false);
1143 if (!f)
1144 return;
1145
1146 fprintf(f, "VM fault report.\n\n");
1147 if (os_get_command_line(cmd_line, sizeof(cmd_line)))
1148 fprintf(f, "Command: %s\n", cmd_line);
1149 fprintf(f, "Driver vendor: %s\n", screen->get_vendor(screen));
1150 fprintf(f, "Device vendor: %s\n", screen->get_device_vendor(screen));
1151 fprintf(f, "Device name: %s\n\n", screen->get_name(screen));
1152 fprintf(f, "Failing VM page: 0x%08" PRIx64 "\n\n", addr);
1153
1154 if (sctx->apitrace_call_number)
1155 fprintf(f, "Last apitrace call: %u\n\n", sctx->apitrace_call_number);
1156
1157 switch (ring) {
1158 case RING_GFX: {
1159 struct u_log_context log;
1160 u_log_context_init(&log);
1161
1162 si_log_draw_state(sctx, &log);
1163 si_log_compute_state(sctx, &log);
1164 si_log_cs(sctx, &log, true);
1165
1166 u_log_new_page_print(&log, f);
1167 u_log_context_destroy(&log);
1168 break;
1169 }
1170 case RING_DMA:
1171 si_dump_dma(sctx, saved, f);
1172 break;
1173
1174 default:
1175 break;
1176 }
1177
1178 fclose(f);
1179
1180 fprintf(stderr, "Detected a VM fault, exiting...\n");
1181 exit(0);
1182 }
1183
1184 void si_init_debug_functions(struct si_context *sctx)
1185 {
1186 sctx->b.dump_debug_state = si_dump_debug_state;
1187
1188 /* Set the initial dmesg timestamp for this context, so that
1189 * only new messages will be checked for VM faults.
1190 */
1191 if (sctx->screen->debug_flags & DBG(CHECK_VM))
1192 ac_vm_fault_occured(sctx->chip_class, &sctx->dmesg_timestamp, NULL);
1193 }