ac/debug: Move IB decode to common code.
[mesa.git] / src / gallium / drivers / radeonsi / si_debug.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Marek Olšák <maraeo@gmail.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "sid_tables.h"
30 #include "radeon/radeon_elf_util.h"
31 #include "ddebug/dd_util.h"
32 #include "util/u_memory.h"
33 #include "ac_debug.h"
34
35 DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL)
36
37 static void si_dump_shader(struct si_screen *sscreen,
38 struct si_shader_ctx_state *state, FILE *f)
39 {
40 struct si_shader *current = state->current;
41
42 if (!state->cso || !current)
43 return;
44
45 if (current->shader_log)
46 fwrite(current->shader_log, current->shader_log_size, 1, f);
47 else
48 si_shader_dump(sscreen, state->current, NULL,
49 state->cso->info.processor, f, false);
50 }
51
52 /**
53 * Shader compiles can be overridden with arbitrary ELF objects by setting
54 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
55 */
56 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary)
57 {
58 const char *p = debug_get_option_replace_shaders();
59 const char *semicolon;
60 char *copy = NULL;
61 FILE *f;
62 long filesize, nread;
63 char *buf = NULL;
64 bool replaced = false;
65
66 if (!p)
67 return false;
68
69 while (*p) {
70 unsigned long i;
71 char *endp;
72 i = strtoul(p, &endp, 0);
73
74 p = endp;
75 if (*p != ':') {
76 fprintf(stderr, "RADEON_REPLACE_SHADERS formatted badly.\n");
77 exit(1);
78 }
79 ++p;
80
81 if (i == num)
82 break;
83
84 p = strchr(p, ';');
85 if (!p)
86 return false;
87 ++p;
88 }
89 if (!*p)
90 return false;
91
92 semicolon = strchr(p, ';');
93 if (semicolon) {
94 p = copy = strndup(p, semicolon - p);
95 if (!copy) {
96 fprintf(stderr, "out of memory\n");
97 return false;
98 }
99 }
100
101 fprintf(stderr, "radeonsi: replace shader %u by %s\n", num, p);
102
103 f = fopen(p, "r");
104 if (!f) {
105 perror("radeonsi: failed to open file");
106 goto out_free;
107 }
108
109 if (fseek(f, 0, SEEK_END) != 0)
110 goto file_error;
111
112 filesize = ftell(f);
113 if (filesize < 0)
114 goto file_error;
115
116 if (fseek(f, 0, SEEK_SET) != 0)
117 goto file_error;
118
119 buf = MALLOC(filesize);
120 if (!buf) {
121 fprintf(stderr, "out of memory\n");
122 goto out_close;
123 }
124
125 nread = fread(buf, 1, filesize, f);
126 if (nread != filesize)
127 goto file_error;
128
129 radeon_elf_read(buf, filesize, binary);
130 replaced = true;
131
132 out_close:
133 fclose(f);
134 out_free:
135 FREE(buf);
136 free(copy);
137 return replaced;
138
139 file_error:
140 perror("radeonsi: reading shader");
141 goto out_close;
142 }
143
144 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
145 * read them, or use "aha -b -f file" to convert them to html.
146 */
147 #define COLOR_RESET "\033[0m"
148 #define COLOR_RED "\033[31m"
149 #define COLOR_GREEN "\033[1;32m"
150 #define COLOR_YELLOW "\033[1;33m"
151 #define COLOR_CYAN "\033[1;36m"
152
153 static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
154 unsigned offset)
155 {
156 struct radeon_winsys *ws = sctx->b.ws;
157 uint32_t value;
158
159 if (ws->read_registers(ws, offset, 1, &value))
160 ac_dump_reg(f, offset, value, ~0);
161 }
162
163 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
164 {
165 if (sctx->screen->b.info.drm_major == 2 &&
166 sctx->screen->b.info.drm_minor < 42)
167 return; /* no radeon support */
168
169 fprintf(f, "Memory-mapped registers:\n");
170 si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
171
172 /* No other registers can be read on DRM < 3.1.0. */
173 if (sctx->screen->b.info.drm_major < 3 ||
174 sctx->screen->b.info.drm_minor < 1) {
175 fprintf(f, "\n");
176 return;
177 }
178
179 si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2);
180 si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0);
181 si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1);
182 si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2);
183 si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3);
184 si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG);
185 si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG);
186 si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS);
187 si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2);
188 si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3);
189 si_dump_mmapped_reg(sctx, f, R_008680_CP_STAT);
190 si_dump_mmapped_reg(sctx, f, R_008674_CP_STALLED_STAT1);
191 si_dump_mmapped_reg(sctx, f, R_008678_CP_STALLED_STAT2);
192 si_dump_mmapped_reg(sctx, f, R_008670_CP_STALLED_STAT3);
193 si_dump_mmapped_reg(sctx, f, R_008210_CP_CPC_STATUS);
194 si_dump_mmapped_reg(sctx, f, R_008214_CP_CPC_BUSY_STAT);
195 si_dump_mmapped_reg(sctx, f, R_008218_CP_CPC_STALLED_STAT1);
196 si_dump_mmapped_reg(sctx, f, R_00821C_CP_CPF_STATUS);
197 si_dump_mmapped_reg(sctx, f, R_008220_CP_CPF_BUSY_STAT);
198 si_dump_mmapped_reg(sctx, f, R_008224_CP_CPF_STALLED_STAT1);
199 fprintf(f, "\n");
200 }
201
202 static void si_dump_last_ib(struct si_context *sctx, FILE *f)
203 {
204 int last_trace_id = -1;
205
206 if (!sctx->last_gfx.ib)
207 return;
208
209 if (sctx->last_trace_buf) {
210 /* We are expecting that the ddebug pipe has already
211 * waited for the context, so this buffer should be idle.
212 * If the GPU is hung, there is no point in waiting for it.
213 */
214 uint32_t *map = sctx->b.ws->buffer_map(sctx->last_trace_buf->buf,
215 NULL,
216 PIPE_TRANSFER_UNSYNCHRONIZED |
217 PIPE_TRANSFER_READ);
218 if (map)
219 last_trace_id = *map;
220 }
221
222 if (sctx->init_config)
223 ac_parse_ib(f, sctx->init_config->pm4, sctx->init_config->ndw,
224 -1, "IB2: Init config", sctx->b.chip_class);
225
226 if (sctx->init_config_gs_rings)
227 ac_parse_ib(f, sctx->init_config_gs_rings->pm4,
228 sctx->init_config_gs_rings->ndw,
229 -1, "IB2: Init GS rings", sctx->b.chip_class);
230
231 ac_parse_ib(f, sctx->last_gfx.ib, sctx->last_gfx.num_dw,
232 last_trace_id, "IB", sctx->b.chip_class);
233 }
234
235 static const char *priority_to_string(enum radeon_bo_priority priority)
236 {
237 #define ITEM(x) [RADEON_PRIO_##x] = #x
238 static const char *table[64] = {
239 ITEM(FENCE),
240 ITEM(TRACE),
241 ITEM(SO_FILLED_SIZE),
242 ITEM(QUERY),
243 ITEM(IB1),
244 ITEM(IB2),
245 ITEM(DRAW_INDIRECT),
246 ITEM(INDEX_BUFFER),
247 ITEM(VCE),
248 ITEM(UVD),
249 ITEM(SDMA_BUFFER),
250 ITEM(SDMA_TEXTURE),
251 ITEM(CP_DMA),
252 ITEM(CONST_BUFFER),
253 ITEM(DESCRIPTORS),
254 ITEM(BORDER_COLORS),
255 ITEM(SAMPLER_BUFFER),
256 ITEM(VERTEX_BUFFER),
257 ITEM(SHADER_RW_BUFFER),
258 ITEM(COMPUTE_GLOBAL),
259 ITEM(SAMPLER_TEXTURE),
260 ITEM(SHADER_RW_IMAGE),
261 ITEM(SAMPLER_TEXTURE_MSAA),
262 ITEM(COLOR_BUFFER),
263 ITEM(DEPTH_BUFFER),
264 ITEM(COLOR_BUFFER_MSAA),
265 ITEM(DEPTH_BUFFER_MSAA),
266 ITEM(CMASK),
267 ITEM(DCC),
268 ITEM(HTILE),
269 ITEM(SHADER_BINARY),
270 ITEM(SHADER_RINGS),
271 ITEM(SCRATCH_BUFFER),
272 };
273 #undef ITEM
274
275 assert(priority < ARRAY_SIZE(table));
276 return table[priority];
277 }
278
279 static int bo_list_compare_va(const struct radeon_bo_list_item *a,
280 const struct radeon_bo_list_item *b)
281 {
282 return a->vm_address < b->vm_address ? -1 :
283 a->vm_address > b->vm_address ? 1 : 0;
284 }
285
286 static void si_dump_bo_list(struct si_context *sctx,
287 const struct radeon_saved_cs *saved, FILE *f)
288 {
289 unsigned i,j;
290
291 if (!saved->bo_list)
292 return;
293
294 /* Sort the list according to VM adddresses first. */
295 qsort(saved->bo_list, saved->bo_count,
296 sizeof(saved->bo_list[0]), (void*)bo_list_compare_va);
297
298 fprintf(f, "Buffer list (in units of pages = 4kB):\n"
299 COLOR_YELLOW " Size VM start page "
300 "VM end page Usage" COLOR_RESET "\n");
301
302 for (i = 0; i < saved->bo_count; i++) {
303 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
304 const unsigned page_size = sctx->b.screen->info.gart_page_size;
305 uint64_t va = saved->bo_list[i].vm_address;
306 uint64_t size = saved->bo_list[i].bo_size;
307 bool hit = false;
308
309 /* If there's unused virtual memory between 2 buffers, print it. */
310 if (i) {
311 uint64_t previous_va_end = saved->bo_list[i-1].vm_address +
312 saved->bo_list[i-1].bo_size;
313
314 if (va > previous_va_end) {
315 fprintf(f, " %10"PRIu64" -- hole --\n",
316 (va - previous_va_end) / page_size);
317 }
318 }
319
320 /* Print the buffer. */
321 fprintf(f, " %10"PRIu64" 0x%013"PRIX64" 0x%013"PRIX64" ",
322 size / page_size, va / page_size, (va + size) / page_size);
323
324 /* Print the usage. */
325 for (j = 0; j < 64; j++) {
326 if (!(saved->bo_list[i].priority_usage & (1llu << j)))
327 continue;
328
329 fprintf(f, "%s%s", !hit ? "" : ", ", priority_to_string(j));
330 hit = true;
331 }
332 fprintf(f, "\n");
333 }
334 fprintf(f, "\nNote: The holes represent memory not used by the IB.\n"
335 " Other buffers can still be allocated there.\n\n");
336 }
337
338 static void si_dump_framebuffer(struct si_context *sctx, FILE *f)
339 {
340 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
341 struct r600_texture *rtex;
342 int i;
343
344 for (i = 0; i < state->nr_cbufs; i++) {
345 if (!state->cbufs[i])
346 continue;
347
348 rtex = (struct r600_texture*)state->cbufs[i]->texture;
349 fprintf(f, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i);
350 r600_print_texture_info(rtex, f);
351 fprintf(f, "\n");
352 }
353
354 if (state->zsbuf) {
355 rtex = (struct r600_texture*)state->zsbuf->texture;
356 fprintf(f, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n");
357 r600_print_texture_info(rtex, f);
358 fprintf(f, "\n");
359 }
360 }
361
362 static void si_dump_descriptor_list(struct si_descriptors *desc,
363 const char *shader_name,
364 const char *elem_name,
365 unsigned num_elements,
366 FILE *f)
367 {
368 unsigned i, j;
369 uint32_t *cpu_list = desc->list;
370 uint32_t *gpu_list = desc->gpu_list;
371 const char *list_note = "GPU list";
372
373 if (!gpu_list) {
374 gpu_list = cpu_list;
375 list_note = "CPU list";
376 }
377
378 for (i = 0; i < num_elements; i++) {
379 fprintf(f, COLOR_GREEN "%s%s slot %u (%s):" COLOR_RESET "\n",
380 shader_name, elem_name, i, list_note);
381
382 switch (desc->element_dw_size) {
383 case 4:
384 for (j = 0; j < 4; j++)
385 ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
386 gpu_list[j], 0xffffffff);
387 break;
388 case 8:
389 for (j = 0; j < 8; j++)
390 ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
391 gpu_list[j], 0xffffffff);
392
393 fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n");
394 for (j = 0; j < 4; j++)
395 ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
396 gpu_list[4+j], 0xffffffff);
397 break;
398 case 16:
399 for (j = 0; j < 8; j++)
400 ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
401 gpu_list[j], 0xffffffff);
402
403 fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n");
404 for (j = 0; j < 4; j++)
405 ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
406 gpu_list[4+j], 0xffffffff);
407
408 fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n");
409 for (j = 0; j < 8; j++)
410 ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
411 gpu_list[8+j], 0xffffffff);
412
413 fprintf(f, COLOR_CYAN " Sampler state:" COLOR_RESET "\n");
414 for (j = 0; j < 4; j++)
415 ac_dump_reg(f, R_008F30_SQ_IMG_SAMP_WORD0 + j*4,
416 gpu_list[12+j], 0xffffffff);
417 break;
418 }
419
420 if (memcmp(gpu_list, cpu_list, desc->element_dw_size * 4) != 0) {
421 fprintf(f, COLOR_RED "!!!!! This slot was corrupted in GPU memory !!!!!"
422 COLOR_RESET "\n");
423 }
424
425 fprintf(f, "\n");
426 gpu_list += desc->element_dw_size;
427 cpu_list += desc->element_dw_size;
428 }
429 }
430
431 static void si_dump_descriptors(struct si_context *sctx,
432 struct si_shader_ctx_state *state,
433 FILE *f)
434 {
435 if (!state->cso || !state->current)
436 return;
437
438 unsigned type = state->cso->type;
439 const struct tgsi_shader_info *info = &state->cso->info;
440 struct si_descriptors *descs =
441 &sctx->descriptors[SI_DESCS_FIRST_SHADER +
442 type * SI_NUM_SHADER_DESCS];
443 static const char *shader_name[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
444
445 static const char *elem_name[] = {
446 " - Constant buffer",
447 " - Shader buffer",
448 " - Sampler",
449 " - Image",
450 };
451 unsigned num_elements[] = {
452 util_last_bit(info->const_buffers_declared),
453 util_last_bit(info->shader_buffers_declared),
454 util_last_bit(info->samplers_declared),
455 util_last_bit(info->images_declared),
456 };
457
458 if (type == PIPE_SHADER_VERTEX) {
459 si_dump_descriptor_list(&sctx->vertex_buffers, shader_name[type],
460 " - Vertex buffer", info->num_inputs, f);
461 }
462
463 for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
464 si_dump_descriptor_list(descs, shader_name[type], elem_name[i],
465 num_elements[i], f);
466 }
467
468 static void si_dump_debug_state(struct pipe_context *ctx, FILE *f,
469 unsigned flags)
470 {
471 struct si_context *sctx = (struct si_context*)ctx;
472
473 if (flags & PIPE_DUMP_DEVICE_STATUS_REGISTERS)
474 si_dump_debug_registers(sctx, f);
475
476 if (flags & PIPE_DUMP_CURRENT_STATES)
477 si_dump_framebuffer(sctx, f);
478
479 if (flags & PIPE_DUMP_CURRENT_SHADERS) {
480 si_dump_shader(sctx->screen, &sctx->vs_shader, f);
481 si_dump_shader(sctx->screen, &sctx->tcs_shader, f);
482 si_dump_shader(sctx->screen, &sctx->tes_shader, f);
483 si_dump_shader(sctx->screen, &sctx->gs_shader, f);
484 si_dump_shader(sctx->screen, &sctx->ps_shader, f);
485
486 si_dump_descriptor_list(&sctx->descriptors[SI_DESCS_RW_BUFFERS],
487 "", "RW buffers", SI_NUM_RW_BUFFERS, f);
488 si_dump_descriptors(sctx, &sctx->vs_shader, f);
489 si_dump_descriptors(sctx, &sctx->tcs_shader, f);
490 si_dump_descriptors(sctx, &sctx->tes_shader, f);
491 si_dump_descriptors(sctx, &sctx->gs_shader, f);
492 si_dump_descriptors(sctx, &sctx->ps_shader, f);
493 }
494
495 if (flags & PIPE_DUMP_LAST_COMMAND_BUFFER) {
496 si_dump_bo_list(sctx, &sctx->last_gfx, f);
497 si_dump_last_ib(sctx, f);
498
499 fprintf(f, "Done.\n");
500
501 /* dump only once */
502 radeon_clear_saved_cs(&sctx->last_gfx);
503 r600_resource_reference(&sctx->last_trace_buf, NULL);
504 }
505 }
506
507 static void si_dump_dma(struct si_context *sctx,
508 struct radeon_saved_cs *saved, FILE *f)
509 {
510 static const char ib_name[] = "sDMA IB";
511 unsigned i;
512
513 si_dump_bo_list(sctx, saved, f);
514
515 fprintf(f, "------------------ %s begin ------------------\n", ib_name);
516
517 for (i = 0; i < saved->num_dw; ++i) {
518 fprintf(f, " %08x\n", saved->ib[i]);
519 }
520
521 fprintf(f, "------------------- %s end -------------------\n", ib_name);
522 fprintf(f, "\n");
523
524 fprintf(f, "SDMA Dump Done.\n");
525 }
526
527 static bool si_vm_fault_occured(struct si_context *sctx, uint32_t *out_addr)
528 {
529 char line[2000];
530 unsigned sec, usec;
531 int progress = 0;
532 uint64_t timestamp = 0;
533 bool fault = false;
534
535 FILE *p = popen("dmesg", "r");
536 if (!p)
537 return false;
538
539 while (fgets(line, sizeof(line), p)) {
540 char *msg, len;
541
542 if (!line[0] || line[0] == '\n')
543 continue;
544
545 /* Get the timestamp. */
546 if (sscanf(line, "[%u.%u]", &sec, &usec) != 2) {
547 static bool hit = false;
548 if (!hit) {
549 fprintf(stderr, "%s: failed to parse line '%s'\n",
550 __func__, line);
551 hit = true;
552 }
553 continue;
554 }
555 timestamp = sec * 1000000llu + usec;
556
557 /* If just updating the timestamp. */
558 if (!out_addr)
559 continue;
560
561 /* Process messages only if the timestamp is newer. */
562 if (timestamp <= sctx->dmesg_timestamp)
563 continue;
564
565 /* Only process the first VM fault. */
566 if (fault)
567 continue;
568
569 /* Remove trailing \n */
570 len = strlen(line);
571 if (len && line[len-1] == '\n')
572 line[len-1] = 0;
573
574 /* Get the message part. */
575 msg = strchr(line, ']');
576 if (!msg) {
577 assert(0);
578 continue;
579 }
580 msg++;
581
582 switch (progress) {
583 case 0:
584 if (strstr(msg, "GPU fault detected:"))
585 progress = 1;
586 break;
587 case 1:
588 msg = strstr(msg, "VM_CONTEXT1_PROTECTION_FAULT_ADDR");
589 if (msg) {
590 msg = strstr(msg, "0x");
591 if (msg) {
592 msg += 2;
593 if (sscanf(msg, "%X", out_addr) == 1)
594 fault = true;
595 }
596 }
597 progress = 0;
598 break;
599 default:
600 progress = 0;
601 }
602 }
603 pclose(p);
604
605 if (timestamp > sctx->dmesg_timestamp)
606 sctx->dmesg_timestamp = timestamp;
607 return fault;
608 }
609
610 void si_check_vm_faults(struct r600_common_context *ctx,
611 struct radeon_saved_cs *saved, enum ring_type ring)
612 {
613 struct si_context *sctx = (struct si_context *)ctx;
614 struct pipe_screen *screen = sctx->b.b.screen;
615 FILE *f;
616 uint32_t addr;
617 char cmd_line[4096];
618
619 if (!si_vm_fault_occured(sctx, &addr))
620 return;
621
622 f = dd_get_debug_file(false);
623 if (!f)
624 return;
625
626 fprintf(f, "VM fault report.\n\n");
627 if (os_get_command_line(cmd_line, sizeof(cmd_line)))
628 fprintf(f, "Command: %s\n", cmd_line);
629 fprintf(f, "Driver vendor: %s\n", screen->get_vendor(screen));
630 fprintf(f, "Device vendor: %s\n", screen->get_device_vendor(screen));
631 fprintf(f, "Device name: %s\n\n", screen->get_name(screen));
632 fprintf(f, "Failing VM page: 0x%08x\n\n", addr);
633
634 if (sctx->apitrace_call_number)
635 fprintf(f, "Last apitrace call: %u\n\n",
636 sctx->apitrace_call_number);
637
638 switch (ring) {
639 case RING_GFX:
640 si_dump_debug_state(&sctx->b.b, f,
641 PIPE_DUMP_CURRENT_STATES |
642 PIPE_DUMP_CURRENT_SHADERS |
643 PIPE_DUMP_LAST_COMMAND_BUFFER);
644 break;
645
646 case RING_DMA:
647 si_dump_dma(sctx, saved, f);
648 break;
649
650 default:
651 break;
652 }
653
654 fclose(f);
655
656 fprintf(stderr, "Detected a VM fault, exiting...\n");
657 exit(0);
658 }
659
660 void si_init_debug_functions(struct si_context *sctx)
661 {
662 sctx->b.b.dump_debug_state = si_dump_debug_state;
663 sctx->b.check_vm_faults = si_check_vm_faults;
664
665 /* Set the initial dmesg timestamp for this context, so that
666 * only new messages will be checked for VM faults.
667 */
668 if (sctx->screen->b.debug_flags & DBG_CHECK_VM)
669 si_vm_fault_occured(sctx, NULL);
670 }