2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <maraeo@gmail.com>
28 #include "si_compute.h"
31 #include "sid_tables.h"
32 #include "ddebug/dd_util.h"
33 #include "util/u_memory.h"
36 DEBUG_GET_ONCE_OPTION(replace_shaders
, "RADEON_REPLACE_SHADERS", NULL
)
38 static void si_dump_shader(struct si_screen
*sscreen
,
39 enum pipe_shader_type processor
,
40 const struct si_shader
*shader
, FILE *f
)
42 if (shader
->shader_log
)
43 fwrite(shader
->shader_log
, shader
->shader_log_size
, 1, f
);
45 si_shader_dump(sscreen
, shader
, NULL
, processor
, f
, false);
48 static void si_dump_gfx_shader(struct si_screen
*sscreen
,
49 const struct si_shader_ctx_state
*state
, FILE *f
)
51 const struct si_shader
*current
= state
->current
;
53 if (!state
->cso
|| !current
)
56 si_dump_shader(sscreen
, state
->cso
->info
.processor
, current
, f
);
59 static void si_dump_compute_shader(struct si_screen
*sscreen
,
60 const struct si_cs_shader_state
*state
, FILE *f
)
62 if (!state
->program
|| state
->program
!= state
->emitted_program
)
65 si_dump_shader(sscreen
, PIPE_SHADER_COMPUTE
, &state
->program
->shader
, f
);
69 * Shader compiles can be overridden with arbitrary ELF objects by setting
70 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
72 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
)
74 const char *p
= debug_get_option_replace_shaders();
75 const char *semicolon
;
80 bool replaced
= false;
88 i
= strtoul(p
, &endp
, 0);
92 fprintf(stderr
, "RADEON_REPLACE_SHADERS formatted badly.\n");
108 semicolon
= strchr(p
, ';');
110 p
= copy
= strndup(p
, semicolon
- p
);
112 fprintf(stderr
, "out of memory\n");
117 fprintf(stderr
, "radeonsi: replace shader %u by %s\n", num
, p
);
121 perror("radeonsi: failed to open file");
125 if (fseek(f
, 0, SEEK_END
) != 0)
132 if (fseek(f
, 0, SEEK_SET
) != 0)
135 buf
= MALLOC(filesize
);
137 fprintf(stderr
, "out of memory\n");
141 nread
= fread(buf
, 1, filesize
, f
);
142 if (nread
!= filesize
)
145 ac_elf_read(buf
, filesize
, binary
);
156 perror("radeonsi: reading shader");
160 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
161 * read them, or use "aha -b -f file" to convert them to html.
163 #define COLOR_RESET "\033[0m"
164 #define COLOR_RED "\033[31m"
165 #define COLOR_GREEN "\033[1;32m"
166 #define COLOR_YELLOW "\033[1;33m"
167 #define COLOR_CYAN "\033[1;36m"
169 static void si_dump_mmapped_reg(struct si_context
*sctx
, FILE *f
,
172 struct radeon_winsys
*ws
= sctx
->b
.ws
;
175 if (ws
->read_registers(ws
, offset
, 1, &value
))
176 ac_dump_reg(f
, offset
, value
, ~0);
179 static void si_dump_debug_registers(struct si_context
*sctx
, FILE *f
)
181 if (sctx
->screen
->b
.info
.drm_major
== 2 &&
182 sctx
->screen
->b
.info
.drm_minor
< 42)
183 return; /* no radeon support */
185 fprintf(f
, "Memory-mapped registers:\n");
186 si_dump_mmapped_reg(sctx
, f
, R_008010_GRBM_STATUS
);
188 /* No other registers can be read on DRM < 3.1.0. */
189 if (sctx
->screen
->b
.info
.drm_major
< 3 ||
190 sctx
->screen
->b
.info
.drm_minor
< 1) {
195 si_dump_mmapped_reg(sctx
, f
, R_008008_GRBM_STATUS2
);
196 si_dump_mmapped_reg(sctx
, f
, R_008014_GRBM_STATUS_SE0
);
197 si_dump_mmapped_reg(sctx
, f
, R_008018_GRBM_STATUS_SE1
);
198 si_dump_mmapped_reg(sctx
, f
, R_008038_GRBM_STATUS_SE2
);
199 si_dump_mmapped_reg(sctx
, f
, R_00803C_GRBM_STATUS_SE3
);
200 si_dump_mmapped_reg(sctx
, f
, R_00D034_SDMA0_STATUS_REG
);
201 si_dump_mmapped_reg(sctx
, f
, R_00D834_SDMA1_STATUS_REG
);
202 if (sctx
->b
.chip_class
<= VI
) {
203 si_dump_mmapped_reg(sctx
, f
, R_000E50_SRBM_STATUS
);
204 si_dump_mmapped_reg(sctx
, f
, R_000E4C_SRBM_STATUS2
);
205 si_dump_mmapped_reg(sctx
, f
, R_000E54_SRBM_STATUS3
);
207 si_dump_mmapped_reg(sctx
, f
, R_008680_CP_STAT
);
208 si_dump_mmapped_reg(sctx
, f
, R_008674_CP_STALLED_STAT1
);
209 si_dump_mmapped_reg(sctx
, f
, R_008678_CP_STALLED_STAT2
);
210 si_dump_mmapped_reg(sctx
, f
, R_008670_CP_STALLED_STAT3
);
211 si_dump_mmapped_reg(sctx
, f
, R_008210_CP_CPC_STATUS
);
212 si_dump_mmapped_reg(sctx
, f
, R_008214_CP_CPC_BUSY_STAT
);
213 si_dump_mmapped_reg(sctx
, f
, R_008218_CP_CPC_STALLED_STAT1
);
214 si_dump_mmapped_reg(sctx
, f
, R_00821C_CP_CPF_STATUS
);
215 si_dump_mmapped_reg(sctx
, f
, R_008220_CP_CPF_BUSY_STAT
);
216 si_dump_mmapped_reg(sctx
, f
, R_008224_CP_CPF_STALLED_STAT1
);
220 static void si_dump_last_ib(struct si_context
*sctx
, FILE *f
)
222 int last_trace_id
= -1;
224 if (!sctx
->last_gfx
.ib
)
227 if (sctx
->last_trace_buf
) {
228 /* We are expecting that the ddebug pipe has already
229 * waited for the context, so this buffer should be idle.
230 * If the GPU is hung, there is no point in waiting for it.
232 uint32_t *map
= sctx
->b
.ws
->buffer_map(sctx
->last_trace_buf
->buf
,
234 PIPE_TRANSFER_UNSYNCHRONIZED
|
237 last_trace_id
= *map
;
240 if (sctx
->init_config
)
241 ac_parse_ib(f
, sctx
->init_config
->pm4
, sctx
->init_config
->ndw
,
242 -1, "IB2: Init config", sctx
->b
.chip_class
,
245 if (sctx
->init_config_gs_rings
)
246 ac_parse_ib(f
, sctx
->init_config_gs_rings
->pm4
,
247 sctx
->init_config_gs_rings
->ndw
,
248 -1, "IB2: Init GS rings", sctx
->b
.chip_class
,
251 ac_parse_ib(f
, sctx
->last_gfx
.ib
, sctx
->last_gfx
.num_dw
,
252 last_trace_id
, "IB", sctx
->b
.chip_class
,
256 static const char *priority_to_string(enum radeon_bo_priority priority
)
258 #define ITEM(x) [RADEON_PRIO_##x] = #x
259 static const char *table
[64] = {
262 ITEM(SO_FILLED_SIZE
),
276 ITEM(SAMPLER_BUFFER
),
278 ITEM(SHADER_RW_BUFFER
),
279 ITEM(COMPUTE_GLOBAL
),
280 ITEM(SAMPLER_TEXTURE
),
281 ITEM(SHADER_RW_IMAGE
),
282 ITEM(SAMPLER_TEXTURE_MSAA
),
285 ITEM(COLOR_BUFFER_MSAA
),
286 ITEM(DEPTH_BUFFER_MSAA
),
292 ITEM(SCRATCH_BUFFER
),
296 assert(priority
< ARRAY_SIZE(table
));
297 return table
[priority
];
300 static int bo_list_compare_va(const struct radeon_bo_list_item
*a
,
301 const struct radeon_bo_list_item
*b
)
303 return a
->vm_address
< b
->vm_address
? -1 :
304 a
->vm_address
> b
->vm_address
? 1 : 0;
307 static void si_dump_bo_list(struct si_context
*sctx
,
308 const struct radeon_saved_cs
*saved
, FILE *f
)
315 /* Sort the list according to VM adddresses first. */
316 qsort(saved
->bo_list
, saved
->bo_count
,
317 sizeof(saved
->bo_list
[0]), (void*)bo_list_compare_va
);
319 fprintf(f
, "Buffer list (in units of pages = 4kB):\n"
320 COLOR_YELLOW
" Size VM start page "
321 "VM end page Usage" COLOR_RESET
"\n");
323 for (i
= 0; i
< saved
->bo_count
; i
++) {
324 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
325 const unsigned page_size
= sctx
->b
.screen
->info
.gart_page_size
;
326 uint64_t va
= saved
->bo_list
[i
].vm_address
;
327 uint64_t size
= saved
->bo_list
[i
].bo_size
;
330 /* If there's unused virtual memory between 2 buffers, print it. */
332 uint64_t previous_va_end
= saved
->bo_list
[i
-1].vm_address
+
333 saved
->bo_list
[i
-1].bo_size
;
335 if (va
> previous_va_end
) {
336 fprintf(f
, " %10"PRIu64
" -- hole --\n",
337 (va
- previous_va_end
) / page_size
);
341 /* Print the buffer. */
342 fprintf(f
, " %10"PRIu64
" 0x%013"PRIX64
" 0x%013"PRIX64
" ",
343 size
/ page_size
, va
/ page_size
, (va
+ size
) / page_size
);
345 /* Print the usage. */
346 for (j
= 0; j
< 64; j
++) {
347 if (!(saved
->bo_list
[i
].priority_usage
& (1llu << j
)))
350 fprintf(f
, "%s%s", !hit
? "" : ", ", priority_to_string(j
));
355 fprintf(f
, "\nNote: The holes represent memory not used by the IB.\n"
356 " Other buffers can still be allocated there.\n\n");
359 static void si_dump_framebuffer(struct si_context
*sctx
, FILE *f
)
361 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
362 struct r600_texture
*rtex
;
365 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
366 if (!state
->cbufs
[i
])
369 rtex
= (struct r600_texture
*)state
->cbufs
[i
]->texture
;
370 fprintf(f
, COLOR_YELLOW
"Color buffer %i:" COLOR_RESET
"\n", i
);
371 r600_print_texture_info(sctx
->b
.screen
, rtex
, f
);
376 rtex
= (struct r600_texture
*)state
->zsbuf
->texture
;
377 fprintf(f
, COLOR_YELLOW
"Depth-stencil buffer:" COLOR_RESET
"\n");
378 r600_print_texture_info(sctx
->b
.screen
, rtex
, f
);
383 static void si_dump_descriptor_list(struct si_descriptors
*desc
,
384 const char *shader_name
,
385 const char *elem_name
,
386 unsigned num_elements
,
390 uint32_t *cpu_list
= desc
->list
;
391 uint32_t *gpu_list
= desc
->gpu_list
;
392 const char *list_note
= "GPU list";
396 list_note
= "CPU list";
399 for (i
= 0; i
< num_elements
; i
++) {
400 fprintf(f
, COLOR_GREEN
"%s%s slot %u (%s):" COLOR_RESET
"\n",
401 shader_name
, elem_name
, i
, list_note
);
403 switch (desc
->element_dw_size
) {
405 for (j
= 0; j
< 4; j
++)
406 ac_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
407 gpu_list
[j
], 0xffffffff);
410 for (j
= 0; j
< 8; j
++)
411 ac_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
412 gpu_list
[j
], 0xffffffff);
414 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
415 for (j
= 0; j
< 4; j
++)
416 ac_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
417 gpu_list
[4+j
], 0xffffffff);
420 for (j
= 0; j
< 8; j
++)
421 ac_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
422 gpu_list
[j
], 0xffffffff);
424 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
425 for (j
= 0; j
< 4; j
++)
426 ac_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
427 gpu_list
[4+j
], 0xffffffff);
429 fprintf(f
, COLOR_CYAN
" FMASK:" COLOR_RESET
"\n");
430 for (j
= 0; j
< 8; j
++)
431 ac_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
432 gpu_list
[8+j
], 0xffffffff);
434 fprintf(f
, COLOR_CYAN
" Sampler state:" COLOR_RESET
"\n");
435 for (j
= 0; j
< 4; j
++)
436 ac_dump_reg(f
, R_008F30_SQ_IMG_SAMP_WORD0
+ j
*4,
437 gpu_list
[12+j
], 0xffffffff);
441 if (memcmp(gpu_list
, cpu_list
, desc
->element_dw_size
* 4) != 0) {
442 fprintf(f
, COLOR_RED
"!!!!! This slot was corrupted in GPU memory !!!!!"
447 gpu_list
+= desc
->element_dw_size
;
448 cpu_list
+= desc
->element_dw_size
;
452 static void si_dump_descriptors(struct si_context
*sctx
,
453 enum pipe_shader_type processor
,
454 const struct tgsi_shader_info
*info
, FILE *f
)
456 struct si_descriptors
*descs
=
457 &sctx
->descriptors
[SI_DESCS_FIRST_SHADER
+
458 processor
* SI_NUM_SHADER_DESCS
];
459 static const char *shader_name
[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
461 static const char *elem_name
[] = {
462 " - Constant buffer",
467 unsigned enabled_slots
[] = {
468 sctx
->const_buffers
[processor
].enabled_mask
,
469 sctx
->shader_buffers
[processor
].enabled_mask
,
470 sctx
->samplers
[processor
].views
.enabled_mask
,
471 sctx
->images
[processor
].enabled_mask
,
473 unsigned required_slots
[] = {
474 info
? info
->const_buffers_declared
: 0,
475 info
? info
->shader_buffers_declared
: 0,
476 info
? info
->samplers_declared
: 0,
477 info
? info
->images_declared
: 0,
480 if (processor
== PIPE_SHADER_VERTEX
) {
481 assert(info
); /* only CS may not have an info struct */
483 si_dump_descriptor_list(&sctx
->vertex_buffers
, shader_name
[processor
],
484 " - Vertex buffer", info
->num_inputs
, f
);
487 for (unsigned i
= 0; i
< SI_NUM_SHADER_DESCS
; ++i
, ++descs
)
488 si_dump_descriptor_list(descs
, shader_name
[processor
], elem_name
[i
],
489 util_last_bit(enabled_slots
[i
] | required_slots
[i
]), f
);
492 static void si_dump_gfx_descriptors(struct si_context
*sctx
,
493 const struct si_shader_ctx_state
*state
,
496 if (!state
->cso
|| !state
->current
)
499 si_dump_descriptors(sctx
, state
->cso
->type
, &state
->cso
->info
, f
);
502 static void si_dump_compute_descriptors(struct si_context
*sctx
, FILE *f
)
504 if (!sctx
->cs_shader_state
.program
||
505 sctx
->cs_shader_state
.program
!= sctx
->cs_shader_state
.emitted_program
)
508 si_dump_descriptors(sctx
, PIPE_SHADER_COMPUTE
, NULL
, f
);
511 struct si_shader_inst
{
512 char text
[160]; /* one disasm line */
513 unsigned offset
; /* instruction offset */
514 unsigned size
; /* instruction size = 4 or 8 */
517 /* Split a disassembly string into lines and add them to the array pointed
518 * to by "instructions". */
519 static void si_add_split_disasm(const char *disasm
,
522 struct si_shader_inst
*instructions
)
524 struct si_shader_inst
*last_inst
= *num
? &instructions
[*num
- 1] : NULL
;
527 while ((next
= strchr(disasm
, '\n'))) {
528 struct si_shader_inst
*inst
= &instructions
[*num
];
529 unsigned len
= next
- disasm
;
531 assert(len
< ARRAY_SIZE(inst
->text
));
532 memcpy(inst
->text
, disasm
, len
);
534 inst
->offset
= last_inst
? last_inst
->offset
+ last_inst
->size
: 0;
536 const char *semicolon
= strchr(disasm
, ';');
538 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
539 inst
->size
= next
- semicolon
> 16 ? 8 : 4;
541 snprintf(inst
->text
+ len
, ARRAY_SIZE(inst
->text
) - len
,
542 " [PC=0x%"PRIx64
", off=%u, size=%u]",
543 start_addr
+ inst
->offset
, inst
->offset
, inst
->size
);
551 #define MAX_WAVES_PER_CHIP (64 * 40)
553 struct si_wave_info
{
554 unsigned se
; /* shader engine */
555 unsigned sh
; /* shader array */
556 unsigned cu
; /* compute unit */
560 uint64_t pc
; /* program counter */
564 bool matched
; /* whether the wave is used by a currently-bound shader */
567 static int compare_wave(const void *p1
, const void *p2
)
569 struct si_wave_info
*w1
= (struct si_wave_info
*)p1
;
570 struct si_wave_info
*w2
= (struct si_wave_info
*)p2
;
572 /* Sort waves according to PC and then SE, SH, CU, etc. */
589 if (w1
->simd
< w2
->simd
)
591 if (w1
->simd
> w2
->simd
)
593 if (w1
->wave
< w2
->wave
)
595 if (w1
->wave
> w2
->wave
)
601 /* Return wave information. "waves" should be a large enough array. */
602 static unsigned si_get_wave_info(struct si_wave_info waves
[MAX_WAVES_PER_CHIP
])
605 unsigned num_waves
= 0;
607 FILE *p
= popen("umr -wa", "r");
611 if (!fgets(line
, sizeof(line
), p
) ||
612 strncmp(line
, "SE", 2) != 0) {
617 while (fgets(line
, sizeof(line
), p
)) {
618 struct si_wave_info
*w
;
619 uint32_t pc_hi
, pc_lo
, exec_hi
, exec_lo
;
621 assert(num_waves
< MAX_WAVES_PER_CHIP
);
622 w
= &waves
[num_waves
];
624 if (sscanf(line
, "%u %u %u %u %u %x %x %x %x %x %x %x",
625 &w
->se
, &w
->sh
, &w
->cu
, &w
->simd
, &w
->wave
,
626 &w
->status
, &pc_hi
, &pc_lo
, &w
->inst_dw0
,
627 &w
->inst_dw1
, &exec_hi
, &exec_lo
) == 12) {
628 w
->pc
= ((uint64_t)pc_hi
<< 32) | pc_lo
;
629 w
->exec
= ((uint64_t)exec_hi
<< 32) | exec_lo
;
635 qsort(waves
, num_waves
, sizeof(struct si_wave_info
), compare_wave
);
641 /* If the shader is being executed, print its asm instructions, and annotate
642 * those that are being executed right now with information about waves that
643 * execute them. This is most useful during a GPU hang.
645 static void si_print_annotated_shader(struct si_shader
*shader
,
646 struct si_wave_info
*waves
,
650 if (!shader
|| !shader
->binary
.disasm_string
)
653 uint64_t start_addr
= shader
->bo
->gpu_address
;
654 uint64_t end_addr
= start_addr
+ shader
->bo
->b
.b
.width0
;
657 /* See if any wave executes the shader. */
658 for (i
= 0; i
< num_waves
; i
++) {
659 if (start_addr
<= waves
[i
].pc
&& waves
[i
].pc
<= end_addr
)
663 return; /* the shader is not being executed */
665 /* Remember the first found wave. The waves are sorted according to PC. */
669 /* Get the list of instructions.
670 * Buffer size / 4 is the upper bound of the instruction count.
672 unsigned num_inst
= 0;
673 struct si_shader_inst
*instructions
=
674 calloc(shader
->bo
->b
.b
.width0
/ 4, sizeof(struct si_shader_inst
));
676 if (shader
->prolog
) {
677 si_add_split_disasm(shader
->prolog
->binary
.disasm_string
,
678 start_addr
, &num_inst
, instructions
);
680 if (shader
->previous_stage
) {
681 si_add_split_disasm(shader
->previous_stage
->binary
.disasm_string
,
682 start_addr
, &num_inst
, instructions
);
684 if (shader
->prolog2
) {
685 si_add_split_disasm(shader
->prolog2
->binary
.disasm_string
,
686 start_addr
, &num_inst
, instructions
);
688 si_add_split_disasm(shader
->binary
.disasm_string
,
689 start_addr
, &num_inst
, instructions
);
690 if (shader
->epilog
) {
691 si_add_split_disasm(shader
->epilog
->binary
.disasm_string
,
692 start_addr
, &num_inst
, instructions
);
695 fprintf(f
, COLOR_YELLOW
"%s - annotated disassembly:" COLOR_RESET
"\n",
696 si_get_shader_name(shader
, shader
->selector
->type
));
698 /* Print instructions with annotations. */
699 for (i
= 0; i
< num_inst
; i
++) {
700 struct si_shader_inst
*inst
= &instructions
[i
];
702 fprintf(f
, "%s\n", inst
->text
);
704 /* Print which waves execute the instruction right now. */
705 while (num_waves
&& start_addr
+ inst
->offset
== waves
->pc
) {
707 " " COLOR_GREEN
"^ SE%u SH%u CU%u "
708 "SIMD%u WAVE%u EXEC=%016"PRIx64
" ",
709 waves
->se
, waves
->sh
, waves
->cu
, waves
->simd
,
710 waves
->wave
, waves
->exec
);
712 if (inst
->size
== 4) {
713 fprintf(f
, "INST32=%08X" COLOR_RESET
"\n",
716 fprintf(f
, "INST64=%08X %08X" COLOR_RESET
"\n",
717 waves
->inst_dw0
, waves
->inst_dw1
);
720 waves
->matched
= true;
730 static void si_dump_annotated_shaders(struct si_context
*sctx
, FILE *f
)
732 struct si_wave_info waves
[MAX_WAVES_PER_CHIP
];
733 unsigned num_waves
= si_get_wave_info(waves
);
735 fprintf(f
, COLOR_CYAN
"The number of active waves = %u" COLOR_RESET
738 si_print_annotated_shader(sctx
->vs_shader
.current
, waves
, num_waves
, f
);
739 si_print_annotated_shader(sctx
->tcs_shader
.current
, waves
, num_waves
, f
);
740 si_print_annotated_shader(sctx
->tes_shader
.current
, waves
, num_waves
, f
);
741 si_print_annotated_shader(sctx
->gs_shader
.current
, waves
, num_waves
, f
);
742 si_print_annotated_shader(sctx
->ps_shader
.current
, waves
, num_waves
, f
);
744 /* Print waves executing shaders that are not currently bound. */
747 for (i
= 0; i
< num_waves
; i
++) {
748 if (waves
[i
].matched
)
752 fprintf(f
, COLOR_CYAN
753 "Waves not executing currently-bound shaders:"
757 fprintf(f
, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64
758 " INST=%08X %08X PC=%"PRIx64
"\n",
759 waves
[i
].se
, waves
[i
].sh
, waves
[i
].cu
, waves
[i
].simd
,
760 waves
[i
].wave
, waves
[i
].exec
, waves
[i
].inst_dw0
,
761 waves
[i
].inst_dw1
, waves
[i
].pc
);
767 static void si_dump_command(const char *title
, const char *command
, FILE *f
)
771 FILE *p
= popen(command
, "r");
775 fprintf(f
, COLOR_YELLOW
"%s: " COLOR_RESET
"\n", title
);
776 while (fgets(line
, sizeof(line
), p
))
782 static void si_dump_debug_state(struct pipe_context
*ctx
, FILE *f
,
785 struct si_context
*sctx
= (struct si_context
*)ctx
;
787 if (flags
& PIPE_DUMP_DEVICE_STATUS_REGISTERS
)
788 si_dump_debug_registers(sctx
, f
);
790 if (flags
& PIPE_DUMP_CURRENT_STATES
)
791 si_dump_framebuffer(sctx
, f
);
793 if (flags
& PIPE_DUMP_CURRENT_SHADERS
) {
794 si_dump_gfx_shader(sctx
->screen
, &sctx
->vs_shader
, f
);
795 si_dump_gfx_shader(sctx
->screen
, &sctx
->tcs_shader
, f
);
796 si_dump_gfx_shader(sctx
->screen
, &sctx
->tes_shader
, f
);
797 si_dump_gfx_shader(sctx
->screen
, &sctx
->gs_shader
, f
);
798 si_dump_gfx_shader(sctx
->screen
, &sctx
->ps_shader
, f
);
799 si_dump_compute_shader(sctx
->screen
, &sctx
->cs_shader_state
, f
);
801 if (flags
& PIPE_DUMP_DEVICE_STATUS_REGISTERS
) {
802 si_dump_annotated_shaders(sctx
, f
);
803 si_dump_command("Active waves (raw data)", "umr -wa | column -t", f
);
804 si_dump_command("Wave information", "umr -O bits -wa", f
);
807 si_dump_descriptor_list(&sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
808 "", "RW buffers", SI_NUM_RW_BUFFERS
, f
);
809 si_dump_gfx_descriptors(sctx
, &sctx
->vs_shader
, f
);
810 si_dump_gfx_descriptors(sctx
, &sctx
->tcs_shader
, f
);
811 si_dump_gfx_descriptors(sctx
, &sctx
->tes_shader
, f
);
812 si_dump_gfx_descriptors(sctx
, &sctx
->gs_shader
, f
);
813 si_dump_gfx_descriptors(sctx
, &sctx
->ps_shader
, f
);
814 si_dump_compute_descriptors(sctx
, f
);
817 if (flags
& PIPE_DUMP_LAST_COMMAND_BUFFER
) {
818 si_dump_bo_list(sctx
, &sctx
->last_gfx
, f
);
819 si_dump_last_ib(sctx
, f
);
821 fprintf(f
, "Done.\n");
824 radeon_clear_saved_cs(&sctx
->last_gfx
);
825 r600_resource_reference(&sctx
->last_trace_buf
, NULL
);
829 static void si_dump_dma(struct si_context
*sctx
,
830 struct radeon_saved_cs
*saved
, FILE *f
)
832 static const char ib_name
[] = "sDMA IB";
835 si_dump_bo_list(sctx
, saved
, f
);
837 fprintf(f
, "------------------ %s begin ------------------\n", ib_name
);
839 for (i
= 0; i
< saved
->num_dw
; ++i
) {
840 fprintf(f
, " %08x\n", saved
->ib
[i
]);
843 fprintf(f
, "------------------- %s end -------------------\n", ib_name
);
846 fprintf(f
, "SDMA Dump Done.\n");
849 static bool si_vm_fault_occured(struct si_context
*sctx
, uint32_t *out_addr
)
854 uint64_t timestamp
= 0;
857 FILE *p
= popen("dmesg", "r");
861 while (fgets(line
, sizeof(line
), p
)) {
864 if (!line
[0] || line
[0] == '\n')
867 /* Get the timestamp. */
868 if (sscanf(line
, "[%u.%u]", &sec
, &usec
) != 2) {
869 static bool hit
= false;
871 fprintf(stderr
, "%s: failed to parse line '%s'\n",
877 timestamp
= sec
* 1000000llu + usec
;
879 /* If just updating the timestamp. */
883 /* Process messages only if the timestamp is newer. */
884 if (timestamp
<= sctx
->dmesg_timestamp
)
887 /* Only process the first VM fault. */
891 /* Remove trailing \n */
893 if (len
&& line
[len
-1] == '\n')
896 /* Get the message part. */
897 msg
= strchr(line
, ']');
906 if (strstr(msg
, "GPU fault detected:"))
910 msg
= strstr(msg
, "VM_CONTEXT1_PROTECTION_FAULT_ADDR");
912 msg
= strstr(msg
, "0x");
915 if (sscanf(msg
, "%X", out_addr
) == 1)
927 if (timestamp
> sctx
->dmesg_timestamp
)
928 sctx
->dmesg_timestamp
= timestamp
;
932 void si_check_vm_faults(struct r600_common_context
*ctx
,
933 struct radeon_saved_cs
*saved
, enum ring_type ring
)
935 struct si_context
*sctx
= (struct si_context
*)ctx
;
936 struct pipe_screen
*screen
= sctx
->b
.b
.screen
;
941 if (!si_vm_fault_occured(sctx
, &addr
))
944 f
= dd_get_debug_file(false);
948 fprintf(f
, "VM fault report.\n\n");
949 if (os_get_command_line(cmd_line
, sizeof(cmd_line
)))
950 fprintf(f
, "Command: %s\n", cmd_line
);
951 fprintf(f
, "Driver vendor: %s\n", screen
->get_vendor(screen
));
952 fprintf(f
, "Device vendor: %s\n", screen
->get_device_vendor(screen
));
953 fprintf(f
, "Device name: %s\n\n", screen
->get_name(screen
));
954 fprintf(f
, "Failing VM page: 0x%08x\n\n", addr
);
956 if (sctx
->apitrace_call_number
)
957 fprintf(f
, "Last apitrace call: %u\n\n",
958 sctx
->apitrace_call_number
);
962 si_dump_debug_state(&sctx
->b
.b
, f
,
963 PIPE_DUMP_CURRENT_STATES
|
964 PIPE_DUMP_CURRENT_SHADERS
|
965 PIPE_DUMP_LAST_COMMAND_BUFFER
);
969 si_dump_dma(sctx
, saved
, f
);
978 fprintf(stderr
, "Detected a VM fault, exiting...\n");
982 void si_init_debug_functions(struct si_context
*sctx
)
984 sctx
->b
.b
.dump_debug_state
= si_dump_debug_state
;
985 sctx
->b
.check_vm_faults
= si_check_vm_faults
;
987 /* Set the initial dmesg timestamp for this context, so that
988 * only new messages will be checked for VM faults.
990 if (sctx
->screen
->b
.debug_flags
& DBG_CHECK_VM
)
991 si_vm_fault_occured(sctx
, NULL
);