2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Marek Olšák <maraeo@gmail.com>
28 #include "si_compute.h"
31 #include "sid_tables.h"
32 #include "ddebug/dd_util.h"
33 #include "util/u_log.h"
34 #include "util/u_memory.h"
37 static void si_dump_bo_list(struct si_context
*sctx
,
38 const struct radeon_saved_cs
*saved
, FILE *f
);
40 DEBUG_GET_ONCE_OPTION(replace_shaders
, "RADEON_REPLACE_SHADERS", NULL
)
42 static void si_dump_shader(struct si_screen
*sscreen
,
43 enum pipe_shader_type processor
,
44 const struct si_shader
*shader
, FILE *f
)
46 if (shader
->shader_log
)
47 fwrite(shader
->shader_log
, shader
->shader_log_size
, 1, f
);
49 si_shader_dump(sscreen
, shader
, NULL
, processor
, f
, false);
52 struct si_log_chunk_shader
{
53 /* The shader destroy code assumes a current context for unlinking of
56 * While we should be able to destroy shaders without a context, doing
57 * so would happen only very rarely and be therefore likely to fail
58 * just when you're trying to debug something. Let's just remember the
59 * current context in the chunk.
61 struct si_context
*ctx
;
62 struct si_shader
*shader
;
64 /* For keep-alive reference counts */
65 struct si_shader_selector
*sel
;
66 struct si_compute
*program
;
70 si_log_chunk_shader_destroy(void *data
)
72 struct si_log_chunk_shader
*chunk
= data
;
73 si_shader_selector_reference(chunk
->ctx
, &chunk
->sel
, NULL
);
74 si_compute_reference(&chunk
->program
, NULL
);
79 si_log_chunk_shader_print(void *data
, FILE *f
)
81 struct si_log_chunk_shader
*chunk
= data
;
82 struct si_screen
*sscreen
= chunk
->ctx
->screen
;
83 si_dump_shader(sscreen
, chunk
->shader
->selector
->info
.processor
,
87 static struct u_log_chunk_type si_log_chunk_type_shader
= {
88 .destroy
= si_log_chunk_shader_destroy
,
89 .print
= si_log_chunk_shader_print
,
92 static void si_dump_gfx_shader(struct si_context
*ctx
,
93 const struct si_shader_ctx_state
*state
,
94 struct u_log_context
*log
)
96 struct si_shader
*current
= state
->current
;
98 if (!state
->cso
|| !current
)
101 struct si_log_chunk_shader
*chunk
= CALLOC_STRUCT(si_log_chunk_shader
);
103 chunk
->shader
= current
;
104 si_shader_selector_reference(ctx
, &chunk
->sel
, current
->selector
);
105 u_log_chunk(log
, &si_log_chunk_type_shader
, chunk
);
108 static void si_dump_compute_shader(const struct si_cs_shader_state
*state
,
109 struct u_log_context
*log
)
111 if (!state
->program
|| state
->program
!= state
->emitted_program
)
114 struct si_log_chunk_shader
*chunk
= CALLOC_STRUCT(si_log_chunk_shader
);
115 chunk
->shader
= &state
->program
->shader
;
116 si_compute_reference(&chunk
->program
, state
->program
);
117 u_log_chunk(log
, &si_log_chunk_type_shader
, chunk
);
121 * Shader compiles can be overridden with arbitrary ELF objects by setting
122 * the environment variable RADEON_REPLACE_SHADERS=num1:filename1[;num2:filename2]
124 bool si_replace_shader(unsigned num
, struct ac_shader_binary
*binary
)
126 const char *p
= debug_get_option_replace_shaders();
127 const char *semicolon
;
130 long filesize
, nread
;
132 bool replaced
= false;
140 i
= strtoul(p
, &endp
, 0);
144 fprintf(stderr
, "RADEON_REPLACE_SHADERS formatted badly.\n");
160 semicolon
= strchr(p
, ';');
162 p
= copy
= strndup(p
, semicolon
- p
);
164 fprintf(stderr
, "out of memory\n");
169 fprintf(stderr
, "radeonsi: replace shader %u by %s\n", num
, p
);
173 perror("radeonsi: failed to open file");
177 if (fseek(f
, 0, SEEK_END
) != 0)
184 if (fseek(f
, 0, SEEK_SET
) != 0)
187 buf
= MALLOC(filesize
);
189 fprintf(stderr
, "out of memory\n");
193 nread
= fread(buf
, 1, filesize
, f
);
194 if (nread
!= filesize
)
197 ac_elf_read(buf
, filesize
, binary
);
208 perror("radeonsi: reading shader");
212 /* Parsed IBs are difficult to read without colors. Use "less -R file" to
213 * read them, or use "aha -b -f file" to convert them to html.
215 #define COLOR_RESET "\033[0m"
216 #define COLOR_RED "\033[31m"
217 #define COLOR_GREEN "\033[1;32m"
218 #define COLOR_YELLOW "\033[1;33m"
219 #define COLOR_CYAN "\033[1;36m"
221 static void si_dump_mmapped_reg(struct si_context
*sctx
, FILE *f
,
224 struct radeon_winsys
*ws
= sctx
->b
.ws
;
227 if (ws
->read_registers(ws
, offset
, 1, &value
))
228 ac_dump_reg(f
, offset
, value
, ~0);
231 static void si_dump_debug_registers(struct si_context
*sctx
, FILE *f
)
233 if (sctx
->screen
->b
.info
.drm_major
== 2 &&
234 sctx
->screen
->b
.info
.drm_minor
< 42)
235 return; /* no radeon support */
237 fprintf(f
, "Memory-mapped registers:\n");
238 si_dump_mmapped_reg(sctx
, f
, R_008010_GRBM_STATUS
);
240 /* No other registers can be read on DRM < 3.1.0. */
241 if (sctx
->screen
->b
.info
.drm_major
< 3 ||
242 sctx
->screen
->b
.info
.drm_minor
< 1) {
247 si_dump_mmapped_reg(sctx
, f
, R_008008_GRBM_STATUS2
);
248 si_dump_mmapped_reg(sctx
, f
, R_008014_GRBM_STATUS_SE0
);
249 si_dump_mmapped_reg(sctx
, f
, R_008018_GRBM_STATUS_SE1
);
250 si_dump_mmapped_reg(sctx
, f
, R_008038_GRBM_STATUS_SE2
);
251 si_dump_mmapped_reg(sctx
, f
, R_00803C_GRBM_STATUS_SE3
);
252 si_dump_mmapped_reg(sctx
, f
, R_00D034_SDMA0_STATUS_REG
);
253 si_dump_mmapped_reg(sctx
, f
, R_00D834_SDMA1_STATUS_REG
);
254 if (sctx
->b
.chip_class
<= VI
) {
255 si_dump_mmapped_reg(sctx
, f
, R_000E50_SRBM_STATUS
);
256 si_dump_mmapped_reg(sctx
, f
, R_000E4C_SRBM_STATUS2
);
257 si_dump_mmapped_reg(sctx
, f
, R_000E54_SRBM_STATUS3
);
259 si_dump_mmapped_reg(sctx
, f
, R_008680_CP_STAT
);
260 si_dump_mmapped_reg(sctx
, f
, R_008674_CP_STALLED_STAT1
);
261 si_dump_mmapped_reg(sctx
, f
, R_008678_CP_STALLED_STAT2
);
262 si_dump_mmapped_reg(sctx
, f
, R_008670_CP_STALLED_STAT3
);
263 si_dump_mmapped_reg(sctx
, f
, R_008210_CP_CPC_STATUS
);
264 si_dump_mmapped_reg(sctx
, f
, R_008214_CP_CPC_BUSY_STAT
);
265 si_dump_mmapped_reg(sctx
, f
, R_008218_CP_CPC_STALLED_STAT1
);
266 si_dump_mmapped_reg(sctx
, f
, R_00821C_CP_CPF_STATUS
);
267 si_dump_mmapped_reg(sctx
, f
, R_008220_CP_CPF_BUSY_STAT
);
268 si_dump_mmapped_reg(sctx
, f
, R_008224_CP_CPF_STALLED_STAT1
);
272 struct si_log_chunk_cs
{
273 struct si_context
*ctx
;
274 struct si_saved_cs
*cs
;
276 unsigned gfx_begin
, gfx_end
;
279 static void si_log_chunk_type_cs_destroy(void *data
)
281 struct si_log_chunk_cs
*chunk
= data
;
282 si_saved_cs_reference(&chunk
->cs
, NULL
);
286 static void si_parse_current_ib(FILE *f
, struct radeon_winsys_cs
*cs
,
287 unsigned begin
, unsigned end
,
288 int *last_trace_id
, unsigned trace_id_count
,
289 const char *name
, enum chip_class chip_class
)
291 unsigned orig_end
= end
;
293 assert(begin
<= end
);
295 fprintf(f
, "------------------ %s begin (dw = %u) ------------------\n",
298 for (unsigned prev_idx
= 0; prev_idx
< cs
->num_prev
; ++prev_idx
) {
299 struct radeon_winsys_cs_chunk
*chunk
= &cs
->prev
[prev_idx
];
301 if (begin
< chunk
->cdw
) {
302 ac_parse_ib_chunk(f
, chunk
->buf
+ begin
,
303 MIN2(end
, chunk
->cdw
) - begin
,
304 last_trace_id
, trace_id_count
,
305 chip_class
, NULL
, NULL
);
308 if (end
<= chunk
->cdw
)
311 if (begin
< chunk
->cdw
)
312 fprintf(f
, "\n---------- Next %s Chunk ----------\n\n",
315 begin
-= MIN2(begin
, chunk
->cdw
);
319 assert(end
<= cs
->current
.cdw
);
321 ac_parse_ib_chunk(f
, cs
->current
.buf
+ begin
, end
- begin
, last_trace_id
,
322 trace_id_count
, chip_class
, NULL
, NULL
);
324 fprintf(f
, "------------------- %s end (dw = %u) -------------------\n\n",
328 static void si_log_chunk_type_cs_print(void *data
, FILE *f
)
330 struct si_log_chunk_cs
*chunk
= data
;
331 struct si_context
*ctx
= chunk
->ctx
;
332 struct si_saved_cs
*scs
= chunk
->cs
;
333 int last_trace_id
= -1;
335 /* We are expecting that the ddebug pipe has already
336 * waited for the context, so this buffer should be idle.
337 * If the GPU is hung, there is no point in waiting for it.
339 uint32_t *map
= ctx
->b
.ws
->buffer_map(scs
->trace_buf
->buf
,
341 PIPE_TRANSFER_UNSYNCHRONIZED
|
344 last_trace_id
= map
[0];
346 if (chunk
->gfx_end
!= chunk
->gfx_begin
) {
347 if (chunk
->gfx_begin
== 0) {
348 if (ctx
->init_config
)
349 ac_parse_ib(f
, ctx
->init_config
->pm4
, ctx
->init_config
->ndw
,
350 NULL
, 0, "IB2: Init config", ctx
->b
.chip_class
,
353 if (ctx
->init_config_gs_rings
)
354 ac_parse_ib(f
, ctx
->init_config_gs_rings
->pm4
,
355 ctx
->init_config_gs_rings
->ndw
,
356 NULL
, 0, "IB2: Init GS rings", ctx
->b
.chip_class
,
361 ac_parse_ib(f
, scs
->gfx
.ib
+ chunk
->gfx_begin
,
362 chunk
->gfx_end
- chunk
->gfx_begin
,
363 &last_trace_id
, map
? 1 : 0, "IB", ctx
->b
.chip_class
,
366 si_parse_current_ib(f
, ctx
->b
.gfx
.cs
, chunk
->gfx_begin
,
367 chunk
->gfx_end
, &last_trace_id
, map
? 1 : 0,
368 "IB", ctx
->b
.chip_class
);
372 if (chunk
->dump_bo_list
) {
373 fprintf(f
, "Flushing.\n\n");
374 si_dump_bo_list(ctx
, &scs
->gfx
, f
);
378 static const struct u_log_chunk_type si_log_chunk_type_cs
= {
379 .destroy
= si_log_chunk_type_cs_destroy
,
380 .print
= si_log_chunk_type_cs_print
,
383 static void si_log_cs(struct si_context
*ctx
, struct u_log_context
*log
,
386 assert(ctx
->current_saved_cs
);
388 struct si_saved_cs
*scs
= ctx
->current_saved_cs
;
389 unsigned gfx_cur
= ctx
->b
.gfx
.cs
->prev_dw
+ ctx
->b
.gfx
.cs
->current
.cdw
;
392 gfx_cur
== scs
->gfx_last_dw
)
395 struct si_log_chunk_cs
*chunk
= calloc(1, sizeof(*chunk
));
398 si_saved_cs_reference(&chunk
->cs
, scs
);
399 chunk
->dump_bo_list
= dump_bo_list
;
401 chunk
->gfx_begin
= scs
->gfx_last_dw
;
402 chunk
->gfx_end
= gfx_cur
;
403 scs
->gfx_last_dw
= gfx_cur
;
405 u_log_chunk(log
, &si_log_chunk_type_cs
, chunk
);
408 void si_auto_log_cs(void *data
, struct u_log_context
*log
)
410 struct si_context
*ctx
= (struct si_context
*)data
;
411 si_log_cs(ctx
, log
, false);
414 void si_log_hw_flush(struct si_context
*sctx
)
419 si_log_cs(sctx
, sctx
->b
.log
, true);
422 static const char *priority_to_string(enum radeon_bo_priority priority
)
424 #define ITEM(x) [RADEON_PRIO_##x] = #x
425 static const char *table
[64] = {
428 ITEM(SO_FILLED_SIZE
),
442 ITEM(SAMPLER_BUFFER
),
444 ITEM(SHADER_RW_BUFFER
),
445 ITEM(COMPUTE_GLOBAL
),
446 ITEM(SAMPLER_TEXTURE
),
447 ITEM(SHADER_RW_IMAGE
),
448 ITEM(SAMPLER_TEXTURE_MSAA
),
451 ITEM(COLOR_BUFFER_MSAA
),
452 ITEM(DEPTH_BUFFER_MSAA
),
458 ITEM(SCRATCH_BUFFER
),
462 assert(priority
< ARRAY_SIZE(table
));
463 return table
[priority
];
466 static int bo_list_compare_va(const struct radeon_bo_list_item
*a
,
467 const struct radeon_bo_list_item
*b
)
469 return a
->vm_address
< b
->vm_address
? -1 :
470 a
->vm_address
> b
->vm_address
? 1 : 0;
473 static void si_dump_bo_list(struct si_context
*sctx
,
474 const struct radeon_saved_cs
*saved
, FILE *f
)
481 /* Sort the list according to VM adddresses first. */
482 qsort(saved
->bo_list
, saved
->bo_count
,
483 sizeof(saved
->bo_list
[0]), (void*)bo_list_compare_va
);
485 fprintf(f
, "Buffer list (in units of pages = 4kB):\n"
486 COLOR_YELLOW
" Size VM start page "
487 "VM end page Usage" COLOR_RESET
"\n");
489 for (i
= 0; i
< saved
->bo_count
; i
++) {
490 /* Note: Buffer sizes are expected to be aligned to 4k by the winsys. */
491 const unsigned page_size
= sctx
->b
.screen
->info
.gart_page_size
;
492 uint64_t va
= saved
->bo_list
[i
].vm_address
;
493 uint64_t size
= saved
->bo_list
[i
].bo_size
;
496 /* If there's unused virtual memory between 2 buffers, print it. */
498 uint64_t previous_va_end
= saved
->bo_list
[i
-1].vm_address
+
499 saved
->bo_list
[i
-1].bo_size
;
501 if (va
> previous_va_end
) {
502 fprintf(f
, " %10"PRIu64
" -- hole --\n",
503 (va
- previous_va_end
) / page_size
);
507 /* Print the buffer. */
508 fprintf(f
, " %10"PRIu64
" 0x%013"PRIX64
" 0x%013"PRIX64
" ",
509 size
/ page_size
, va
/ page_size
, (va
+ size
) / page_size
);
511 /* Print the usage. */
512 for (j
= 0; j
< 64; j
++) {
513 if (!(saved
->bo_list
[i
].priority_usage
& (1ull << j
)))
516 fprintf(f
, "%s%s", !hit
? "" : ", ", priority_to_string(j
));
521 fprintf(f
, "\nNote: The holes represent memory not used by the IB.\n"
522 " Other buffers can still be allocated there.\n\n");
525 static void si_dump_framebuffer(struct si_context
*sctx
, struct u_log_context
*log
)
527 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
528 struct r600_texture
*rtex
;
531 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
532 if (!state
->cbufs
[i
])
535 rtex
= (struct r600_texture
*)state
->cbufs
[i
]->texture
;
536 u_log_printf(log
, COLOR_YELLOW
"Color buffer %i:" COLOR_RESET
"\n", i
);
537 r600_print_texture_info(sctx
->b
.screen
, rtex
, log
);
538 u_log_printf(log
, "\n");
542 rtex
= (struct r600_texture
*)state
->zsbuf
->texture
;
543 u_log_printf(log
, COLOR_YELLOW
"Depth-stencil buffer:" COLOR_RESET
"\n");
544 r600_print_texture_info(sctx
->b
.screen
, rtex
, log
);
545 u_log_printf(log
, "\n");
549 typedef unsigned (*slot_remap_func
)(unsigned);
551 struct si_log_chunk_desc_list
{
552 /** Pointer to memory map of buffer where the list is uploader */
554 /** Reference of buffer where the list is uploaded, so that gpu_list
556 struct r600_resource
*buf
;
558 const char *shader_name
;
559 const char *elem_name
;
560 slot_remap_func slot_remap
;
561 unsigned element_dw_size
;
562 unsigned num_elements
;
568 si_log_chunk_desc_list_destroy(void *data
)
570 struct si_log_chunk_desc_list
*chunk
= data
;
571 r600_resource_reference(&chunk
->buf
, NULL
);
576 si_log_chunk_desc_list_print(void *data
, FILE *f
)
578 struct si_log_chunk_desc_list
*chunk
= data
;
580 for (unsigned i
= 0; i
< chunk
->num_elements
; i
++) {
581 unsigned cpu_dw_offset
= i
* chunk
->element_dw_size
;
582 unsigned gpu_dw_offset
= chunk
->slot_remap(i
) * chunk
->element_dw_size
;
583 const char *list_note
= chunk
->gpu_list
? "GPU list" : "CPU list";
584 uint32_t *cpu_list
= chunk
->list
+ cpu_dw_offset
;
585 uint32_t *gpu_list
= chunk
->gpu_list
? chunk
->gpu_list
+ gpu_dw_offset
: cpu_list
;
587 fprintf(f
, COLOR_GREEN
"%s%s slot %u (%s):" COLOR_RESET
"\n",
588 chunk
->shader_name
, chunk
->elem_name
, i
, list_note
);
590 switch (chunk
->element_dw_size
) {
592 for (unsigned j
= 0; j
< 4; j
++)
593 ac_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
594 gpu_list
[j
], 0xffffffff);
597 for (unsigned j
= 0; j
< 8; j
++)
598 ac_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
599 gpu_list
[j
], 0xffffffff);
601 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
602 for (unsigned j
= 0; j
< 4; j
++)
603 ac_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
604 gpu_list
[4+j
], 0xffffffff);
607 for (unsigned j
= 0; j
< 8; j
++)
608 ac_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
609 gpu_list
[j
], 0xffffffff);
611 fprintf(f
, COLOR_CYAN
" Buffer:" COLOR_RESET
"\n");
612 for (unsigned j
= 0; j
< 4; j
++)
613 ac_dump_reg(f
, R_008F00_SQ_BUF_RSRC_WORD0
+ j
*4,
614 gpu_list
[4+j
], 0xffffffff);
616 fprintf(f
, COLOR_CYAN
" FMASK:" COLOR_RESET
"\n");
617 for (unsigned j
= 0; j
< 8; j
++)
618 ac_dump_reg(f
, R_008F10_SQ_IMG_RSRC_WORD0
+ j
*4,
619 gpu_list
[8+j
], 0xffffffff);
621 fprintf(f
, COLOR_CYAN
" Sampler state:" COLOR_RESET
"\n");
622 for (unsigned j
= 0; j
< 4; j
++)
623 ac_dump_reg(f
, R_008F30_SQ_IMG_SAMP_WORD0
+ j
*4,
624 gpu_list
[12+j
], 0xffffffff);
628 if (memcmp(gpu_list
, cpu_list
, chunk
->element_dw_size
* 4) != 0) {
629 fprintf(f
, COLOR_RED
"!!!!! This slot was corrupted in GPU memory !!!!!"
638 static const struct u_log_chunk_type si_log_chunk_type_descriptor_list
= {
639 .destroy
= si_log_chunk_desc_list_destroy
,
640 .print
= si_log_chunk_desc_list_print
,
643 static void si_dump_descriptor_list(struct si_descriptors
*desc
,
644 const char *shader_name
,
645 const char *elem_name
,
646 unsigned element_dw_size
,
647 unsigned num_elements
,
648 slot_remap_func slot_remap
,
649 struct u_log_context
*log
)
654 struct si_log_chunk_desc_list
*chunk
=
655 CALLOC_VARIANT_LENGTH_STRUCT(si_log_chunk_desc_list
,
656 4 * element_dw_size
* num_elements
);
657 chunk
->shader_name
= shader_name
;
658 chunk
->elem_name
= elem_name
;
659 chunk
->element_dw_size
= element_dw_size
;
660 chunk
->num_elements
= num_elements
;
661 chunk
->slot_remap
= slot_remap
;
663 r600_resource_reference(&chunk
->buf
, desc
->buffer
);
664 chunk
->gpu_list
= desc
->gpu_list
;
666 for (unsigned i
= 0; i
< num_elements
; ++i
) {
667 memcpy(&chunk
->list
[i
* element_dw_size
],
668 &desc
->list
[slot_remap(i
) * element_dw_size
],
669 4 * element_dw_size
);
672 u_log_chunk(log
, &si_log_chunk_type_descriptor_list
, chunk
);
675 static unsigned si_identity(unsigned slot
)
680 static void si_dump_descriptors(struct si_context
*sctx
,
681 enum pipe_shader_type processor
,
682 const struct tgsi_shader_info
*info
,
683 struct u_log_context
*log
)
685 struct si_descriptors
*descs
=
686 &sctx
->descriptors
[SI_DESCS_FIRST_SHADER
+
687 processor
* SI_NUM_SHADER_DESCS
];
688 static const char *shader_name
[] = {"VS", "PS", "GS", "TCS", "TES", "CS"};
689 const char *name
= shader_name
[processor
];
690 unsigned enabled_constbuf
, enabled_shaderbuf
, enabled_samplers
;
691 unsigned enabled_images
;
694 enabled_constbuf
= info
->const_buffers_declared
;
695 enabled_shaderbuf
= info
->shader_buffers_declared
;
696 enabled_samplers
= info
->samplers_declared
;
697 enabled_images
= info
->images_declared
;
699 enabled_constbuf
= sctx
->const_and_shader_buffers
[processor
].enabled_mask
>>
700 SI_NUM_SHADER_BUFFERS
;
701 enabled_shaderbuf
= sctx
->const_and_shader_buffers
[processor
].enabled_mask
&
702 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
);
703 enabled_shaderbuf
= util_bitreverse(enabled_shaderbuf
) >>
704 (32 - SI_NUM_SHADER_BUFFERS
);
705 enabled_samplers
= sctx
->samplers
[processor
].views
.enabled_mask
;
706 enabled_images
= sctx
->images
[processor
].enabled_mask
;
709 if (processor
== PIPE_SHADER_VERTEX
) {
710 assert(info
); /* only CS may not have an info struct */
712 si_dump_descriptor_list(&sctx
->vertex_buffers
, name
,
713 " - Vertex buffer", 4, info
->num_inputs
,
717 si_dump_descriptor_list(&descs
[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
],
718 name
, " - Constant buffer", 4,
719 util_last_bit(enabled_constbuf
),
720 si_get_constbuf_slot
, log
);
721 si_dump_descriptor_list(&descs
[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS
],
722 name
, " - Shader buffer", 4,
723 util_last_bit(enabled_shaderbuf
),
724 si_get_shaderbuf_slot
, log
);
725 si_dump_descriptor_list(&descs
[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
],
726 name
, " - Sampler", 16,
727 util_last_bit(enabled_samplers
),
728 si_get_sampler_slot
, log
);
729 si_dump_descriptor_list(&descs
[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES
],
731 util_last_bit(enabled_images
),
732 si_get_image_slot
, log
);
735 static void si_dump_gfx_descriptors(struct si_context
*sctx
,
736 const struct si_shader_ctx_state
*state
,
737 struct u_log_context
*log
)
739 if (!state
->cso
|| !state
->current
)
742 si_dump_descriptors(sctx
, state
->cso
->type
, &state
->cso
->info
, log
);
745 static void si_dump_compute_descriptors(struct si_context
*sctx
,
746 struct u_log_context
*log
)
748 if (!sctx
->cs_shader_state
.program
||
749 sctx
->cs_shader_state
.program
!= sctx
->cs_shader_state
.emitted_program
)
752 si_dump_descriptors(sctx
, PIPE_SHADER_COMPUTE
, NULL
, log
);
755 struct si_shader_inst
{
756 char text
[160]; /* one disasm line */
757 unsigned offset
; /* instruction offset */
758 unsigned size
; /* instruction size = 4 or 8 */
761 /* Split a disassembly string into lines and add them to the array pointed
762 * to by "instructions". */
763 static void si_add_split_disasm(const char *disasm
,
766 struct si_shader_inst
*instructions
)
768 struct si_shader_inst
*last_inst
= *num
? &instructions
[*num
- 1] : NULL
;
771 while ((next
= strchr(disasm
, '\n'))) {
772 struct si_shader_inst
*inst
= &instructions
[*num
];
773 unsigned len
= next
- disasm
;
775 assert(len
< ARRAY_SIZE(inst
->text
));
776 memcpy(inst
->text
, disasm
, len
);
778 inst
->offset
= last_inst
? last_inst
->offset
+ last_inst
->size
: 0;
780 const char *semicolon
= strchr(disasm
, ';');
782 /* More than 16 chars after ";" means the instruction is 8 bytes long. */
783 inst
->size
= next
- semicolon
> 16 ? 8 : 4;
785 snprintf(inst
->text
+ len
, ARRAY_SIZE(inst
->text
) - len
,
786 " [PC=0x%"PRIx64
", off=%u, size=%u]",
787 start_addr
+ inst
->offset
, inst
->offset
, inst
->size
);
795 #define MAX_WAVES_PER_CHIP (64 * 40)
797 struct si_wave_info
{
798 unsigned se
; /* shader engine */
799 unsigned sh
; /* shader array */
800 unsigned cu
; /* compute unit */
804 uint64_t pc
; /* program counter */
808 bool matched
; /* whether the wave is used by a currently-bound shader */
811 static int compare_wave(const void *p1
, const void *p2
)
813 struct si_wave_info
*w1
= (struct si_wave_info
*)p1
;
814 struct si_wave_info
*w2
= (struct si_wave_info
*)p2
;
816 /* Sort waves according to PC and then SE, SH, CU, etc. */
833 if (w1
->simd
< w2
->simd
)
835 if (w1
->simd
> w2
->simd
)
837 if (w1
->wave
< w2
->wave
)
839 if (w1
->wave
> w2
->wave
)
845 /* Return wave information. "waves" should be a large enough array. */
846 static unsigned si_get_wave_info(struct si_wave_info waves
[MAX_WAVES_PER_CHIP
])
849 unsigned num_waves
= 0;
851 FILE *p
= popen("umr -wa", "r");
855 if (!fgets(line
, sizeof(line
), p
) ||
856 strncmp(line
, "SE", 2) != 0) {
861 while (fgets(line
, sizeof(line
), p
)) {
862 struct si_wave_info
*w
;
863 uint32_t pc_hi
, pc_lo
, exec_hi
, exec_lo
;
865 assert(num_waves
< MAX_WAVES_PER_CHIP
);
866 w
= &waves
[num_waves
];
868 if (sscanf(line
, "%u %u %u %u %u %x %x %x %x %x %x %x",
869 &w
->se
, &w
->sh
, &w
->cu
, &w
->simd
, &w
->wave
,
870 &w
->status
, &pc_hi
, &pc_lo
, &w
->inst_dw0
,
871 &w
->inst_dw1
, &exec_hi
, &exec_lo
) == 12) {
872 w
->pc
= ((uint64_t)pc_hi
<< 32) | pc_lo
;
873 w
->exec
= ((uint64_t)exec_hi
<< 32) | exec_lo
;
879 qsort(waves
, num_waves
, sizeof(struct si_wave_info
), compare_wave
);
885 /* If the shader is being executed, print its asm instructions, and annotate
886 * those that are being executed right now with information about waves that
887 * execute them. This is most useful during a GPU hang.
889 static void si_print_annotated_shader(struct si_shader
*shader
,
890 struct si_wave_info
*waves
,
894 if (!shader
|| !shader
->binary
.disasm_string
)
897 uint64_t start_addr
= shader
->bo
->gpu_address
;
898 uint64_t end_addr
= start_addr
+ shader
->bo
->b
.b
.width0
;
901 /* See if any wave executes the shader. */
902 for (i
= 0; i
< num_waves
; i
++) {
903 if (start_addr
<= waves
[i
].pc
&& waves
[i
].pc
<= end_addr
)
907 return; /* the shader is not being executed */
909 /* Remember the first found wave. The waves are sorted according to PC. */
913 /* Get the list of instructions.
914 * Buffer size / 4 is the upper bound of the instruction count.
916 unsigned num_inst
= 0;
917 struct si_shader_inst
*instructions
=
918 calloc(shader
->bo
->b
.b
.width0
/ 4, sizeof(struct si_shader_inst
));
920 if (shader
->prolog
) {
921 si_add_split_disasm(shader
->prolog
->binary
.disasm_string
,
922 start_addr
, &num_inst
, instructions
);
924 if (shader
->previous_stage
) {
925 si_add_split_disasm(shader
->previous_stage
->binary
.disasm_string
,
926 start_addr
, &num_inst
, instructions
);
928 if (shader
->prolog2
) {
929 si_add_split_disasm(shader
->prolog2
->binary
.disasm_string
,
930 start_addr
, &num_inst
, instructions
);
932 si_add_split_disasm(shader
->binary
.disasm_string
,
933 start_addr
, &num_inst
, instructions
);
934 if (shader
->epilog
) {
935 si_add_split_disasm(shader
->epilog
->binary
.disasm_string
,
936 start_addr
, &num_inst
, instructions
);
939 fprintf(f
, COLOR_YELLOW
"%s - annotated disassembly:" COLOR_RESET
"\n",
940 si_get_shader_name(shader
, shader
->selector
->type
));
942 /* Print instructions with annotations. */
943 for (i
= 0; i
< num_inst
; i
++) {
944 struct si_shader_inst
*inst
= &instructions
[i
];
946 fprintf(f
, "%s\n", inst
->text
);
948 /* Print which waves execute the instruction right now. */
949 while (num_waves
&& start_addr
+ inst
->offset
== waves
->pc
) {
951 " " COLOR_GREEN
"^ SE%u SH%u CU%u "
952 "SIMD%u WAVE%u EXEC=%016"PRIx64
" ",
953 waves
->se
, waves
->sh
, waves
->cu
, waves
->simd
,
954 waves
->wave
, waves
->exec
);
956 if (inst
->size
== 4) {
957 fprintf(f
, "INST32=%08X" COLOR_RESET
"\n",
960 fprintf(f
, "INST64=%08X %08X" COLOR_RESET
"\n",
961 waves
->inst_dw0
, waves
->inst_dw1
);
964 waves
->matched
= true;
974 static void si_dump_annotated_shaders(struct si_context
*sctx
, FILE *f
)
976 struct si_wave_info waves
[MAX_WAVES_PER_CHIP
];
977 unsigned num_waves
= si_get_wave_info(waves
);
979 fprintf(f
, COLOR_CYAN
"The number of active waves = %u" COLOR_RESET
982 si_print_annotated_shader(sctx
->vs_shader
.current
, waves
, num_waves
, f
);
983 si_print_annotated_shader(sctx
->tcs_shader
.current
, waves
, num_waves
, f
);
984 si_print_annotated_shader(sctx
->tes_shader
.current
, waves
, num_waves
, f
);
985 si_print_annotated_shader(sctx
->gs_shader
.current
, waves
, num_waves
, f
);
986 si_print_annotated_shader(sctx
->ps_shader
.current
, waves
, num_waves
, f
);
988 /* Print waves executing shaders that are not currently bound. */
991 for (i
= 0; i
< num_waves
; i
++) {
992 if (waves
[i
].matched
)
996 fprintf(f
, COLOR_CYAN
997 "Waves not executing currently-bound shaders:"
1001 fprintf(f
, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016"PRIx64
1002 " INST=%08X %08X PC=%"PRIx64
"\n",
1003 waves
[i
].se
, waves
[i
].sh
, waves
[i
].cu
, waves
[i
].simd
,
1004 waves
[i
].wave
, waves
[i
].exec
, waves
[i
].inst_dw0
,
1005 waves
[i
].inst_dw1
, waves
[i
].pc
);
1011 static void si_dump_command(const char *title
, const char *command
, FILE *f
)
1015 FILE *p
= popen(command
, "r");
1019 fprintf(f
, COLOR_YELLOW
"%s: " COLOR_RESET
"\n", title
);
1020 while (fgets(line
, sizeof(line
), p
))
1026 static void si_dump_debug_state(struct pipe_context
*ctx
, FILE *f
,
1029 struct si_context
*sctx
= (struct si_context
*)ctx
;
1032 u_log_flush(sctx
->b
.log
);
1034 if (flags
& PIPE_DUMP_DEVICE_STATUS_REGISTERS
) {
1035 si_dump_debug_registers(sctx
, f
);
1037 si_dump_annotated_shaders(sctx
, f
);
1038 si_dump_command("Active waves (raw data)", "umr -wa | column -t", f
);
1039 si_dump_command("Wave information", "umr -O bits -wa", f
);
1043 void si_log_draw_state(struct si_context
*sctx
, struct u_log_context
*log
)
1048 si_dump_framebuffer(sctx
, log
);
1050 si_dump_gfx_shader(sctx
, &sctx
->vs_shader
, log
);
1051 si_dump_gfx_shader(sctx
, &sctx
->tcs_shader
, log
);
1052 si_dump_gfx_shader(sctx
, &sctx
->tes_shader
, log
);
1053 si_dump_gfx_shader(sctx
, &sctx
->gs_shader
, log
);
1054 si_dump_gfx_shader(sctx
, &sctx
->ps_shader
, log
);
1056 si_dump_descriptor_list(&sctx
->descriptors
[SI_DESCS_RW_BUFFERS
],
1057 "", "RW buffers", 4, SI_NUM_RW_BUFFERS
,
1059 si_dump_gfx_descriptors(sctx
, &sctx
->vs_shader
, log
);
1060 si_dump_gfx_descriptors(sctx
, &sctx
->tcs_shader
, log
);
1061 si_dump_gfx_descriptors(sctx
, &sctx
->tes_shader
, log
);
1062 si_dump_gfx_descriptors(sctx
, &sctx
->gs_shader
, log
);
1063 si_dump_gfx_descriptors(sctx
, &sctx
->ps_shader
, log
);
1066 void si_log_compute_state(struct si_context
*sctx
, struct u_log_context
*log
)
1071 si_dump_compute_shader(&sctx
->cs_shader_state
, log
);
1072 si_dump_compute_descriptors(sctx
, log
);
1075 static void si_dump_dma(struct si_context
*sctx
,
1076 struct radeon_saved_cs
*saved
, FILE *f
)
1078 static const char ib_name
[] = "sDMA IB";
1081 si_dump_bo_list(sctx
, saved
, f
);
1083 fprintf(f
, "------------------ %s begin ------------------\n", ib_name
);
1085 for (i
= 0; i
< saved
->num_dw
; ++i
) {
1086 fprintf(f
, " %08x\n", saved
->ib
[i
]);
1089 fprintf(f
, "------------------- %s end -------------------\n", ib_name
);
1092 fprintf(f
, "SDMA Dump Done.\n");
1095 static bool si_vm_fault_occured(struct si_context
*sctx
, uint64_t *out_addr
)
1100 uint64_t timestamp
= 0;
1103 FILE *p
= popen("dmesg", "r");
1107 while (fgets(line
, sizeof(line
), p
)) {
1110 if (!line
[0] || line
[0] == '\n')
1113 /* Get the timestamp. */
1114 if (sscanf(line
, "[%u.%u]", &sec
, &usec
) != 2) {
1115 static bool hit
= false;
1117 fprintf(stderr
, "%s: failed to parse line '%s'\n",
1123 timestamp
= sec
* 1000000ull + usec
;
1125 /* If just updating the timestamp. */
1129 /* Process messages only if the timestamp is newer. */
1130 if (timestamp
<= sctx
->dmesg_timestamp
)
1133 /* Only process the first VM fault. */
1137 /* Remove trailing \n */
1139 if (len
&& line
[len
-1] == '\n')
1142 /* Get the message part. */
1143 msg
= strchr(line
, ']');
1150 const char *header_line
, *addr_line_prefix
, *addr_line_format
;
1152 if (sctx
->b
.chip_class
>= GFX9
) {
1154 * ..: [gfxhub] VMC page fault (src_id:0 ring:158 vm_id:2 pas_id:0)
1155 * ..: at page 0x0000000219f8f000 from 27
1156 * ..: VM_L2_PROTECTION_FAULT_STATUS:0x0020113C
1158 header_line
= "VMC page fault";
1159 addr_line_prefix
= " at page";
1160 addr_line_format
= "%"PRIx64
;
1162 header_line
= "GPU fault detected:";
1163 addr_line_prefix
= "VM_CONTEXT1_PROTECTION_FAULT_ADDR";
1164 addr_line_format
= "%"PRIX64
;
1169 if (strstr(msg
, header_line
))
1173 msg
= strstr(msg
, addr_line_prefix
);
1175 msg
= strstr(msg
, "0x");
1178 if (sscanf(msg
, addr_line_format
, out_addr
) == 1)
1190 if (timestamp
> sctx
->dmesg_timestamp
)
1191 sctx
->dmesg_timestamp
= timestamp
;
1195 void si_check_vm_faults(struct r600_common_context
*ctx
,
1196 struct radeon_saved_cs
*saved
, enum ring_type ring
)
1198 struct si_context
*sctx
= (struct si_context
*)ctx
;
1199 struct pipe_screen
*screen
= sctx
->b
.b
.screen
;
1202 char cmd_line
[4096];
1204 if (!si_vm_fault_occured(sctx
, &addr
))
1207 f
= dd_get_debug_file(false);
1211 fprintf(f
, "VM fault report.\n\n");
1212 if (os_get_command_line(cmd_line
, sizeof(cmd_line
)))
1213 fprintf(f
, "Command: %s\n", cmd_line
);
1214 fprintf(f
, "Driver vendor: %s\n", screen
->get_vendor(screen
));
1215 fprintf(f
, "Device vendor: %s\n", screen
->get_device_vendor(screen
));
1216 fprintf(f
, "Device name: %s\n\n", screen
->get_name(screen
));
1217 fprintf(f
, "Failing VM page: 0x%08"PRIx64
"\n\n", addr
);
1219 if (sctx
->apitrace_call_number
)
1220 fprintf(f
, "Last apitrace call: %u\n\n",
1221 sctx
->apitrace_call_number
);
1225 struct u_log_context log
;
1226 u_log_context_init(&log
);
1228 si_log_draw_state(sctx
, &log
);
1229 si_log_compute_state(sctx
, &log
);
1231 u_log_new_page_print(&log
, f
);
1232 u_log_context_destroy(&log
);
1236 si_dump_dma(sctx
, saved
, f
);
1245 fprintf(stderr
, "Detected a VM fault, exiting...\n");
1249 void si_init_debug_functions(struct si_context
*sctx
)
1251 sctx
->b
.b
.dump_debug_state
= si_dump_debug_state
;
1252 sctx
->b
.check_vm_faults
= si_check_vm_faults
;
1254 /* Set the initial dmesg timestamp for this context, so that
1255 * only new messages will be checked for VM faults.
1257 if (sctx
->screen
->b
.debug_flags
& DBG_CHECK_VM
)
1258 si_vm_fault_occured(sctx
, NULL
);